JP4887575B2 - Manufacturing method of high-density multilayer build-up wiring board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a high-density multilayer buildup wiring board in which openings having different wiring layer structures are processed using an ultraviolet laser and excellent in connection reliability with a mounted semiconductor chip.
[0002]
[Prior art]
In recent years, as represented by personal computers and the like, electronic devices are required to be smaller and thinner. For this reason, a semiconductor device substrate used inside is also required to be reduced in size and thickness. These semiconductor device substrates have semiconductor chips and other components mounted thereon, and are mounted on the semiconductor device substrate as a parent substrate in the form of a ball grid array (BGA), pin grid array (PGA), or the like. In many cases, it is also used as a parent substrate.
In order to realize miniaturization and thinning, so-called high-density wiring is required in which the wiring width is narrow, the gap is small, the wiring layers are multilayered, and the vias connecting the wiring layers are reduced in diameter. There has been a demand for a highly reliable semiconductor device that does not cause connection failure or insulation failure even when the density is increased.
[0003]
A multilayer build-up wiring board using a build-up method is known as a substrate for a semiconductor device that meets these requirements. In this method, a wiring layer is formed on an insulative core substrate, an insulating layer is formed thereon, a wiring layer is further formed thereon, and a step of forming an insulating layer is repeated, whereby a multilayer is formed. A build-up wiring board is formed.
This multilayer build-up wiring board is suitable for high-density wiring because a large number of vias can be formed between arbitrary layers. Vias are becoming smaller in diameter with high density wiring, and lasers are increasingly used as processing methods. Further, by filling the vias with metal and forming vias on the vias, higher density wiring is achieved.
[0004]
An example of a multilayer buildup wiring board using the buildup method will be described with reference to FIG. First, as shown in FIG. 2A, a wiring layer 52 is formed on an insulating substrate 51 made of a rigid material such as a glass epoxy substrate. In this case, a method of forming a wiring layer by etching using a double-sided copper-clad glass epoxy substrate may be simple. In the wiring layer, wiring patterns, via lands, and the like are formed. Subsequently, as illustrated in FIG. 2B, a sheet-like insulating resin is attached to form the insulating layer 53.
In forming the insulating layer, a method of sticking a sheet-like resin is preferable from the viewpoint that the insulating layer can be easily formed with a uniform thickness, but a method of applying a liquid resin may also be used. As a coating method in that case, a screen printing method, a curtain coating method, or a spin coating method is applied. Other materials for the insulating layer include polyimide resin and acrylic resin.
[0005]
Then, the insulating resin above the lands 54 forming the vias is removed by irradiation with a laser. By forming via holes by laser processing in this way, fine vias can be obtained. As the laser, a laser such as a YAG laser, a carbon dioxide gas laser, or an excimer laser is used.
And the inside of a hole is wash | cleaned by being immersed in potassium permanganate. By this cleaning, the residue adhering to the hole wall and the residue remaining at the bottom of the hole are removed.
Then, as shown in FIG. 2C, a copper layer is formed on the insulating layer 53 by electroless plating or electrolytic plating, a via 55 is provided, and the formed copper layer is etched to form a wiring layer 56. . At this time, the electroless plating is performed in order to impart conductivity to the insulating layer so that the electrolytic plating can be performed.
[0006]
Next, as shown in FIG. 2D, an insulating layer 57 is formed on the entire surface, and a portion where a via is formed is laser processed. The formation method may be the same as the method used in the step of FIG. Further, a through hole 58 for a through hole is formed using a drill.
Then, plating is performed in the same process as in FIG. 2C to form the via 59 and the through hole 60 (FIG. 2E). In this case, it is preferable that the hole diameter of the through hole 60 is as small as possible so as not to hinder the high density formation of the wiring layer.
Subsequently, the wiring layer 61 is formed by etching. At this time, the copper foil on the opposite surface is also etched to form the power source layer 62. And the solder resist 63 which protects the wiring layer 61 and the power supply layer 62 is provided, and a multilayer buildup wiring board is completed (FIG.2 (f)).
[0007]
By the way, in order to have high reliability as described above and high-density wiring, the following is required.
That is, as shown in FIG. 3, the wiring layer 72 is formed on the insulating substrate 71, and the insulating layer 73 is formed on the wiring layer. Via holes are formed in the insulating layer 73 by laser processing, and conductor layers and vias 74 and 79 are formed by plating. The via 74 has a shape embedded by plating.
Then, after the conductor layer is patterned by etching to form the wiring layer 75, an insulating layer 76 is further formed. Then, via holes are formed in the insulating layer, and conductor layers and vias 77 and 80 are similarly formed by plating. At this time, the via 77 is formed to overlap the via 74.
In this way, by forming vias on top of vias, the degree of freedom in design can be further improved, thus enabling high-density wiring.
Further, a solder resist 81 is formed on the wiring layer 78, and the pad portions 82 and 83 to which components and the like are connected are exposed.
[0008]
[Problems to be solved by the invention]
Based on the technical background as described above, as a result of researches conducted by the inventors to meet the above requirements all at once, the following problems became clear.
That is, as shown in FIG. 3, when laser processing is performed on the insulating layer on the via, in the lower part of the insulating layer 76, the 77 part of the via having the via 74 is processed, and the 80 part of the via having no via are processed. In this case, it cannot be formed under the same processing conditions. Alternatively, when a solder resist layer having an opening on the outer layer is to be formed by laser processing, an opening 82 on the pad formed on the via and an opening 83 on the pad not formed on the via. Cannot be formed under the same processing conditions.
[0009]
This means that an opening cannot be formed under the same processing conditions because a difference occurs in the heat capacity depending on the structure below the processing portion.
In other words, the opening formed on the via has a larger heat capacity because the via is filled with metal compared to the opening not formed on the via, so the energy of the ultraviolet laser is easily absorbed by the via, As a result, the insulating layer or solder resist residue tends to remain in the opening. On the other hand, the opening not formed on the via has a smaller heat capacity than the opening formed on the via, so the influence of energy absorption by the ultraviolet laser is large, and as a result, the conductor portion corresponding to the bottom of the opening Easy to take damage. Therefore, it is difficult to form the opening stably even if the opening is formed under the same processing conditions.
[0010]
The present invention has been made in view of the above-mentioned problems, and the problem is that a high-density multilayer build capable of performing high-density wiring and manufacturing a highly reliable multilayer printed wiring board is possible. It is in providing the manufacturing method of an up-wiring board.
[0011]
[Means for Solving the Problems]
In order to solve the above-described problem, according to the first aspect of the present invention, a plurality of wiring layers and insulating layers are alternately laminated on both surfaces of a core substrate in which through holes are formed, and the wiring layers are filled with metal. A part of the pad of the outer layer is formed on the via, and a solder resist layer having an opening is formed on the outer layer, and the pad is exposed from the opening. In the method for manufacturing a multilayer build-up wiring board, the opening is formed by using an ultraviolet laser, and the irradiation conditions are different between an opening on the pad formed on the via and an opening on the pad not formed on the via. It is characterized by processing.
[0012]
According to a second aspect of the present invention, a plurality of wiring layers and insulating layers are alternately laminated on both surfaces of a core substrate on which through holes are formed, and vias in which the wiring layers are filled with metal are interposed. A method for manufacturing a high-density multilayer build-up wiring board in which openings for vias are formed in the insulating layer on the upper wiring layer of the vias so that some openings are formed on the vias. In the method, the opening is processed using an ultraviolet laser under different irradiation conditions between an opening formed on the via and an opening on a land not formed on the via. Yes.
[0013]
That is, in the method for manufacturing a multilayer printed wiring board according to the present invention, when the opening is processed with a laser, the laser irradiation conditions are changed according to the structure below the processed portion to form the opening. As a result, appropriate processing according to the heat capacity of the lower structure can be performed, and a manufacturing method free from solder resist residue is obtained. Irradiation conditions include the number of pulses of laser light, energy density, and the like.
[0014]
The invention according to claim 3 of the present invention is characterized in that the different irradiation conditions are that the ultraviolet laser is irradiated in a pulsed manner and the number of pulses is different. It is a manufacturing method of a density multilayer buildup wiring board.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
1A and 1B are partial cross-sectional views showing an embodiment of a manufacturing process of a high-density multilayer build-up wiring board in the order of processes.
[0016]
First, using a double-sided copper-clad laminate in which a copper foil having a thickness of 18 μm is adhered to both sides of a 0.6 mm-thick insulating substrate 1 in which a glass cloth is impregnated with a bismaleimide-triazine resin, a hole diameter is measured by a drill Drilled 250 μm (not shown). And after performing electroless plating about 0.3 micrometer, electrolytic plating was performed. The thickness of the copper layer on both sides at this time was 27 μm. Thereafter, PSR-4000 (trade name; manufactured by Taiyo Ink Mfg. Co., Ltd.), which is an epoxy insulating resin, is filled into the plated through holes by screen printing, thermally cured, and both sides are lightened. The protruding part was smoothened by polishing.
Then, the first wiring layer 2 was formed by patterning the copper layers on both sides. The land which becomes the lower part of the via was etched so as to have a circular shape of 140 μm.
[0017]
In addition to the above-described subtractive method, an additive method is also used for forming the wiring layer.
As described above, the subtractive method forms a wiring layer by plating the entire surface, forming a resist for etching, patterning the resist, and etching the copper layer exposed from the resist. is there.
[0018]
The additive method includes a semi-additive method and a full additive method.
In the semi-additive method, a thin copper layer is formed by electroless plating, a plating resist is formed, the resist is patterned, and then the copper layer exposed from the resist is subjected to pattern plating. For example, there is a method of performing electrolytic plating using a copper layer as a plating electrode. Then, the resist is peeled off, and the entire surface is lightly etched to remove the thin copper layer covered with the resist and form a wiring layer.
[0019]
In the full additive method, a plating resist is formed on an insulating layer, the resist is patterned, and then pattern plating is performed on the copper layer exposed from the resist. Generally, it is performed by electroless plating.
[0020]
And here, the copper layer on both sides is subjected to oxidation treatment called blackening treatment, or further oxidation treatment, followed by reduction treatment, soft etching treatment, organic acid treatment such as citric acid, etc. It is preferable to carry out the treatment. This improves the adhesion between the first wiring layer and the next formed insulating layer interface.
[0021]
Next, PSR-4000 (trade name; solar ink), which is an epoxy-based insulating resin, is formed on the first wiring layer 2 subjected to the copper surface treatment so that the resin thickness when finished as the insulating layer 3 is 35 μm. (Manufactured by Manufacturing Co., Ltd.) was applied and thermally cured. Then, UV laser irradiation is performed, and a hole having a diameter of 140 μm on the first wiring layer is used as a stopper layer to perform drilling, so that the upper diameter of the insulating layer in the via forming portion is circular so that the diameter is 40 μm. Removal and holes were formed to form a final first build-up insulating layer. In this case, the laser processing conditions were such that the energy density was 2.0 J / cm ² and the number of pulses was such that a via lower diameter was 20% or more, which was 50% of the upper diameter. The actual lower diameter was 20 μm.
[0022]
Here, it is desirable to form a small hole for via, and a laser is used for this purpose.However, if the wavelength is too long, it is difficult to optically narrow the beam diameter, and when using a mask, Except for the narrowed part, the mask is lost, so there is a possibility that the irradiation energy becomes small.
Therefore, even when a mask is used, it is necessary to optically narrow the beam diameter to some extent. Therefore, it is desirable to use an ultraviolet wavelength laser so that the beam diameter can be optically reduced and easily reduced, and the irradiation energy per unit beam diameter can be easily secured.
[0023]
Next, after conducting a resin surface treatment with permanganic acid on both insulating layers, electroless plating and electrolytic plating were performed to form a conductor layer.
Next, an etching resist was applied on the conductor layer, exposed, developed, and etched, and the copper foils on both sides were patterned to form the second wiring layer 4. The via land provided in the second wiring layer uses a design pattern having a diameter of 140 μm as in the first wiring layer.
[0024]
Subsequently, the same material as that of the first build-up insulating layer was applied on the second wiring layers 4 on both sides so that the resin thickness at the time of finishing as the insulating layer 5 was 35 μm, and was thermally cured ( FIG. 1 (a)).
Then, the UV laser 9 is irradiated, the land on the second wiring layer is used as a stopper layer, the hole is drilled, the insulating layer in the via forming portion is removed in a circular shape with a diameter of 40 μm, and a hole is formed. A build-up insulating layer was formed (FIG. 1B). The laser processing conditions at this time are all energy density of 2.0 J / cm ² , and the number of pulses when forming the opening on the opening 7 formed on the via 6 is 45 pulses. Processing was performed under the condition that the number of pulses when forming the opening 8 not above was 35 pulses.
[0025]
And although the residue was confirmed visually, the residue was not confirmed in any of the opening part 7 and the opening part 8. FIG.
[0026]
Furthermore, in order to perform high-density wiring, it is desirable to adopt the following embodiment.
The first is to reduce the thickness of the wiring layer. This is because if the wiring layer is thick, it is difficult to perform high-precision patterning, and it is difficult to manufacture a high-density, highly reliable multilayer printed wiring board. In the case of the subtractive method, if the wiring layer is thick, the etching of the lower part is difficult to proceed when etching is performed, and a trapezoidal shape is formed. If etching time is lengthened, side etching will become large and the center part will have a constricted shape. Therefore, patterning with a narrow wiring width and a small gap is very difficult. In the case of the additive method, the pattern plating is performed in both the semi-additive method and the full additive method, so if the wiring density or the wiring is uneven in the plane, the plating thickness will vary, but the wiring layer As the thickness increases, this variation becomes larger, resulting in variations in electrical characteristics. Therefore, it is desired to make the wiring layer thin. Specifically, if the thickness is 10 μm or less, a stable wiring shape can be obtained by any of the subtractive and additive methods, which is preferable.
[0027]
The second is to reduce the land at the bottom of the via. This is necessary for high-density wiring, and specifically, it is preferably 140 μm or less.
[0028]
Thirdly, the difference between the lower diameter and the upper diameter of the via hole is reduced.
This means that plating or a combination of sputtering and plating is used as a means for forming a conductor layer on the via hole wall. However, if the lower diameter is small, the plating solution is difficult to enter the interior. Bubbles may remain inside and plating solution may not enter. Also, in the case of sputtering, it is difficult to adhere to the inside, so that a conductor layer is not sufficiently formed on the hole wall, and there is a risk of poor connection. Therefore, we try to obtain a lower diameter of a certain size, but if the size of the lower diameter is too small compared to the upper diameter, the upper part becomes a shape that is significantly widened, and the land at the upper part of the via becomes larger, This is because the wiring density decreases. Specifically, it is preferable that the lower diameter is 50% or more of the upper diameter because high-density wiring can be performed while satisfying connection reliability.
[0029]
If it exceeds 100%, the lower diameter becomes larger, and as described above, a conductor layer may not be sufficiently formed on the hole wall, which may result in poor connection. Note that in ordinary laser processing, the lower diameter is not larger than the upper diameter, that is, the shape does not exceed 100%. Therefore, it is not necessary to consider exceeding 100%.
[0030]
Fourthly, the value obtained by dividing the depth of the via hole by the upper diameter of the hole is reduced. In the present specification, this value is referred to as an aspect ratio. An aspect ratio of 1 or less is preferable because a conductor layer is sufficiently formed on the hole wall and there is no risk of poor connection.
As another embodiment, a solder resist layer is formed in place of the insulating layer 5 in FIG. As a material for the solder resist layer, the same PSR-4000 (trade name; manufactured by Taiyo Ink Manufacturing Co., Ltd.) as the material of the insulating layer was applied and heat-cured so that the resin thickness at the time of finishing was 15 μm. . And the opening part was formed by laser processing.
The laser processing conditions at this time were an energy density of 2.0 J / cm ² , a pulse number of 25 when forming an opening on the opening 7 formed on the via 6, and an opening 8 not on the via. When forming, processing was performed under the condition of 10 pulses.
[0031]
And although the residue was confirmed visually, the residue was not confirmed in any of the opening part 7 and the opening part 8. FIG.
[0032]
【Effect of the invention】
According to the present invention, an opening is processed using an ultraviolet laser under different irradiation conditions between an opening on a pad formed on a via and an opening on a pad not formed on a via. Therefore, it is possible to provide a method for manufacturing a high-density multilayer build-up wiring board capable of performing high-density wiring and capable of manufacturing a highly reliable multilayer printed wiring board.
[Brief description of the drawings]
FIG. 1 is an explanatory view of a manufacturing method of a high-density build-up wiring board according to an embodiment of the present invention. FIG. 2 is an explanatory view of a manufacturing method of a substrate for a semiconductor device according to a conventional technique. Explanatory drawing of manufacturing method of substrate for equipment [Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Insulating substrate 2, 4 Wiring layer 3, 5 Insulating layer 6 Via 7, 7 Opening 9 Laser 51, 71 Insulating substrate 52, 72 Wiring layer 53, 73 Insulating layer 54 Via formation part 55, 74, 79 Via 56, 75 Wiring layer 57, 76 Insulating layer 58 Through hole 59, 77, 80 Via 60 Through hole 61, 78 Wiring layer 62 Power supply layer pattern 63, 81 Solder resist 82, 83 Opening

Claims (3)

A plurality of wiring layers and insulating layers are alternately stacked on both sides of the core substrate in which through holes are formed, and the outer layer and other wiring layers are connected via metal-filled vias, and part of the pads on the outer layer Is formed on the via, forms a solder resist layer having an opening on the outer layer, and in the method of manufacturing a high-density multilayer build-up wiring board in which the pad is exposed from the opening,
The opening is processed using an ultraviolet laser under different irradiation conditions between an opening on a pad formed on a via and an opening on a land not formed on a via. Manufacturing method of high-density multilayer build-up wiring board. A plurality of wiring layers and insulating layers are alternately stacked on both surfaces of the core substrate in which the through holes are formed, and the wiring layers are connected via vias filled with metal, and insulation on the upper wiring layer of the vias In the method of manufacturing a high-density multilayer build-up wiring board that forms openings for vias such that some openings are formed on the vias in the layer,
The opening is processed under different irradiation conditions using an ultraviolet laser in an opening formed on the via and an opening on a land not formed on the via. A manufacturing method of a density multilayer build-up wiring board.   3. The method for producing a high-density multilayer build-up wiring board according to claim 1, wherein the different irradiation conditions are that the ultraviolet laser is irradiated in a pulse shape and the number of pulses is different.

Images