JP4893320B2 - Solid-state imaging device, imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device and an imaging device which are an example of a semiconductor device for physical quantity distribution detection. Specifically, for example, a plurality of unit components that are sensitive to electromagnetic waves input from the outside, such as light and radiation, are arranged, and an analog signal indicating a physical quantity distribution converted into an electric signal by the unit components. The present invention relates to a mechanism for converting an electrical signal into digital data and outputting it externally.

  For example, a plurality of unit components (for example, pixels) that are sensitive to changes in physical quantity such as electromagnetic waves input from the outside such as light and radiation or pressure (contact, etc.) are arranged in a matrix (matrix). Physical quantity distribution detection semiconductor devices are used in various fields.

  For example, in the field of video equipment, a CCD (Charge Coupled Device) type, a MOS (Metal Oxide Semiconductor) or CMOS (Complementary Metal-oxide) that detects a change in light (an example of an electromagnetic wave) which is an example of a physical quantity. A solid-state imaging device using a semiconductor (complementary metal oxide semiconductor) type imaging device (imaging device) is used.

  In recent years, MOS and CMOS type image sensors that can overcome various problems of CCD image sensors have attracted attention as an example of solid-state imaging devices. In the field of computer equipment, fingerprint authentication devices that detect fingerprint images based on changes in electrical characteristics based on pressure and changes in optical characteristics are used. These read out, as an electrical signal, a physical quantity distribution converted into an electrical signal by a unit component (a pixel in a solid-state imaging device).

  For example, a CMOS image sensor has an amplifying circuit such as a floating diffusion amplifier for each pixel. When reading a pixel signal, one row in the pixel array unit is selected as an example of address control. A so-called column-parallel output type or column type is often used in which row signals are accessed simultaneously and in units of rows, that is, pixel signals are read from the pixel array unit simultaneously in parallel for all pixels in one row. ing.

  Further, in the solid-state imaging device, there is a method in which an analog pixel signal read from the pixel array unit is converted into digital data by an analog-digital conversion device (AD conversion device; Analog Digital Converter) and then output to the outside. Sometimes taken.

  The same applies to the column parallel output type solid-state imaging device, and various signal output circuits have been devised. As an example of the most advanced form, an AD conversion device is provided for each column. A method of taking out pixel information as digital data to the outside is considered.

  However, when digital data that has been AD-converted for each column in the column parallel output type is output to the subsequent stage (generally referred to as horizontal data transfer), the parasitic capacitance existing in the horizontal data transfer bus line is a problem. Become. If the capacitance value of the parasitic capacitance is increased, signal delay is caused by that amount, and the speeding up of data transfer is hindered.

  For example, when high-speed operation is performed for reasons such as increasing the frame rate, operations such as row scanning, AD conversion, and horizontal data transfer must be performed at high speed. Of these, when it is desired to speed up horizontal data transfer, the data output stage of the column specified by column address selection drives the bus line, and the time until the data of that column reaches the subsequent circuit is dominant. It becomes.

  A data output stage for pixels in the horizontal direction is connected to the bus line, the parasitic capacitances of the data output stages are combined, and the data output stage of the selected column is driven using the large capacity as a load. It will be. In recent years, since there is a demand for increasing the number of pixels, the number of data output stages connected to the bus line tends to increase, and in recent years, there is a restriction on high speed operation that is particularly required.

  As a technique for solving such a problem, a method of processing in parallel for every certain number of rows as in Patent Document 1 is also conceivable. However, the mechanism described in Patent Document 1 is an application example where analog information is output to the outside as it is, and the mechanism described in Patent Document 1 is particularly applied to a mechanism for digitally converting pixel signals and outputting them externally. Then, problems such as an increase in the number of output terminals and a need for multiplex processing of the output portion arise.

JP 2000-32344 A

  The present invention has been made in view of the above circumstances, and provides a mechanism that can improve problems caused by parasitic capacitance on a bus line in a mechanism for digitally converting a pixel signal and outputting it to the outside of the apparatus. The purpose is to do.

  In one embodiment of the solid-state imaging device according to the present invention, a pixel array unit in which unit pixels are arranged in a matrix, a vertical scanning unit that reads an analog pixel signal from each unit pixel of the pixel array unit, and a pixel array unit AD converter provided for each column that converts analog pixel signals read from each unit pixel into digital data, output driver for data output, and digital data output from the output driver are transferred to the subsequent circuit A column-parallel configuration including a horizontal scanning unit is employed.

  A data holding unit that holds the digital data converted by the AD conversion unit is provided at the subsequent stage of the AD conversion unit of each column. Further, the number of output drivers smaller than the total number of columns of the data holding unit is provided at a subsequent stage of any of the data holding units. It is not a configuration in which output drivers are provided on a one-to-one basis in each column of the data holding unit, but has a great feature in that the number of output drivers is smaller than the total number of columns of the data holding unit.

  Here, various mechanisms can be considered as a mechanism for reducing the number of output drivers below the total number of columns in the data holding unit. For example, all the columns in the data holding unit are changed to a plurality of blocks each including a plurality of columns. Each block can have a configuration in which one output driver is provided in the subsequent stage of one data holding unit, or an output driver in the subsequent stage of any one data holding unit for all columns of the data holding unit. It is also possible to adopt a configuration in which one is provided. When adopting block division, it is preferable to reduce power consumption by stopping circuit operations of invalid blocks that are not related to the data output operation.

  More preferably, a mechanism that enables a data shift operation in which one data holding unit sequentially shifts data in the data holding units in the other columns is possible. For this purpose, a data switching unit is provided between the AD conversion unit and the data holding unit for each column. The data switching unit connects one input to the output side of the AD conversion unit of the own column and connects the other input to the output side of the data holding unit of the other column.

  In order to shift the data, first, the digital data converted by the AD converter of the own column is transferred to the data holding unit of the own column, and then the digital data output from the data holding unit of the other column is transferred to the own column. Transfer to the data holding unit. At this time, the horizontal scanning unit supplies a clock that enables a data shift operation to the data holding unit. The output driver is provided at the subsequent stage of the data holding unit located at the head of such a data shift operation.

  Note that the solid-state imaging device may have a form formed as a single chip, or a module-like form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Also good.

  Further, the present invention can be applied not only to a solid-state imaging device but also to an imaging device. In this case, the same effect as the solid-state imaging device can be obtained as the imaging device. Here, the imaging device indicates, for example, a camera (or camera system) or a portable device having an imaging function. “Imaging” includes not only capturing an image during normal camera shooting, but also includes fingerprint detection in a broad sense.

  According to one embodiment of the present invention, since the number of output drivers is smaller than the total number of columns of the data holding unit, output is compared with a configuration in which output drivers are provided on a one-to-one basis in each column of the data holding unit. Parasitic capacitance on the bus line caused by the driver can be reduced. By reducing the number of output drivers connected to the bus line and reducing the parasitic capacitance, problems caused by the parasitic capacitance can be improved. The output driver selected at the time of horizontal data transfer reduces the need to drive a large capacity, and enables a higher-speed horizontal data transfer operation.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a case where a CMOS solid-state imaging device, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example. The CMOS solid-state imaging device will be described on the assumption that all pixels are made of NMOS.

  However, this is an example, and the target device is not limited to the MOS type solid-state imaging device. All the semiconductor device for physical quantity distribution detection in which a plurality of unit components that are sensitive to electromagnetic waves input from outside such as light and radiation are arranged in a line or matrix form, and all implementations described later. Forms are applicable as well.

<Overview of solid-state imaging device>
FIG. 1 is a schematic configuration diagram of a CMOS solid-state imaging device (CMOS image sensor) which is an embodiment of the solid-state imaging device according to the present invention.

  The solid-state imaging device 1 has a pixel unit in which a plurality of pixels including a light receiving element (an example of a charge generation unit) that outputs a signal corresponding to an incident light amount is arranged in rows and columns (that is, in a two-dimensional matrix). The signal output from each pixel is a voltage signal, and a CDS (Correlated Double Sampling) processing function unit, a digital conversion unit (ADC), etc. are provided in parallel in a column. It is.

  “A CDS processing function unit and a digital conversion unit are provided in parallel in a column” means that a plurality of CDS processing function units substantially parallel to a vertical signal line (an example of a column signal line) 19 in a vertical column This means that a digital conversion unit is provided.

  Each of the plurality of functional units is arranged only on one end side in the column direction with respect to the pixel array unit 10 (output side arranged on the lower side of the drawing) when the device is viewed in plan view. Or one end side in the column direction (output side arranged on the lower side of the figure) and the other end side opposite to the pixel array unit 10 (upper side in the figure). ) May be arranged separately. In the latter case, it is preferable that the horizontal scanning unit that performs readout scanning (horizontal scanning) in the row direction is also arranged separately on each edge side so that each can operate independently.

  For example, as a typical example in which a CDS processing function unit and a digital conversion unit are provided in parallel in a column, a CDS processing function unit and a digital conversion unit are arranged for each vertical column in a portion called a column area provided on the output side of the imaging unit. And is a column type that sequentially reads out to the output side. In addition to the column type (column parallel type), one CDS processing function unit or digital conversion unit is allocated to a plurality of adjacent (for example, two) vertical signal lines 19 (vertical columns), N A mode in which one CDS processing function unit or digital conversion unit is allocated to N vertical signal lines 19 (vertical columns) every other number (N is a positive integer; N−1 are arranged therebetween). It can also be taken.

  Except for the column type, in any form, since a plurality of vertical signal lines 19 (vertical columns) commonly use one CDS processing function unit and digital conversion unit, they are supplied from the pixel array unit 10 side. A switching circuit (switch) that supplies pixel signals for a plurality of columns to one CDS processing function unit or digital conversion unit is provided. Depending on the subsequent processing, a separate measure such as providing a memory for holding the output signal is required.

  In any case, the signal processing of each pixel signal is read out in units of pixel columns by adopting a form in which one CDS processing function unit or digital conversion unit is assigned to a plurality of vertical signal lines 19 (vertical columns). By performing the processing later, the configuration in each unit pixel can be simplified and the number of pixels of the image sensor can be reduced, the size can be reduced, and the cost can be reduced as compared with the case where the same signal processing is performed in each unit pixel.

  In addition, since a plurality of signal processing units arranged in parallel in a column can simultaneously process pixel signals for one row, one CDS processing function unit or digital conversion unit is provided on the output circuit side or outside the device. Therefore, the signal processing unit can be operated at a low speed as compared with the case where processing is performed, which is advantageous in terms of power consumption, bandwidth performance, noise, and the like. In other words, when the power consumption and bandwidth performance are the same, the entire sensor can be operated at high speed.

  In the case of a column type configuration, it can be operated at a low speed, which is advantageous in terms of power consumption, bandwidth performance, noise, and the like, and has an advantage that a switching circuit (switch) is unnecessary. In the following embodiments, this column type will be described unless otherwise specified.

  As shown in FIG. 1, the solid-state imaging device 1 of the present embodiment includes a pixel array unit 10 that is also referred to as a pixel unit or an imaging unit in which a plurality of unit pixels 3 are arranged in rows and columns, and a pixel array unit 10. Drive control unit 7 provided outside, a read current source unit 24 for supplying an operation current (read current) for reading a pixel signal to the unit pixels 3 of the pixel array unit 10, and a column arranged for each vertical column A column processing unit 26 having an AD circuit 25 and an output circuit 28 are provided. Each of these functional units is provided on the same semiconductor substrate.

  In FIG. 1, some of the rows and columns are omitted for the sake of simplicity, but in reality, tens to thousands of unit pixels 3 are arranged in each row and each column. The unit pixel 3 typically includes a photodiode as a light receiving element (charge generation unit) that is an example of a detection unit, and an intra-pixel amplifier (for example, a transistor) of an amplification semiconductor element (for example, a transistor). Example).

  Note that the solid-state imaging device 1 can make the pixel array unit 10 compatible with color imaging by using a color separation (color separation) filter. That is, color separation comprising a combination of a plurality of color filters for capturing a color image on a light receiving surface on which electromagnetic waves (light in this example) of each charge generation unit (photodiode, etc.) in the pixel array unit 10 are incident. Any color filter of the filter is provided in, for example, a so-called Bayer array, so that color image capturing is supported.

  The column AD circuit 25 of the present embodiment performs a difference process between a signal level immediately after pixel reset (hereinafter referred to as a reset level), which is a reference level of the pixel signal So, and a signal level, whereby the reset level and the signal A difference processing unit (CDS) 25a that acquires a signal component indicated by a level difference, and an AD conversion unit that converts a signal component that is a difference between a reset level that is a reference level of a pixel signal and a signal level into N-bit digital data (ADC) 25b is provided.

  The difference processing unit 25a and the AD conversion unit 25b can be arranged in any order. For example, as shown in FIG. 1, the difference processing unit 25a performs difference processing between an analog reset level and a signal level. The difference processing result may be converted into digital data by the AD conversion unit 25b. Although not shown, the AD conversion unit 25b converts the reset level and the signal level into digital data, and the difference between the digital data. The difference processing unit 25a may take the above.

  The function of the difference processing unit 25a is equivalent to a process (equivalent to a so-called CDS process) that takes a difference between a reset level and a true signal level (according to a received light amount), and is equivalent to a fixed pattern noise (FPN). A noise signal component called reset noise can be removed.

  As described above, the column AD circuit 25 of the present embodiment has both an AD conversion function that converts an analog pixel signal transferred from the pixel array unit 10 into digital data and a function that suppresses and removes noise components. It functions as an AD conversion / noise removal signal processing apparatus. In the column AD circuit (AD conversion / noise removal signal processing device) 25, the pixel signals output from the unit pixels 3 in the row selected by the vertical scanning unit 14 for selecting the row address are simultaneously converted into N-bit digital data for each row. Conversion to noise and noise removal signal processing are performed.

  As the AD conversion processing in the column processing unit 26, analog signals held in parallel in units of rows are used for each row by using a column AD circuit 25 (specifically, the AD conversion unit 25b) provided for each column. A method of AD conversion in parallel is adopted. In this case, an AD conversion method called a single slope integration type or a ramp signal comparison type may be adopted. Since this method can realize an AD converter with a simple configuration, it has a feature that the circuit scale does not increase even if it is provided in parallel.

  In the single slope integration type AD conversion in the column AD circuit 25 (AD conversion unit 25b), an analog signal is generated based on the time from the start of conversion until the reference signal Vslop matches the processing target signal voltage (pixel signal voltage Vx). Is converted into a digital signal. As a mechanism for this, in principle, a ramp-like reference signal Vslop is supplied to a comparator (voltage comparator), and counting (counting) with a clock signal is started and input via a vertical signal line 19. AD conversion is performed by counting the number of clocks until a pulse signal indicating the comparison result is obtained by comparing the analog pixel signal thus obtained with the reference signal Vslop.

  At this time, by devising the circuit configuration and operation of the AD conversion unit 25b, with respect to the voltage mode pixel signal input through the vertical signal line 19 together with the AD conversion, CDS processing that takes a difference from the true signal level (according to the amount of received light) can be performed, and it can also function as a difference processing unit 25a that removes noise signal components such as fixed pattern noise.

  However, adopting a single slope integration type configuration as the column AD circuit 25 is only an example, and any other circuit configuration may be employed as long as it can perform AD conversion processing and noise removal signal processing. be able to.

  The drive control unit 7 has a control circuit function for sequentially reading signals from the pixel array unit 10. For example, as the drive control unit 7, a horizontal scanning unit (column scanning circuit) 12 that controls column addresses and column scanning, a vertical scanning unit (row scanning circuit) 14 that controls row addresses and row scanning, and an internal clock are generated. And a communication / timing control unit 20 having functions such as

  The unit pixel 3 includes a vertical scanning unit 14 via a row control line 15 for row selection, a column processing unit 26 in which a column AD circuit 25 is provided for each vertical column via a vertical signal line 19, Each is connected. Here, the row control line 15 indicates the entire wiring that enters the pixel from the vertical scanning unit 14.

  The vertical scanning unit 14 selects a row of the pixel array unit 10 and supplies a necessary pulse to the row. For example, the vertical scanning unit 14 defines a readout row in the vertical direction (selects a row of the pixel array unit 10). It has a vertical decoder 14a and a vertical driver 14b that supplies a pulse to the row control line 15 for the unit pixel 3 on the read address (in the row direction) defined by the vertical decoder 14a and drives it. Note that the vertical decoder 14a selects not only a row from which a signal is read (reading row: also referred to as a selection row or a signal output row) but also a row for an electronic shutter.

  The horizontal scanning unit 12 has a function of a reading scanning unit that sequentially selects the column AD circuit 25 of the column processing unit 26 in synchronization with the clock and reads data obtained by digitally converting the pixel signal to the horizontal signal line 18. For example, the horizontal scanning unit 12 defines a horizontal readout row (selects each column AD circuit 25 in the column processing unit 26), and a read address defined by the horizontal decoder 12a. A horizontal driving unit 12b for guiding each signal of the column processing unit 26 to the horizontal signal line 18;

  For example, if the horizontal signal line 18 corresponds to the number of bits n (n is a positive integer) handled by the column AD circuit 25, for example, 10 (= n) bits, 10 bus lines are arranged corresponding to the number of bits. It is.

  Although not shown, the communication / timing control unit 20 is externally connected via a functional block of a timing generator TG (an example of a read address control device) that supplies a clock signal required for the operation of each unit and a pulse signal of a predetermined timing, and a terminal 5a. Receives the master clock CLK0 supplied from the main control unit, receives data instructing the operation mode supplied from the external main control unit via the terminal 5b, and further includes data including information of the solid-state imaging device 1. And a functional block of a communication interface that outputs to an external main control unit.

  For example, the horizontal address signal is output to the horizontal decoder 12a and the vertical address signal is output to the vertical decoder 14a, and each decoder 12a, 14a receives it and selects a corresponding row or column. The horizontal scanning unit 12 and the vertical scanning unit 14 include address setting decoders 12a and 14a, and perform a shift operation (scanning) in response to control signals CN1 and CN2 provided from the communication / timing control unit 20. Switch the read address.

  At this time, since the unit pixels 3 are arranged in a two-dimensional matrix, analog pixel signals generated by the pixel signal generation unit provided in the unit pixels 3 and output in the column direction via the vertical signal lines 19 are processed. Access and fetch (vertical) scan reading in units (in parallel), and then access the row direction, which is the arrangement direction of the vertical columns, and output pixel signals (digital pixel data in this example) to the output side Reading (horizontal) scan reading is preferably performed to speed up reading of pixel signals and pixel data. Of course, not only scanning reading but also random access for reading out only the information of the necessary unit pixel 3 is possible by directly addressing the unit pixel 3 to be read out.

  The elements of the drive control unit 7 such as the horizontal scanning unit 12 and the vertical scanning unit 14 are formed integrally with the pixel array unit 10 in a semiconductor region such as single crystal silicon using a technique similar to the semiconductor integrated circuit manufacturing technique. As a so-called one-chip (provided on the same semiconductor substrate), a CMOS image sensor which is an example of a semiconductor system is configured to form part of the solid-state imaging device 1 of the present embodiment. .

  Note that the solid-state imaging device 1 may be configured as one chip in which each unit is integrally formed in the semiconductor region as described above. Although not illustrated, the pixel array unit 10 and the drive control unit are omitted. 7. In addition to various signal processing units such as the column processing unit 26, an imaging function in which these are collectively packaged in a state including an optical system such as a photographing lens, an optical low-pass filter, or an infrared light cut filter It is good also as a modular form which has.

  In the solid-state imaging device 1 having such a configuration, the pixel signal output from the unit pixel 3 is supplied to the column AD circuit 25 of the column processing unit 26 via the vertical signal line 19 for each vertical column.

  In the case of a basic configuration in which the data storage unit (memory) 256 is not provided, the output of the AD conversion unit 25 b or the difference processing unit 25 a is connected to the horizontal signal line 18. When analog difference processing is performed by the difference processing unit 25a and then converted into digital data by the AD conversion unit 25b, the output of the AD conversion unit 25b is connected to the horizontal signal line 18, and conversely, by the AD conversion unit 25b. When differential processing is performed by the differential processing unit 25 a after conversion to digital data, the output of the differential processing unit 25 a is connected to the horizontal signal line 18. Hereinafter, the former case will be described as shown in FIG.

  A control pulse (horizontal data transfer clock φH) is input from the horizontal scanning unit 12 to the AD conversion unit 25b via the control line 12c. The AD conversion unit 25b has a latch function for holding the count result, and holds data until an instruction by a control pulse is given via the control line 12c.

  In the present embodiment, as shown in the drawing, the output side of each column AD circuit 25 has data as an N-bit memory device that holds the count result held by the AD conversion unit 25b at the subsequent stage of the AD conversion unit 25b. A storage unit 256 and a load / shift selection selector (SEL) 258 which is an example of a data switching unit disposed between the AD conversion unit 25b and the data storage unit 256 are provided.

  When the configuration including the data storage unit 256 is adopted, the load / shift selection selector 258 receives a control pulse from the communication / timing control unit 20 at a predetermined timing in common with the load / shift selection selector 258 of the other vertical columns. The memory transfer instruction pulse CN8 is supplied.

  When the memory transfer instruction pulse CN8 is supplied based on the load function, the load / shift selection selector 258 transfers the data of the corresponding AD conversion unit 25b in its own column to the data storage unit 256. The data storage unit 256 holds and stores the transferred data.

  Here, the load / shift selection selector 258 of this embodiment will not only have a function of transferring data of the AD conversion unit 25b of the own column to the data storage unit 256 side but also stores data of other columns, as will be described in detail later. It also has a function of transferring the data held by the unit 256 to the data storage unit 256 side of the own column. This is the reason why it is also called a shift selection selector.

  In the horizontal scanning unit 12 according to the present embodiment, each difference processing unit 25a and AD conversion unit 25b of the column processing unit 26 perform the processing that they are responsible for in response to the provision of the load / shift selection selector 258. In parallel with this, it has a function of a reading scanning section for reading out data held in each data storage section 256.

  The output of the data storage unit 256 is connected to the horizontal signal line 18. The horizontal signal line 18 has a signal line of N bit width which is the bit width of the column AD circuit 25, and is connected to an output circuit 28 having n sense circuits corresponding to the respective output lines (not shown). .

  In particular, if the configuration includes the data storage unit 256, AD conversion data held by the AD conversion unit 25b can be transferred to the data storage unit 256, so that the AD conversion processing of the AD conversion unit 25b and the AD conversion are performed. The read operation to the horizontal signal line 18 as a result can be controlled independently, and a pipeline operation in which AD conversion processing and signal read operation to the outside are performed in parallel can be realized.

  For example, when a single slope integration type AD conversion method is adopted as the column AD circuit 25, the column AD circuit 25 reads out a pixel signal from the pixel array unit 10 at a predetermined timing in one horizontal period, and then single slope integration. A system AD conversion process is performed, and an AD conversion result is output at a predetermined timing. That is, first, the voltage comparison unit compares the reference signal for comparison processing (for practical AD conversion processing) with the pixel signal voltage input via the vertical signal line 19, and the two voltages are the same. Then, the comparator output of the voltage comparison unit is inverted. For example, the voltage comparison unit sets the H level such as the power supply potential to the inactive state, and transitions to the L level (active state) when the pixel signal voltage matches the reference signal.

  The counter unit provided in the subsequent stage of the voltage comparison unit starts the count operation in the down-count mode or the up-count mode in synchronization with the change of the reference signal, and performs the count operation when the inverted information of the comparator output is notified. The AD conversion is completed by latching (holding / storing) the count value at that time as pixel data. Thereafter, the data is transferred to the data storage unit 256 at a predetermined timing, and stored / held.

  Thereafter, the column AD circuit 25 stores pixel data stored and held in the data storage unit 256 based on a shift operation synchronized with a control pulse input from the horizontal scanning unit 12 via the control line 12c at a predetermined timing. The output is sequentially output from the output terminal 5c to the outside of the column processing unit 26 or the outside of the chip having the pixel array unit 10.

<Problems of horizontal data transfer>
Here, when the data held in the data storage unit 256 of each column is sequentially transferred to the output circuit 28 side via the horizontal signal line 18 which is a bus line, the data is transferred to the horizontal signal line 18 connected to the output circuit 28. Due to the presence of parasitic capacitance, due to the presence of parasitic capacitance, such as deterioration in transfer speed, and the wiring width (Metal width) used for the horizontal signal line 18 must be increased in order to suppress parasitic capacitance, the chip size increases. Various problems arise.

For example, the value of parasitic capacitance is
(1) Capacity due to the horizontal signal line 18,
(2) capacitance due to the input stage of the output circuit 28;
(3) Capacity by output stage of one data storage unit 256 × total number of data storage units 256,
(4) capacity of wiring connecting the horizontal signal line 18 and the output stage of one data storage unit 256 × total number of data storage units 256,
It is the total value.

  Therefore, when data held in the data storage unit 256 of each column is sequentially selected and read out to the horizontal signal line 18 by the data storage unit 256, there is an obstacle in data transfer due to the parasitic capacitance of the horizontal signal line 18 described above. Arise. In particular, if the capacitance value of the parasitic capacitance is increased, it causes signal delay and hinders speeding up of data transfer.

  For example, when high-speed operation is performed for reasons such as increasing the frame rate, operations such as row scanning, AD conversion, and horizontal data transfer must be performed at high speed. Of these, when it is desired to speed up the horizontal data transfer, the time until the data storage unit 256 selected by the horizontal scanning unit 12 drives the horizontal signal line 18 and the signal reaches the output circuit 28 is dominant. It becomes.

  In the case of the pixel array unit 10 having horizontal pixels, for example, 2000 columns of unit pixels 3, 2000 data storage units 256 are connected to the horizontal signal line 18, and each output stage of the data storage unit 256 is connected to the horizontal signal line 18. Thus, the selected data storage unit 256 is driven with the large capacitance as a load. In recent years, since there is a demand for increasing the number of pixels, the number of data storage units 256 connected to the horizontal signal line 18 tends to increase.

  As a method for solving such a problem, a method of widening the wiring width used for the horizontal signal line 18 in order to suppress the parasitic capacitance is conceivable, but bit-specific data is transferred by the horizontal signal line 18 as a bus line. In some cases, the chip size becomes large.

  As another method for solving such a problem, a method of processing in parallel for each number of columns as in Patent Document 1 (Japanese Patent Laid-Open No. 2000-32344) is also conceivable. However, the mechanism described in Patent Document 1 is an application example in the case where analog information is output to the outside of the solid-state imaging device 1 as it is, and in particular, pixel signals are digitally converted and output to the outside of the solid-state imaging device 1. If the mechanism of Patent Document 1 is applied to the mechanism, problems such as an increase in the number of output terminals and a need for multiplex processing of the output portion arise.

  Therefore, in the present embodiment, in the mechanism in which the pixel signal is digitally converted and output to the outside of the solid-state imaging device 1, the column processing unit 26 and the horizontal scanning unit 12 are caused to have a problem caused by the parasitic capacitance of the horizontal signal line 18. Make it a mechanism that can be improved. This will be specifically described below.

<Details around data storage and load / shift selection selector; first example>
FIG. 2 is a diagram showing a first example of a detailed configuration of the column processing unit 26 (particularly around the data storage unit 256 and the load / shift selection selector 258) shown in FIG. FIG. 3 is a diagram showing a comparative example with respect to the configuration of the column processing unit 26 of the first example shown in FIG.

  In the solid-state imaging device 1 of the present embodiment, as a mechanism for reducing the parasitic capacitance of the horizontal signal line 18, the data in each data storage unit 256 is directly output to the horizontal signal line 18 via the output driver for each column. Instead, a configuration is employed in which the output is made to the horizontal signal line 18 via a smaller number of output drivers than the total number of columns in the data storage unit 256. Various mechanisms are conceivable as a mechanism for this, but in the first example, a data shift operation in which one data storage unit 256 sequentially shifts data in the data storage unit 256 in another column is possible. It is characterized in that

  In the first example of the detailed configuration of the column processing unit 26 according to the present embodiment (hereinafter referred to as the column processing unit 26 of the first example), first, the data storage unit 256 has the rising edge of the subclock SUBCK input to the clock terminal CK. A D-type flip-flop (denoted as DFF in the figure) 310, which is an example of a data holding unit that captures and holds data input to the D input terminal in synchronization therewith, is provided. A load / shift selection selector 258 having a two-input / one-output data selector structure is disposed in front of the D input terminal of the D flip-flop 310.

  Further, the column processing unit 26 of the first example divides all the columns of the data storage unit 256 into a plurality of blocks each including a plurality of columns, and one output driver 320 is provided in the subsequent stage of one data storage unit 256 per block. Provide. Specifically, the data storage unit 256 and the load / shift selection selector 258 in each column are paired into a plurality of blocks (groups) each having a plurality of pairs (the data storage unit 256 and the load / shift selection selector 258). Divide. One of the data storage units 256 for each block has an output driver 320 that is an example of a bus drive circuit (data output stage) on the non-inverted output (Q terminal output) side of the D-type flip-flop 310. The output of the output driver 320 is connected to the output circuit 28 via the horizontal signal line 18 that is a bus line.

  That is, the column processing unit 26 of the first example divides a column into blocks, and when the data is output to the horizontal signal line 18, the data passed to the D-type flip-flop 310 by the load / shift selection selector 258 is converted to the data of the other columns. By switching, the data storage unit 256 belonging to the block is operated as one shift register for each block. Hereinafter, each block having a plurality of pairs of the data storage unit 256 and the load / shift selection selector 258 is referred to as a horizontal data transfer sub-block 300.

  In the block, m pairs of data storage units 256 and load / shift selection selectors 258 are provided, and n horizontal data transfer sub-blocks 300 are provided. For example, the horizontal data transfer sub-block 100 holds data after AD conversion by the AD conversion unit 25b of 100 columns, for example, from the entire column, and transfers horizontal data to the output circuit 28 side via the horizontal signal line 18. A plurality of sub-blocks are arranged side by side in the entire column.

  Hereinafter, in order to distinguish each of the data storage unit 256 (specifically, the D-type flip-flop 310), the load / shift selection selector 258, and the output driver 320, first, “_1” to “_n” are blocked after each reference. The data storage unit 256 (D-type flip-flop 310) and the load / shift selection selector 258 are further assigned the identification numbers in the block with "_1" to "_m". To do. As a whole, there will be n * m columns.

  The data C of the AD conversion unit 25b of the own column is input to one input terminal of the load / shift selection selector 258, and the output (for example, non-inverted output Q) of the data storage unit 256 of the adjacent column is input to the other input terminal. input.

  Note that the data storage unit 256 on the lower side of the shift operation is limited to the other input terminal of the load / shift selection selectors 258_1_m to 258_n_m at the end (final stage: right end in the figure) in each horizontal data transfer sub-block 300. Since it does not exist, the output of the data storage unit 256 in the other column cannot be taken in. Instead, a certain logic level is input. During the shift operation, data that is ultimately useless for data output is prevented from changing between L / H, thereby reducing power consumption.

  As a certain logic level, for example, the other input terminal may be connected to a power supply for the logic level, and may be set to the H level, or conversely, the other input terminal may be connected to the ground to be the L level. In this example, the latter case of setting to the L level is shown.

  The load / shift selection selector 258 is supplied with a load / shift selection signal LD from the communication / timing controller 20 as an example of the memory transfer instruction pulse CN8. For example, the load / shift selection selector 258 loads the data digitally converted by the AD conversion unit 25b into the data storage unit 256 or performs a shift operation to be described later together with the data storage unit 256 as a load / shift selection signal LD. Switch with.

  As an example, when the load / shift selection signal LD is set to active H, a normal operation of transferring data from the AD conversion unit 25b of the own column to the data storage unit 256 of the own column is performed. On the other hand, when inactive L is set, a shift operation is performed by transferring data from the data storage unit 256 in the other column to the data storage unit 256 in the own column. When the load / shift selection signal LD is inactive L, the shift register configuration is adopted as a whole.

  Corresponding block selection signals BSEL_1 to BSEL_n are input from the communication / timing control unit 20 to the output enable terminals OE of the output drivers 320_1 to 320_n of each horizontal data transfer sub-block 300. Each of the output drivers 320_1 to 320_n is input when the corresponding block selection signal BSEL_1 to BSEL_n is active (in this example, H (high) level) (that is, when the output enable terminal OE is at H level). The information is transferred to the output circuit 28 through the horizontal signal line 18.

  The output driver 320 of this embodiment converts data of a general logic level (logic level) from the D-type flip-flop 310 into an analog signal having a narrower voltage amplitude and outputs the analog signal to the horizontal signal line 18. This is because, in terms of high-speed data transfer, it is more advantageous in terms of driving capability and power consumption than when information is transferred to the output circuit 28 via the horizontal signal line 18 while maintaining the logic level.

  When the output circuit 28 receives the information converted from the logic level (logic level) to the analog signal having a narrow voltage amplitude by the output driver 320 via the horizontal signal line 18, the output circuit 28 again receives the information of the logic level (logic level). Convert to and output.

  The output driver 320 provided for each block (that is, for each horizontal data transfer sub-block 300) is provided in the column of the final stage of the shift operation of the D-type flip-flop 310 during the shift operation in the horizontal data transfer sub-block 300, and its output terminal Are connected to the horizontal signal line 18 which is a bus line. As an example, in the figure, an output driver 320 is provided on the output side of the D-type flip-flop 310 that is remote from the output circuit 28.

  Further, the horizontal scanning unit 12 (referred to as the horizontal scanning unit 12 in the first example) corresponding to the column processing unit 26 in the first example is common to the clock terminal CK of the D-type flip-flop 310 of each horizontal data transfer sub-block 300. The clock generation unit 340 generates the clock signal CK_HLD to be input to each group.

  The clock generation unit 340 captures and holds the corresponding block selection signals BSEL_1 to BSEL_n input to the D input terminal in synchronization with the falling edge of the reference clock CK_TR0 input from the communication / timing control unit 20 to the clock terminal CK. D-type flip-flop (denoted as DFF in the figure) 342 and the horizontal data transfer to which the sub-clock SUBCK belongs by taking the logical product of the non-inverted output (Q terminal output) of the D-type flip-flop 342 and the reference clock CK_TRN And an AND gate 344 that supplies the clock terminal CK of each data storage unit 256 of the sub-block 300.

  The reference clock CK_TR0 is a clock signal that drives the D-type flip-flop 310 of the data storage unit 256, and the block selection signals BSEL_1 to BSEL_n are the D-type flip-flop 310 and the output driver of the horizontal data transfer sub-block 300 of each block. This is a selection signal for activating 320.

  The AND gate 344 functions as a clock gate circuit, and outputs the sub clock SUBCK by aligning the edge of the clock CK_TR0 to the sub clock line 350 of the selected horizontal data transfer sub block 300 during the period when the block selection signal BSEL is selected. To do.

  In the horizontal data transfer sub-block 300 to which the sub-clock SUBCK is not supplied, the data shift operation is not performed, so that the circuit operation is effectively stopped and the shift operation (circuit operation) is in a standby state. By stopping the operation of a block that does not require data transfer to the output circuit 28 via the horizontal signal line 18, it is possible not only to wait for the shift operation but also to reduce power consumption.

  As a mechanism for waiting for the shift operation (circuit operation), various mechanisms may be used in addition to stopping the clock input, such as switching the power supply for each block, and other methods while keeping the clock input. However, if there is a clock input, some operation is performed at least in the input stage connected to the clock terminal CK. Therefore, it is considered that the power consumption will increase slightly though the mechanism of this embodiment that stops the clock input. In addition, the method for switching the power supply for each block complicates the configuration.

  Normally, as in the comparative example shown in FIG. 3, an output driver 320 is provided after the D-type flip-flop 310 for each column. That is, the D-type flip-flop 310 receives the output (non-inverted output) of the AD conversion unit 25b in the column corresponding to the D input terminal, and transmits the load / shift selection signal LD to the clock terminal CK. Enter from. Further, an output driver 320 is provided for each output (for example, non-inverted output Q) of the D-type flip-flop 310. The horizontal data transfer clocks φH_1 to φH_n * m from the horizontal scanning unit 12 are supplied to the output enable terminal OE of the output driver 320.

  On the other hand, in this embodiment, the output driver 320 that is effectively shared by a plurality of data storage units 256 (specifically, the D-type flip-flop 310) is attached to one block (for each horizontal data transfer sub-block 300). ) One D-type flip-flop 310 is provided in the subsequent stage.

  As inferred from the comparison between FIG. 2 and FIG. 3, in the configuration of the column processing unit 26 of the first example, a horizontal line that is a bus line connected to the output side of the output driver 320 to which a large load capacity is connected. The circuit format in which the signal line 18 is used is changed to a mechanism in which data is transferred by a shift register method by sequentially switching for each group (horizontal data transfer sub-block 300). By connecting each horizontal data transfer sub-block 300 to the horizontal signal line 18 (bus line), the load capacity connected to the horizontal signal line 18 is reduced, and as a result, high speed operation is realized. This will be specifically described below.

<Operation of Column Processing Unit; First Example>
FIG. 4 is a timing chart for explaining the operation of each horizontal data transfer sub-block 300 and clock generation unit 340 of the column processing unit 26 of the first example shown in FIG. In FIG. 4, along the time axis t, the reference clock CK_TR0, the subclock SUBCK, the load / shift selection signal LD, the block selection signal BSEL, the data held and output by the D-type flip-flop 310, and the horizontal signal line 18 Represents the transfer data.

  The reference clock CK_TR0 input to the D-type flip-flop 342 of the clock generation unit 340 is a synchronous clock that continues to be output during the period during which the horizontal data transfer operation is performed, and the communication / timing control unit 20 starts with all the horizontal data In order to select the transfer sub-block 300, all the block selection signals BSEL_1 to BSEL_n are asserted (active H here) during the L level period of the reference clock CK_TR0 (t30).

  Thereafter, in synchronization with the falling edge of the next reference clock CK_TR0, the load shift selection signal LD is asserted for one period of the reference clock CK_TR0 (in this case, active H) (t32).

  As a result, the load / shift selection selectors 258_1_1 to 258_n_m of each column select the data digitally converted by the AD conversion units 25b_1_1 to 254_n_m and supply them to the D input terminals of the D-type flip-flops 310_1_1 to 310_n_m. For example, in the horizontal data transfer sub-block 300_1 of the first block, the load / shift selection selectors 258_1_1 to 258_1_m select the data digitally converted by the AD conversion unit 25b and apply it to the D input terminals of the D-type flip-flops 310_1_1 to 310_1_m. Supply. The same applies to the horizontal data transfer sub-blocks 300_2 to 300_n after the second block.

  At the same time, the clock generators 340_1 to 340_n corresponding to the horizontal data transfer sub-blocks 300_1 to 300_n first receive the block selection signals BSEL_1 to BSEL_n in synchronization with the falling edge of the reference clock CK_TR0 by the D-type flip-flop 342. The logical product of the non-inverted output and the reference clock CK_TR0 is obtained by AND gates 344_1 to 344_n, and the sub clocks SUBCK_1 to SUBCK_n are output to the corresponding sub clock lines 350_1 to 350_n for one clock (t34). Thus, each D-type flip-flop (DFF) 310 loads and shifts the data digitally converted by the AD conversion unit 25b over the entire column in synchronization with the rising edges of the corresponding subclocks SUBCK_1 to SUBCK_n. Capture and hold via the selector 258.

  In this process, the communication / timing controller 20 deselects other than the horizontal data transfer sub-block 300_1 that outputs data first at the next clock timing (t33 before timing t34) of the reference clock CK_TR0. Then, the block selection signal BSEL_2 and thereafter (up to ~ BSEL_n) are negated (set to inactive L).

  Therefore, only the output of the output driver 320_1 of the selected first horizontal data transfer sub-block 300_1 is output to the horizontal signal line 18 at time t34. This output driver 320_1 is the output of the D-type flip-flop 310_1_1 located at the leftmost position in the figure of the horizontal data transfer sub-block 300_1. At the previous timing (t34), the information corresponding to the loaded data C_1_1 Is output to the horizontal signal line 18.

  Further, at the next clock timing (t36) of the reference clock CK_TR0, the load shift selection signal LD is negated (set to inactive L), and the load shift selection selector 258 receives the D-type flip-flop 310 in the other column. Data is taken in and transferred to the D-type flip-flop 310 in its own column, thereby performing a shift operation.

  Note that for a while after this timing (t36) (until the block selection signal BSEL1 becomes inactive L), the data shift operation is valid only in the horizontal data transfer sub-block 300 of the first block.

  In the horizontal data transfer sub-block 300 of the first block, the data C_1_2 of the adjacent D-type flip-flop 310_1_2 is moved to the leftmost D-type flip-flop 310_1_1, and the D-type flip-flop 310_1_1 is transferred to the output driver 320_1. The data C_1_2 is output (t36). That is, data shifted by one column at the next clock timing is transferred to the output circuit 28 via the horizontal signal line 18 and output. At this time, the L level is input to the D-type flip-flop 310_1_m at the final stage (the rightmost side in the figure) of the horizontal data transfer sub-block 300_1 via the load / shift selection selector 258_1_m.

  Similarly, this clock-synchronized shift operation is repeated for the number of data storage units 256 (specifically, D-type flip-flop 310) belonging to one horizontal data transfer sub-block 300 (in this example, for m columns). As a result, the data of the columns for the blocks are sequentially output.

  When the data shift operation for m columns in the horizontal data transfer sub-block 300_1 of the first block is completed (t40), the process shifts to the data shift operation for m columns in the horizontal data transfer sub-block 300_2 of the next second block. Therefore, the communication / timing control unit 20 negates the block selection signal BSEL_1 for the first block (sets it to inactive L) and simultaneously asserts the block selection signal BSEL_2 for the second block (sets it to active H). .

  As a result, the horizontal data transfer sub-block 300_2 of the second block is activated, so that the output driver 320_2 first outputs the data C_2_1 held in the D-type flip-flop 310_2_1 to the horizontal signal line 18. Thereafter, the horizontal data transfer operation is performed in the same manner as the data shift operation in the horizontal data transfer sub-block 300_1 of the first block. Eventually, the horizontal data transfer sub-blocks 300 of all the blocks are sequentially activated, so that the horizontal data transfer of all the columns is completed.

  Thus, according to the configuration of the column processing unit 26 (particularly the horizontal data transfer sub-block 300) of the first example shown in FIG. 2 and the operation shown in FIG. 4, the output driver connected to the horizontal signal line 18 The number of 320 can be reduced. In the example shown in FIG. 2, only n output drivers 320 are connected to the horizontal signal line 18 for a total of n (blocks) × m (number of columns per block). Thus, it can be reduced to 1 / m compared to the case where the output driver 320 is provided for each column as in the comparative example shown in FIG.

  In the comparative example shown in FIG. 3, the output driver 320 added to all the columns is connected to the horizontal signal line 18 that is a bus line, whereas in this embodiment, for each horizontal data transfer sub-block 300. Only the output driver 320 provided is connected to the horizontal signal line 18, and as a result, the number of output drivers 320 connected to the bus line (horizontal signal line 18) is reduced.

  For example, when 2000 unit pixels 3 are grouped into the horizontal data transfer sub-block 300 every 100 columns, the number of output drivers 320 connected to the horizontal signal line 18 is 20. This reduces the parasitic capacitance of the output portion of each output driver 320 attached to the horizontal signal line 18, reduces the need for the selected output driver 320 to drive a large capacitance, and enables a faster horizontal data transfer operation. It becomes.

  In addition, in the column processing unit 26 of the first example, the column is divided into a plurality of blocks, and the sub clock SUBCK is applied only to the horizontal data transfer sub block 300 that needs to perform the shift operation (in other words, needs to be activated). Since the shift operation is performed for each block, the power consumption can be reduced compared to the second example described later.

  As the number of blocks is increased, the number of D-type flip-flops 310 in the block, that is, the number of D-type flip-flops 310 that perform a shift operation is reduced, so that the effect of reducing power consumption is enhanced. However, the number of output drivers 320 corresponding to the number of blocks is required, and the load capacity of the horizontal signal line 18 increases accordingly.

  In the column processing unit 26 of the first example, a fixed logic level (L level in the previous example) is input to the terminal D-type flip-flops 310_1_m to 310_n_m for each group to perform a shift operation. Unnecessary signal transitions are eliminated. This brings about an effect of further reducing power consumption.

  Similarly to the comparative example, the horizontal signal line 18 that is a bus line may be one system. As in Patent Document 1, the number of output terminals may be increased, or the horizontal signal line 18 or later (output) The problem that multiplex processing is necessary does not occur.

<Details around data storage and load / shift selection selector; second example>
FIG. 5 is a diagram showing a second example of a detailed configuration of the column processing unit 26 (particularly, around the data storage unit 256 and the load / shift selection selector 258) shown in FIG.

  The second example of the detailed configuration of the column processing unit 26 (hereinafter referred to as the column processing unit 26 of the second example) is the same as the first example in which the data storage unit 256 is shifted when data is output to the horizontal signal line 18. This is a modified example. When the data is output to the horizontal signal line 18 without being divided into blocks, the data to be transferred to the D-type flip-flop 310 is switched to data in another column by the load / shift selection selector 258, so that the entire data storage unit 256 is It is characterized in that it is operated as one shift register. That is, the present invention is characterized in that one output driver 320 is provided in the subsequent stage of any one D-type flip-flop 310 for all columns of the D-type flip-flop 310.

  Specifically, first, as in the first example, the data of the AD conversion unit 25b of the own column is input to one input terminal of the load / shift selection selector 258, and the data of the adjacent column is input to the other input terminal. The non-inverted output of the storage unit 256 is input.

  Since each block is not classified, first, an output driver 320 is provided in any one of the data storage units 256 on the non-inverted output (Q terminal output) side of the D-type flip-flop 310. The output of the output driver 320 is connected to the output circuit 28 via the horizontal signal line 18 that is a bus line.

  In addition, since it is not classified by block, a fixed logic level (L level in this example) is set only for the other input terminal of the load shift selection selector 258_n * m at the end (the last stage: the right end in the figure). The power consumption is reduced by preventing the useless data from being finally shifted to the data output during the shift operation. Although it differs from the first example in that only the load / shift selection selector 258_n * m is targeted, the basic concept is the same as the first example.

  Further, since it is not classified for each block, it is not necessary to prepare the clock generation unit 340 for each block (in fact, only one block may be supported), and only one clock generation unit 340 of the first example is provided. Instead of the block selection signals BSEL_1 to BSEL_n, a data storage control signal MEMO that enables the operation of the data storage unit 256 is input from the communication / timing control unit 20 to the D input terminal of the D-type flip-flop 342.

  As inferred from the comparison between FIG. 2 and FIG. 5, in the configuration of the second example, the circuit format in which the horizontal signal line 18 that is a bus line connected to the output side of the output driver 320 is used is a column. The system is changed to a system in which data is transferred as a whole by a shift register method, and the horizontal signal line 18 (bus line) is connected to only one data storage unit 256 (specifically, the output driver 320) for the previous column. As a result, the load capacity connected to the horizontal signal line 18 is greatly reduced, and as a result, high speed operation is realized. This will be specifically described below.

<Operation of Column Processing Unit; Second Example>
The reference clock CK_TR0 input to the D-type flip-flop 342 of the clock generation unit 340 is a synchronous clock that is continuously output during the horizontal data transfer operation, and the communication / timing control unit 20 starts with the data storage unit 256. The data storage control signal MEMO is asserted (in this case, active H) during the L level period of the reference clock CK_TR0.

  Thereafter, in synchronization with the falling edge of the next reference clock CK_TR0, the load shift selection signal LD is asserted for one period of the reference clock CK_TR0 (in this case, active H). As a result, the load / shift selection selectors 258_1 to 258_n * m of each column select the data digitally converted by the AD conversion units 25b_1 to 254_n * m and apply them to the D input terminals of the D-type flip-flops 310_1 to 310_n * m. Supply.

  At the same time, the clock generation unit 340 first takes in the data storage control signal MEMO in synchronization with the falling edge of the reference clock CK_TR0 by the D-type flip-flop 342, and ANDs the AND of the non-inverted output and the reference clock CK_TR0. Therefore, the sub clock SUBCK is output to the sub clock line 350 by only one clock. Thereby, each D-type flip-flop 310 captures and holds the data digitally converted by the AD converter 25b via the load / shift selection selector 258 over the entire column in synchronization with the rising edge of the sub clock SUBCK. To do. At this timing t54, the output of the output driver 320 is output to the horizontal signal line 18.

  Further, at the clock timing next to the reference clock CK_TR0, the load shift selection signal LD is negated (set to inactive L), and the load shift selection selector 258 receives data from the D-type flip-flop 310 in the other column. Is transferred to the D-type flip-flop 310 in its own column, and the shift operation is performed.

  The data C_2 of the adjacent D-type flip-flop 310_2 is moved to the D-type flip-flop 310_1 located on the leftmost side, and the D-type flip-flop 310_1 outputs the data C_2 to the output driver 320. That is, data shifted by one column at the next clock timing is transferred to the output circuit 28 via the horizontal signal line 18 and output. At this time, the L level is input to the D-type flip-flop 310_n * m in the final stage (the rightmost side in FIG. 5) via the load / shift selection selector 258_n * m.

  Similarly, by repeating such a clock-synchronized shift operation for all columns (in this example, for n * m columns), data in all columns is sequentially output. The horizontal data transfer for all the columns is completed.

  Thus, according to the configuration and operation of the column processing unit 26 (particularly the horizontal data transfer sub-block 300) of the present embodiment shown in FIG. 5, the number of output drivers 320 connected to the horizontal signal line 18 is one. Can be reduced to one. In the first example shown in FIG. 2, in the case of n (blocks) × m (number of columns per block), the number of columns can be reduced to 1 / m compared to the comparative example shown in FIG. In this case, only one output driver 320 needs to be connected to the horizontal signal line 18, and in comparison with the column processing unit 26 of the first example, a significant reduction can be achieved and a higher-speed horizontal data transfer operation can be performed. That is easy to understand.

  In the column processing unit 26 of the second example, as in the first example, a fixed logic level (L level in the previous example) is input to the terminal D-type flip-flop 310_n * m to perform the shift operation. This eliminates unnecessary signal transitions. This brings about an effect of further reducing power consumption.

  Further, the horizontal signal line 18 that is a bus line may be one system as in the comparative example and the first example. As in Patent Document 1, the number of output terminals may increase, There is no problem that multiplex processing is necessary after 18 (output side).

<Comparison between the first example and the second example>
FIG. 6 is a diagram comparing the effects of the first example and the second example in which the data storage unit 256 is shifted when data is output to the horizontal signal line 18. In FIG. 6, the horizontal axis indicates the number of blocks n, the solid line L1 indicates the load capacity of the horizontal signal line 18 in relation to the number of blocks n, and the dotted line L2 indicates the power consumption during the shift operation in relation to the number of blocks n. Show.

  In the column processing unit 26 of the second example, when the data is output to the horizontal signal line 18 without dividing the block, the entire data storage units 256 of all the columns are collectively operated as one shift register. Therefore, it is considered that “the number of blocks = 1” in practice, and there is a concern about an increase in power consumption during the shift operation. That is, in terms of reducing the load capacity of the horizontal signal line 18, the configuration of the second example with one output driver 320 is very advantageous, but when the shift operation is performed on the entire column, the D type Since the through current of the flip-flop 310 is large, the power consumption increases.

  In order to reduce the power consumption during the shift operation, the mechanism of the first example in which the blocks are divided is adopted. In this case, the number of output drivers 320 corresponding to the number of blocks is required, and the horizontal signal line The 18 load capacity increases accordingly.

  That is, when a configuration is adopted in which the data storage unit 256 is shifted when data is output to the horizontal signal line 18, there is a trade-off between the load capacity reduction effect of the horizontal signal line 18 and the power consumption reduction during the shift operation. If you try to prioritize one of them, the other will be sacrificed, and you cannot increase the effect of one without adversely affecting the other (without reducing the effect of the other) .

  In consideration of these viewpoints, the power consumption during the shift operation and the load capacity of the horizontal signal line 18 are taken into consideration, and a balance is reached between the power consumption reduction effect and the load capacity reduction effect. As a matter of fact, it is considered appropriate to adopt a configuration in which the number of blocks is set to an appropriate value while actually using the mechanism of the first example.

<Details around data storage and load / shift selection selector; third example>
7 to 11 are diagrams showing a third example of a detailed configuration of the column processing unit 26 (particularly, around the data storage unit 256 and the load / shift selection selector 258) shown in FIG.

  The third example of the detailed configuration of the column processing unit 26 (hereinafter referred to as the column processing unit 26 of the third example) is the first example described above that shifts the data storage unit 256 when data is output to the horizontal signal line 18. Unlike the second example, the method is characterized in that data is output to the horizontal signal line 18 by a simple data selector method.

  Similar to the first example, the idea of grouping can be adopted (third example (part 1) shown in FIG. 7). In addition, while adopting the idea of grouping, it is also possible to adopt a mechanism for arranging a plurality of data selector configurations (only two or more stages are required) (third example shown in FIG. 8 (part 2) to FIG. 10). Third example (part 4)). Further, as in the second example, all the columns may be switched together without performing grouping (third example (part 5) shown in FIG. 11).

  In the case of grouping, it is preferable to reduce power consumption by taking a mechanism to stop circuit operations of invalid blocks that are not related to the data output operation by switching the power supply for each block.

  In the first example and the second example, when the number of output drivers 320 connected to the horizontal signal line 18 is reduced, the D-type flip-flop 310 constituting the data storage unit 256 is connected to the shift register system for load / shift selection. The output driver 320 is provided only in one D-type flip-flop 310 which is switched through the selector 258 and serves as an output stage thereof.

  On the other hand, in the third example, the D-type flip-flop 310 is used while directly using the mechanism of the horizontal scanning unit 12 for switching which output of the D-type flip-flop 310 constituting the data storage unit 256 is to be transferred. The number of output drivers 320 smaller than the number of columns is arranged between the horizontal signal line 18 and the horizontal signal line 18 to avoid the D-type flip-flops 310 in each column being directly connected to the horizontal signal line 18 as they are. Thus, the load capacity of the horizontal signal line 18 is reduced.

  For example, in the column processing unit 26 of the third example (part 1) shown in FIG. 7, as in the first example, the idea of grouping is adopted and one output driver 320 is provided for each group. Hereinafter, each block having a plurality of D-type flip-flops 310 and one output driver 320 is referred to as a horizontal data transfer sub-block 300. For example, m D-type flip-flops 310 and one output driver 320 are provided in each block, and n horizontal data transfer sub-blocks 300 are provided.

  Also here, in order to distinguish each of the D-type flip-flop 310 and the output driver 320, first, a number for distinguishing the blocks from “_1” to “_n” is given after each reference, and then, “_1”. The identification number in the block is given by “_m” (partially omitted in the figure). As a whole, there will be n * m columns.

  The D-type flip-flop 310 receives the output (non-inverted output) of the AD conversion unit 25b in the column corresponding to the D input terminal, and the load / shift selection signal LD is input from the communication / timing control unit 20 to the clock terminal CK. To do. Further, horizontal data transfer clocks φH_1_1 to φH_n_m from the horizontal scanning unit 12 are supplied to the output enable terminal OE.

  The output driver 320 commonly connects its input to each output of each D-type flip-flop 310 belonging to its own group, and connects its output to the output circuit 28 via the horizontal signal line 18 that is a bus line.

  A combination of the output enable function of the D-type flip-flop 310 of each column and the output enable function of the plurality of output drivers 320 constitutes a practical data selector.

  Further, the horizontal scanning unit 12 (referred to as the horizontal scanning unit 12 in the third example (1)) corresponding to the column processing unit 26 in the third example (part 1) is ORed for each horizontal data transfer sub-block 300. A gate 360 is provided. Each OR gate 360 receives clock groups φH_1 to φH_n output from the horizontal decoder 12a as the horizontal address setting unit, that is, horizontal data transfer clocks φH_1_1 to φH_1_m,..., ΦH_n_1 to φH_n_m.

  Each OR gate 360_1 to 360_n takes the logical sum of horizontal data transfer clocks φH_1_1 to φH_1_m,... Output to the output enable terminal OE of the output driver 320 to be output.

  Each of the output drivers 320_1 to 320_n is input when the corresponding block selection signal φN_1 to G_n is active (in this example, H (high) level) (that is, when the output enable terminal OE is at H level). The information is transferred to the output circuit 28 through the horizontal signal line 18.

  Further, in the column processing unit 26 of the third example (part 2) shown in FIG. 8, the output driver has a two-stage configuration. For example, the n group is further divided into k groups having j blocks (j = 2 in the figure). The outputs of the output drivers 320_1 to 320_j of j blocks are connected in common to the inputs of the second stage output drivers 322_1 to 322_k, and the outputs of the output drivers 322_1 to 322_k are connected via the horizontal signal line 18 which is a bus line. Connected to the output circuit 28.

  A combination of the output enable function of the D-type flip-flop 310 of each column and the output enable function of the plurality of output drivers 320 and 322 respectively constitutes a virtual data selector.

  The horizontal scanning unit 12 (referred to as the horizontal scanning unit 12 in the third example (2)) corresponding to the column processing unit 26 in the third example (part 2) is ORed so as to correspond to each of the output drivers 322. A gate 362 is included. Each OR gate 362 receives a block selection signal φN output from each OR gate 360 of the group to which the output driver 322 belongs. Each OR gate 362 takes a logical sum of the input block selection signal φN, and outputs the result (hereinafter referred to as block selection signal) φK_1 to φK_n to the output enable terminal OE of the corresponding output driver 322, respectively. .

  Each of the output drivers 322_1 to 320_k is input when the corresponding block selection signals φK_1 to G_k are active (in this example, H (high) level) (that is, when the output enable terminal OE is at H level). The information is transferred to the output circuit 28 through the horizontal signal line 18.

  Further, the column processing unit 26 of the third example (part 3) shown in FIG. 9 and the third example (part 4) shown in FIG. 10 is an example in which the output driver has three or more stages. In the third example (part 2), one output driver 320 is provided as a middle data selector between the data storage unit 256 and the lowermost output driver 322. However, this may be two or more stages. .

  In this case, as shown in FIG. 9 and FIG. 10, the lower side of the output drivers 320 * (* indicates az indicating the stage) and the output driver 322 sends the output data on the upper stage side of itself to the bus line. It receives via 18a-18z, and is comprised so that it may send to the lower stage side rather than itself. An inverted pyramid configuration of the output driver group having the topmost output driver 322 as the apex and the topmost D-type flip-flop 310 as the base is created.

  In the figure, the OR gates (360a to 360z and 362) for controlling the output enable terminals of the output drivers 320a to 320z and 322 in each stage are omitted, but the OR gate outputs on the previous stage side are sequentially shown. It is provided so as to correspond to the grouping of each stage.

  Also in these cases, one output driver 322 connected to the horizontal signal line 18 may be provided by commonly connecting the output side bus line 18z of the lowermost output driver 320z as shown in FIG. Alternatively, as shown in FIG. 10, the bus lines 18z on the output side of the output driver 320z at the lowest stage may be grouped and provided one for each group.

  Even in such a configuration, in principle, only the lowermost output driver 322 affects the parasitic capacitance with respect to the horizontal signal line 18, and the load capacity of the horizontal signal line 18 can be extremely reduced.

  On the other hand, in the column processing unit 26 of the third example (No. 5) shown in FIG. 11, no grouping is performed, and one output driver 320 is commonly used for the data storage units 256 (D-type flip-flops 310) of all columns. Is provided. The output driver 320 connects its output to the output circuit 28 via the horizontal signal line 18 that is a bus line, and the output enable terminal OE replaces the block selection signals φN_1 to φN_n from the OR gate 360 with the output driver. An output permission signal OEN that enables the operation of 320 is input from the communication / timing control unit 20.

  When the output enable signal OEN is active (in this example, set to H (high) level) (that is, when the output enable terminal OE is at H level), the output driver 320 sends the input information to the horizontal signal line 18. To the output circuit 28. The output enable function of the D-type flip-flop 310 of each column constitutes a de facto data selector, and the select output is output to the horizontal signal line 18 via the output driver 320.

  As can be inferred from the comparison between FIGS. 7 to 10 and FIG. 11, in the configuration of the third example (No. 5), the horizontal signal line 18 that is a bus line connected to the output side of the output driver 320 is used. The circuit format is changed to a mechanism in which data is transferred by a simple data selector method with the entire column as one unit, and the horizontal signal line 18 (bus line) is connected by one output driver 320, thereby generating a horizontal signal. The load capacity connected to the line 18 is greatly reduced, and as a result, high-speed operation is realized.

<Imaging device>
FIG. 12 is a diagram illustrating a schematic configuration of an imaging apparatus (camera system) which is an example of a physical information acquisition apparatus using a mechanism similar to that of the solid-state imaging apparatus 1 of the present embodiment described above. The imaging device 8 is an imaging device that obtains a visible light color image.

  Specifically, the imaging device 8 includes a photographing lens 802 that guides light L carrying an image of the subject Z under the light source 801 such as sunlight or a fluorescent lamp to the imaging device side, and an optical lens. A low-pass filter 804, a color filter group 812 in which, for example, R, G, and B color filters are arranged in a Bayer array, a pixel array unit 10, a drive control unit 7 that drives the pixel array unit 10, and a pixel array unit 10 A column processing unit 26 that performs CDS processing, AD conversion processing, and the like on the pixel signal output from, and a camera signal processing unit 810 that processes imaging data output from the column processing unit 26.

  The camera signal processing unit 810 includes an imaging signal processing unit 820 and a camera control unit 900 that functions as a main control unit that controls the entire imaging apparatus 8. The imaging signal processing unit 820 outputs a digital imaging signal supplied from the column AD circuit 25b (see FIG. 1) of the column processing unit 26 as R (red), when a color filter other than the primary color filter is used. A signal separation unit 822 having a primary color separation function for separating primary color signals of G (green) and B (blue), and a color signal C based on the primary color signals R, G, and B separated by the signal separation unit 822 And a color signal processing unit 830 that performs signal processing.

  The imaging signal processing unit 820 also converts the luminance signal Y / color signal C into a luminance signal processing unit 840 that performs signal processing on the luminance signal Y based on the primary color signals R, G, and B separated by the signal separation unit 822. And an encoder unit 860 that generates a video signal VD based on the encoder 860.

  The camera control unit 900 of the present embodiment is a microprocessor that forms the center of an electronic computer whose representative example is a CPU (Central Processing Unit) in which calculation and control functions performed by a computer are integrated into an ultra-small integrated circuit. 902, a ROM (Read Only Memory) 904 that is a read-only storage unit, a RAM (Random Access Memory) 906 that is an example of a volatile storage unit that can be written and read at any time, and others that are not illustrated The peripheral member is included. The microprocessor 902, the ROM 904, and the RAM 906 are collectively referred to as a microcomputer.

  In the above description, the “volatile storage unit” means a storage unit in which the stored contents are lost when the power of the apparatus is turned off. On the other hand, the “nonvolatile storage unit” means a storage unit in a form that keeps stored contents even when the main power supply of the apparatus is turned off. Any memory device can be used as long as it can retain the stored contents. The semiconductor memory device itself is not limited to a nonvolatile memory device, and a backup power supply is provided to make a volatile memory device “nonvolatile”. You may comprise as follows.

  The camera control unit 900 controls the entire system. The ROM 904 stores a control program for the camera control unit 900. In this example, in particular, the camera control unit 900 stores a program for setting on / off timings of various control pulses. The RAM 906 stores data for the camera control unit 900 to perform various processes.

  The camera control unit 900 is configured so that a recording medium 924 such as a memory card can be inserted and removed, and can be connected to a communication network such as the Internet. For example, the camera control unit 900 includes a memory reading unit 907 and a communication I / F (interface) 908 in addition to the microprocessor 902, the ROM 904, and the RAM 906.

  The recording medium 924 includes, for example, program data for causing the microprocessor 902 to perform software processing, a convergence range of the photometric data DL based on the luminance system signal from the luminance signal processing unit 840, and exposure control processing (including electronic shutter control). It is used for registering data such as various set values such as on / off timing of various control pulses for the purpose.

  The memory reading unit 907 stores (installs) the data read from the recording medium 924 in the RAM 906. The communication I / F 908 mediates transfer of communication data with a communication network such as the Internet.

  In addition, although such an imaging device 8 shows the drive control unit 7 and the column processing unit 26 in a module form separately from the pixel array unit 10, as described for the solid-state imaging device 1, Needless to say, the one-chip solid-state imaging device 1 integrally formed on the same semiconductor substrate as the pixel array unit 10 may be used.

  In the figure, in addition to the pixel array unit 10, the drive control unit 7, the column processing unit 26, and the camera signal processing unit 810, an optical system such as a photographing lens 802, an optical low-pass filter 804, or an infrared light cut filter 805 is provided. In this state, the imaging device 8 is shown. This aspect is suitable for a module-like form having an imaging function packaged together.

  Here, in relation to the modules in the solid-state imaging device 1 described above, as shown in the figure, the pixel array unit 10 (imaging unit), the column processing unit 26 having an AD conversion function and a difference (CDS) processing function, and the like A solid-state imaging device in the form of a module having an imaging function in a state where signal processing units closely related to the pixel array unit 10 side (excluding the camera signal processing unit following the column processing unit 26) are packaged together 1 is provided, and a camera signal processing unit 810, which is the remaining signal processing unit, is provided in the subsequent stage of the solid-state imaging device 1 provided in the module form so that the entire imaging device 8 is configured. Also good.

  Alternatively, although not shown, the solid-state imaging device 1 is provided in a modular form having an imaging function in a state where the pixel array unit 10 and the optical system such as the photographing lens 802 are packaged together. In addition to the solid-state imaging device 1 provided in the form of a module, a camera signal processing unit 810 may be provided in the module to constitute the entire imaging device 8.

  Further, as a module form in the solid-state imaging device 1, a camera signal processing unit 810 corresponding to the camera signal processing unit 200 may be included. In this case, the solid-state imaging device 1 and the imaging device 8 are practically the same. It can also be regarded as a thing.

  Such an imaging device 8 is provided as a portable device having an imaging function, for example, for performing “imaging”. Note that “imaging” includes not only capturing an image during normal camera shooting but also includes fingerprint detection in a broad sense.

  The imaging device 8 having such a configuration is configured to include all the functions of the solid-state imaging device 1 described above, and can be the same as the basic configuration and operation of the solid-state imaging device 1 described above. By applying any of the above-described methods as the column processing unit 26 or the horizontal scanning unit 12, the problem of the load capacity on the horizontal signal line 18 in horizontal data transfer can be solved.

It is a schematic block diagram of the CMOS solid-state imaging device which is one Embodiment of the solid-state imaging device concerning this invention. It is a figure which shows the 1st example of a detailed structure of a column process part. It is a figure which shows the comparative example (henceforth a comparative example) with respect to the structure of the column process part of the 1st example shown in FIG. 3 is a timing chart for explaining the operation of the column processing unit of the first example shown in FIG. 2. It is a figure which shows the 2nd example of a detailed structure of a column process part. It is the figure which compared the effect of the 1st example and the 2nd example. It is a figure which shows the 3rd example (the 1) of a detailed structure of a column process part. It is a figure which shows the 3rd example (the 2) of a detailed structure of a column process part. It is a figure which shows the 3rd example (the 3) of a detailed structure of a column process part. It is a figure which shows the 3rd example (the 4) of a detailed structure of a column process part. It is a figure which shows the 3rd example (the 5) of a detailed structure of a column process part. It is a figure which shows schematic structure of the imaging device which is an example of the physical information acquisition apparatus using the structure similar to the solid-state imaging device of this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 10 ... Pixel array part, 12 ... Horizontal scanning part, 12a ... Horizontal decoder, 12b ... Horizontal drive part, 14 ... Vertical scanning part, 14a ... Vertical decoder, 14b ... Vertical drive part, 15 ... Row control Line 18, Horizontal signal line 19, Vertical signal line 20, Communication / timing control section 24, Read current source section 25, Column AD circuit 256, Data storage section 258 Load / shift selection selector (data Switching unit), 25a ... difference processing unit, 25b ... AD conversion unit, 26 ... column processing unit, 28 ... output circuit, 3 ... unit pixel, 300 ... horizontal transfer sub-block, 310 ... D-type flip-flop (data holding unit) 320, 322,... Output driver, 340, clock generation unit, 7 ... drive control unit, 8 ... imaging device, 900 ... camera control unit (main control unit)

Claims (11)

A pixel array unit in which unit pixels are arranged in a matrix;
A vertical scanning unit that reads an analog pixel signal from each unit pixel of the pixel array unit;
An AD conversion unit provided for each column for converting an analog pixel signal read from each unit pixel of the pixel array unit into digital data;
A data holding unit that is provided in a subsequent stage of the AD conversion unit of each column and holds digital data converted by the AD conversion unit;
A lower number of output drivers than the total number of columns of the data holding unit provided in the subsequent stage of the data holding unit;
A solid-state imaging device comprising: a horizontal scanning unit that transfers digital data output from the output driver to a subsequent circuit. The solid-state imaging device according to claim 1, wherein the vertical scanning unit reads an analog pixel signal for each row from each unit pixel of the pixel array unit. 2. All the columns of the data holding unit are divided into a plurality of blocks each including a plurality of columns, and one output driver is provided after one data holding unit per block. The solid-state imaging device described in 1. The solid-state imaging device according to claim 3, wherein the circuit operation of an invalid block not related to the data output operation is stopped. 2. The solid-state imaging device according to claim 1, wherein one output driver is provided in a subsequent stage of any one of the data holding units for all columns of the data holding unit. For each column, a data switching unit is provided between the AD conversion unit and the data holding unit,
In the data switching unit, one input is connected to the output side of the AD conversion unit of the own column, the other input is connected to the output side of the data holding unit of the other column, and the AD conversion unit of the own column Transfer the converted digital data to the data holding unit of the own column, and then transfer the digital data output from the data holding unit of the other column to the data holding unit of the own column,
The horizontal scanning unit supplies a clock that enables a data shift operation to the data holding unit,
The solid-state imaging device according to claim 1, wherein the output driver is provided at a subsequent stage of the data holding unit positioned at a head part of the data shift operation. The output driver is provided for each block in which all columns of the data holding unit are divided into a plurality of blocks each including a plurality of columns.
The solid-state imaging device according to claim 6, wherein the horizontal scanning unit sequentially transfers data of all columns to the subsequent stage circuit by sequentially switching blocks that enable the data shift operation. The solid-state imaging device according to claim 6, wherein the horizontal scanning unit stops supplying the clock to a block in which the data shift operation is invalid. The solid-state imaging device according to claim 6, wherein one output driver is provided for all columns. The solid-state imaging device according to claim 6, wherein a constant logic level is input to the other input of the data switching unit located at the end of the data shift operation. A pixel array unit in which unit pixels are arranged in a matrix;
A vertical scanning unit that reads an analog pixel signal from each unit pixel of the pixel array unit;
An AD conversion unit provided for each column for converting an analog pixel signal read from each unit pixel of the pixel array unit for each row into digital data;
A data holding unit that is provided in a subsequent stage of the AD conversion unit of each column and stores digital data converted by the AD conversion unit;
A lower number of output drivers than the total number of columns of the data holding unit provided in the subsequent stage of the data holding unit;
A horizontal scanning unit for transferring digital data output from the output driver to a subsequent circuit;
An imaging apparatus comprising: a main control unit that generates control information for controlling the vertical scanning unit and the horizontal scanning unit.

Images