JP4894391B2 - Control device - Google Patents

Description

  The present invention relates to a control device that controls an industrial plant and the like, and relates to a control device that is made redundant by a plurality of control units that operate independently of each other and perform synchronization processing with each other at a timing when predetermined processing is completed.

  A control device called CS (control station) that controls industrial plants and the like is equipped with two or more control units to perform processing constantly with high reliability, and each control unit performs the same processing. Some of them are made redundant by redundant or multiplexed control processing. For example, Patent Document 1 discloses a technique related to a processor device that performs the same operation with first and second microprocessors capable of performing arithmetic processing alone and makes the arithmetic processing redundant.

  In each control unit that is duplicated or multiplexed and performs the same arithmetic process independently of each other, a synchronization matching process is performed to shift to the next process when a certain process is completed. In a control device including a plurality of control units that are duplicated or multiplexed, the synchronization processing is performed to synchronize arithmetic processing in each control unit and detect an abnormality in each control unit.

  Here, the synchronization processing performed in the control unit in the conventional control apparatus will be described with reference to FIGS. First, FIG. 4 illustrates a configuration of a conventional control device CS2 that performs processing by duplicating a control unit. As shown in FIG. 4, the control device CS <b> 2 is configured such that the control unit 100 and the control unit 200 are communicably connected to each other via the backboard bus 300.

  The control unit 100 includes a processor 110, an interface controller 120, a main memory 130, a backboard bus controller 140, and a backboard bus controller 150. Similarly, the control unit 200 includes a processor 210, an interface controller 220, an interface controller 220, a main memory 230, a backboard bus controller 240, and a backboard bus controller 250.

  The processor 110 is a so-called CPU (Central Processing Unit) having a ROM (Read Only Memory), an internal RAM (Random Access Memory), and the like (not shown). Data and a processing program are developed in the main memory 130 to perform arithmetic processing. Overall control of the operation processing in the control unit 100 is performed. The interface controller 120 is a DMA (Direct Memory Access) controller, for example, and adjusts data input / output of the processor 110, the main memory 130, the interface, and the like in the control unit 100. The main memory 130 is a DRAM (Dynamic Random Access Memory) or the like, and has a synchronization confirmation area 131 for performing synchronization processing with other control units. The backboard bus controllers 140 and 150 perform data communication by serial transfer with the backboard bus controllers 240 and 250 on the control unit 200 side connected via the serial buses 310 and 320 in the backboard bus 300. The detailed configuration of the control unit 200 is the same as that of the control unit 100, and thus the description thereof is omitted.

  Next, FIG. 5 illustrates an outline of the synchronization matching process. As shown in FIG. 5, the processor 110 of the control unit 100 performs a write access for writing data indicating that the certain calculation process has been completed and data such as the calculation result to the synchronization confirmation area 231 after the certain calculation process. Is performed (step S101). Specifically, in this write access, the processor 110 issues an access request to the backboard bus controller 140 or the backboard bus controller 150 through the interface controller 120. Upon receiving the access request, the backboard bus controller 140 or the backboard bus controller 150 secures the bus right of the serial bus 310 or serial bus 320 to be connected, and sends the write request to the backboard bus controller 240 or backboard on the control unit 200 side. Apply to bus controller 250. The backboard bus controller 240 or the backboard bus controller 250 that has received the write request writes data into the synchronization confirmation area 231 of the main memory 230 via the interface controller 220.

  Similar to the above-described write access from the control unit 100 to the synchronization confirmation area 231, the processor 210 of the control unit 200 writes data indicating the completion of certain computation processing, data such as computation results, and the like to the synchronization confirmation area 131. Write access is performed (step S201).

  Subsequent to step S101, the processor 110 performs read access to the synchronization confirmation area 131 to confirm the stored data, and confirms whether the write access from the control unit 200 side has been completed (step S102). Similarly, after step S201, the processor 210 confirms whether or not the write access from the control unit 100 side is completed (step S202). In other words, in the control units 100 and 200, after the write access to the synchronization confirmation area to other control units, the data in the own synchronization confirmation area is confirmed, so that certain arithmetic processing is completed on the other control unit side. This is a configuration for confirming whether or not.

  Subsequent to step S102, when the processor 110 confirms the write access from the control unit 200 side, the processor 110 performs the write access for clearing the data stored in the synchronization confirmation area 131 (step S103), and the synchronization confirmation area 231. Is executed to check whether or not the data in the synchronization confirmation area 231 has been cleared. If clear is confirmed, the process proceeds to the next calculation process (step S104). Similarly, after step S202, the processor 210 performs write access for clearing data stored in the synchronization confirmation area 231 when confirming write access from the control unit 100 side (step S203). A read access to the confirmation area 131 is executed to check whether or not the data in the synchronization confirmation area 131 has been cleared. If clear is confirmed, the process proceeds to the next calculation process (step S204).

As described above, in the control device CS2, when performing the same arithmetic processing independently from each other in each control unit, when a certain arithmetic processing is completed, the control unit CS2 moves to the synchronization confirmation area on the main memory of the other control unit. Each control unit performs the synchronization matching process using the data access, thereby synchronizing the arithmetic processing in each control unit.
JP 2001-256070 A

  However, in the above-described conventional technology, when any control unit performs write access or read access to another control unit during the synchronization adjustment process, it starts not after acquiring the access right of the backboard bus and the main memory. I can't. For example, even if the local side is performing synchronization processing, the other side may be using the main memory or backboard bus, and unless it is completed, the access right to the main memory and the bus right are acquired. Cannot be performed, and write access or read access cannot be executed. For this reason, it takes a lot of time for the synchronization processing, and there is a possibility that the performance of the arithmetic processing is lowered.

  Further, in the conventional technology, when any control unit performs a write access to another control unit during the synchronization process, if the access becomes an error due to external noise or the like, the write access is performed again. As a result, there is a possibility that the synchronization alignment process may be shifted. For example, if a signal indicating that the write access is completed is written normally during the first write access from any control unit to the other control unit and is affected by noise, the other control unit confirms the synchronization. Although the data in the area is confirmed and cleared, any control unit executes write access again and writes the data in the synchronization confirmation area after the clearing, resulting in a deviation in the synchronization matching process. For this reason, in the prior art, there is a possibility that the redundant arithmetic processing cannot be continued due to the influence of noise.

  The present invention has been made in view of such problems, and an object of the present invention is to use a plurality of control units that operate independently of each other and perform synchronization processing with each other at a timing when predetermined processing is completed. It is to provide a technique for improving the performance and noise resistance of arithmetic processing in a redundant control device.

In order to solve the above problems, the invention described in claim 1 is connected to each other via a serial bus, and operates independently of each other under the control of the respective processors, and one of the processors is actually working. In the control device that is made redundant by two control units that perform the same operation by the other processor, wait at the timing when the predetermined processing is completed, and perform synchronization processing with each other,
Each of the two control units is
A synchronization register for storing synchronization adjustment processing data;
A communication unit that constantly transmits a frame to a connected control unit via the serial bus and can directly access the synchronization register;
With
The synchronization register includes a synchronization register for storing synchronization processing data to be transmitted to the control unit at the connection destination, and a synchronization register for storing synchronization processing data transmitted from the control unit at the connection destination. Have
The communication unit transmits synchronization adjustment processing data stored in the own-side synchronization register of the own control unit to the connection-destination control unit in the always-on frame, and is transmitted from the connection-destination control unit in the always-on frame. When the adjustment processing data is received, it is stored in the counterpart synchronization register of the own control unit ,
The processor stores data indicating the end of the arithmetic processing in the local synchronization register as synchronization processing data when a certain arithmetic processing of the own control unit is completed, and is stored in the counterpart synchronization register. when the synchronizing process data is data indicating the end of the arithmetic process of the control unit of the destination, the self side synchronization as the synchronizing process data data indicating the confirmation of synchronization between the connection destination of the control unit stored in the register, wherein when mating the synchronizing synchronization register Ru stored processed data is data indicating the confirmation of synchronization, that the own control unit and the control unit of the connection destination is determined to confirm the synchronization It is characterized by.

According to a second aspect of the present invention, in the first aspect of the present invention, the communication unit adds check data for checking an error of data to be transmitted to the always-on frame.

According to the present invention, in the control device made redundant by the two control units that operate independently of each other under the control of the respective processors and perform the synchronization processing with each other at the timing when the predetermined processing is completed, Each of the two control units can directly access the synchronization register for storing the synchronization processing data of the arithmetic processing, so that the communication unit communicating with the connected control unit can be accessed without affecting the arithmetic processing of the processor. The synchronization processing data can be transmitted / received to / from the connected control unit, and the performance of the arithmetic processing can be improved. Also, in communication with the connected control unit, synchronization processing data is transmitted using constantly transmitted and received frames, so even if one of the always affected frames is affected by noise, it is compensated with another always frame. Noise resistance can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments. Further, the embodiment of the present invention shows the most preferable embodiment of the invention, and the uses and terms of the invention are not limited to this.

  FIG. 1 is a block diagram schematically showing a functional configuration of a control device CS including a control unit 1 and a control unit 2 that are connected to be communicable with each other. FIG. 2A is a conceptual diagram illustrating an outline of data transmission in the serial buses 3a and 3b, and FIG. 2B is a conceptual diagram illustrating an outline of a frame related to data transmission. FIG. 3 is a conceptual diagram illustrating an overview of the synchronization processing in the control units 1 and 2 of the control device CS.

  First, the configuration of the control device CS having the control units 1 and 2 according to the present invention will be described. As shown in FIG. 1, the control device CS is configured such that the control unit 1 and the control unit 2 are communicably connected via a backboard bus 3.

  The control unit 1 includes a processor 11, an interface controller 12, a main memory 13, a communication unit 14, and a synchronization register 15. Similarly, the control unit 2 includes a processor 21, an interface controller 22, a main memory 23, a communication unit 24, and a synchronization register 25. Note that the detailed configuration of the control unit 2 is the same as that of the control unit 1, and thus the description thereof is omitted.

  The processor 11 is a so-called CPU having a ROM or an internal RAM (not shown). The processor 11 develops data, processing programs, and the like on the interface controller 12 and performs overall control of arithmetic processing and overall operation processing in the control unit 1. The interface controller 12 is a DMA controller, for example, and adjusts data input / output of the processor 11, main memory 13, communication unit 14, synchronization register 15, etc. in the control unit 1. The main memory 13 is a DRAM or the like that provides a work area related to the processing of the processor 11.

  The communication unit 14 includes an interface (not shown) connected to the backboard bus 3 and performs data communication via the backboard bus 3. The communication unit 14 includes backboard bus controllers 14 a and 14 b that perform data communication by serial transmission with the control unit 2 connected via the serial buses 3 a and 3 b of the backboard bus 3.

  The backboard bus controllers 14 a and 14 b directly access the synchronization register 15 without passing through the interface controller 12 based on data transmitted from other control units such as the control unit 2, and store data in the synchronization register 15. It is a configuration capable of writing. Specifically, data transmitted from another control unit is written to a counterpart synchronization register 15b described later. The backboard bus controllers 14a and 14b directly access the synchronization register 15 and transmit serial data based on the data stored in the synchronization register 15 to the serial buses 3a and 3b. Specifically, serial data based on data read with reference to a self-side synchronization register 15a described later is transmitted.

  Therefore, in the control unit 1, the interface controller 12 is used when writing data from the communication unit 14 to the synchronization register 15 or when transmitting data from the communication unit 14 with reference to the data stored in the synchronization register 15. Therefore, the arithmetic processing in the processor 11 is not affected, and the performance of the arithmetic processing can be improved.

  The synchronization register 15 is a storage element that can be accessed from the processor 11 via the interface controller 12 or directly from the backboard bus controllers 14a and 14b. The synchronization register 15 stores, as synchronization processing data, data indicating the end of certain arithmetic processing and data such as the result value of the certain arithmetic processing, and stores the local data. A counterpart synchronization register 15b for storing data transmitted from the register 15a and another control unit is provided.

  In the other party synchronization register 15b, the data stored in the own synchronization register 15a is cleared (stores Null data or the like), and the data transmitted from another control unit clears the data in the other party synchronization register 15b. In this case, the data stored in the counterpart synchronization register 15b is cleared when it is an instruction to perform (such as Null data). The data stored in the counterpart synchronization register 15b is cleared when the communication unit 14 clears the data of the counterpart synchronization register 15b (when writing null data or the like) under the control of the processor 11. A configuration in which data in the register 15a is read and compared may be used, or a configuration in which a logic circuit included in the synchronization register 15 (not shown) is used may be used.

  Next, serial data transmitted from the backboard bus controllers 14a and 14b to the serial buses 3a and 3b will be described. As shown in FIG. 2A, the serial transmission performed by the backboard bus controllers 14a and 14b is a transmission control procedure using a frame such as HDLC (High Level Data Link Control), for example. Other than the time of data transmission to the device, the frames are always transmitted as shown in the frames Fr11 to Fr14 and the frames Fr21 to Fr26.

  In this always-on frame, data read by the backboard bus controllers 14a and 14b with reference to the own synchronization register 15a is set. Specifically, as shown in FIG. 2A, when the synchronization processing data stored in the local synchronization register 15a is Null before time T1, and another data is set after time T1. The data is set in the continuous frames (frames Fr12 to 14, Fr23 to 26) transmitted after the time T1.

  Therefore, the backboard bus controllers 14a and 14b can transmit the synchronization processing data necessary for the synchronization processing without acquiring the bus right of the serial bus. Further, even when any one of the serial buses is in use, data can be transmitted without acquiring the bus right of the other serial bus.

  As shown in FIG. 2B, the structures of the frames Fr11 to Fr14 and the frames Fr21 to Fr26 include data Fd to be transmitted between a start flag Fs indicating the start of the frame and an end flag Fe indicating the end of the frame. It has check data FCS for error control of the frame. The data Fd includes data read from the above-described counterpart synchronization register 15b, and the check data FCS includes data for detecting an error in data in a frame using, for example, a CRC (Cyclic Redundancy Check) method.

  For this reason, the backboard bus controllers 14a, 14b and other control units when receiving the above-described always-on frame perform data error detection based on the check data FCS, so that noise or the like is present in any always-on frame. Even when the synchronization processing data necessary for the synchronization processing is erroneously transmitted, the data can be discarded before being stored in the synchronization register 15, and noise resistance during the synchronization processing can be reduced. Can be improved.

  Next, synchronization processing performed in the control device CS between the control unit 1 and the control unit 2 will be described in detail with reference to FIG. This synchronization matching process is performed on the control unit 1 side (steps S11 to S14) performed under the control of the processor 11 and on the control unit 2 side (steps S21 to S24) performed under the control of the processor 21. ).

  As shown in FIG. 3, the processor 11 of the control unit 1 automatically receives synchronization processing data such as data indicating the completion of the certain calculation process and calculation results after the certain calculation process (time T1). Write to the side synchronization register 15a (step S11). As described above, the data written in the own-side synchronization register 15a is transmitted to the backboard bus controllers 24a and 24b via the backboard bus controllers 14a and 14b that operate under the control of the processor 11, and is transmitted to the counterpart side. It is written into the synchronization register 25b.

  Similar to the control unit 1, the processor 11 of the control unit 2 writes the synchronization processing data into the own-side synchronization register 25a after a certain calculation process (time T2) (step S21). The data written in the self-side synchronization register 25a is transmitted to the backboard bus controllers 14a and 14b via the backboard bus controllers 24a and 24b operating under the control of the processor 21, as in the case of the control unit 1 described above. And is written to the counterpart synchronization register 15b.

  Subsequent to step S11, the processor 11 performs read access to the counterpart synchronization register 15b to check the stored data, and data indicating that certain arithmetic processing transmitted from the control unit 2 side is completed is stored. It is confirmed whether it is (step S12). Similarly, after step S21, the processor 21 confirms the stored data by performing read access to the counterpart synchronization register 25b, and data indicating that certain arithmetic processing transmitted from the control unit 1 side has been completed. Is stored (step S22).

  That is, in the control units 1 and 2, when a certain arithmetic process is completed, the other synchronization unit side is confirmed by checking the data in the other-side synchronization register after writing the synchronization processing data to the own-side synchronization register. In this configuration, it is confirmed whether or not certain arithmetic processing has been completed.

  Subsequent to step S12, when the processor 11 confirms the end of certain arithmetic processing on the control unit 2 side, that is, the synchronization on the control unit 2 side, the processor 11 synchronizes data indicating confirmation of the synchronization (for example, Null data). In order to store the data in the register 15a, a write access for clearing the data stored in the local synchronization register 15a is performed (step S13), and a read access to the counterpart synchronization register 15b is executed to execute the counterpart synchronization register 15b. It is confirmed whether or not the data has been cleared. If clear is confirmed, the process proceeds to the next calculation process (step S14).

  Similarly, after step S22, the processor 21 performs a write access to clear the data stored in the local synchronization register 25a when confirming the end of certain arithmetic processing on the control unit 1 side (step S22). S23) The read access to the counterpart synchronization register 25b is executed to check whether or not the data in the counterpart synchronization register 25b has been cleared. If clear is confirmed, the process proceeds to the next calculation process (step S24). ).

  As described above, the clearing of the data in the own-side synchronization register 15a in step S13 is reflected in the constant frame transmitted via the communication unit 14 and transmitted to the control unit 2 side. Further, when the data of the self-synchronization register 15a is cleared and the data of the constant frame transmitted from the control unit 2 side is data for instructing the clear, that is, the control unit 2 performs certain arithmetic processing on the control unit 1 side. When it is confirmed that the control unit 1 has finished a certain calculation process on the control unit 2 side, the data in the counterpart synchronization register 15b is cleared.

  For this reason, the control unit 1 can confirm the end of the synchronization for shifting to the next arithmetic processing only by confirming the clearing of the data in the counterpart synchronization register 15b in step S14. After completion of the arithmetic processing, the performance of the arithmetic processing can be improved without accessing another control unit via the backboard bus 3 for confirming the end of synchronization.

  In addition, since the data in the counterpart synchronization register 15b is cleared only when the control unit 1 and the control unit 2 finish certain arithmetic processing, the control unit 1 clears the counterpart synchronization register 15b. By confirming, it is possible to surely confirm the end of the synchronization matching process.

  As described above, in the control device CS that is made redundant by the control unit 2 and the control unit 1 that are communicably connected to each other via the backboard bus 3, each control unit stores synchronization processing data. The communication unit 14 includes a communication unit 14 that always transmits and receives frames to and from the synchronization register 15 and the control unit 2 and can directly access the synchronization register 15. The communication unit 14 is synchronized with the synchronization stored in the synchronization register 15. Such data is always transmitted / received to / from the connected control unit using a frame.

  For this reason, in the control device CS, since the communication unit 14 can directly access the synchronization register 15 when transmitting the synchronization processing data, the performance of the arithmetic processing can be improved without affecting the arithmetic processing of the processors 11 and 21. Can be improved. In addition, since the communication unit 14 always transmits synchronization processing data using continuous frames that are always transmitted and received from each other, even if any of the continuous frames is affected by noise, it can be compensated by other continuous frames. Can be improved.

  Note that the description in the present embodiment shows an example of the present invention, and the present invention is not limited to this. The detailed configuration and detailed operation of the control units 1 and 2 in the present invention can be changed as appropriate without departing from the spirit of the present invention.

  For example, in the present embodiment, the synchronization alignment processing is performed under the control of the processors 11 and 21, that is, the configuration is performed according to the processing of the application program executed by the processors 11 and 21, but the communication unit 14 (backboard A configuration executed by the bus controllers 14a and 14b) or a configuration including a dedicated controller for controlling the synchronization process as hardware may be used. In this case, access and confirmation processing for synchronization can be performed without imposing a burden on the processors 11 and 21, which leads to further improvement in performance.

  In addition, the data indicating the confirmation of synchronization is Null data, and the configuration in which the data is cleared when the data indicating the confirmation of synchronization is stored in the synchronization register 15 is exemplified. There is no particular limitation.

It is a block diagram which shows typically the functional structure of control apparatus CS which has the control unit 1 and the control unit 2 which are connected so that communication is mutually possible. (A) is a conceptual diagram illustrating an outline of data transmission in the serial buses 3a and 3b, and (b) is a conceptual diagram illustrating an outline of a frame related to data transmission. It is a conceptual diagram explaining the outline | summary of the synchronization process in the control units 1 and 2 of the control apparatus CS. It is a block diagram which shows typically the functional structure of the conventional control apparatus CS2. It is a conceptual diagram explaining the outline | summary of the synchronizing process in control apparatus CS2.

Explanation of symbols

CS controller 1, 2 Control unit 3 Backboard bus 3a, 3b Serial bus 11, 21 Processor 12, 22 Interface controller 13, 23 Main memory 14, 24 Communication units 14a, 14b, 24a, 24b Backboard bus controllers 15, 25 Synchronization registers 15a and 25a Self-side synchronization registers 15b and 25b Counter-side synchronization registers Fr11 to Fr26 Frame Fs Start flag Fd Data FCS Check data Fe End flag

Claims (2)

Connected to each other via a serial bus, operate independently of each other under the control of each processor, and while one processor is performing actual work, the other processor executes the same operation, and the predetermined processing is completed In a control device made redundant by two control units that wait at timing and perform synchronization processing with each other,
Each of the two control units is
A synchronization register for storing synchronization adjustment processing data;
A communication unit that constantly transmits a frame to a connected control unit via the serial bus and can directly access the synchronization register;
With
The synchronization register includes a synchronization register for storing synchronization processing data to be transmitted to the control unit at the connection destination, and a synchronization register for storing synchronization processing data transmitted from the control unit at the connection destination. Have
The communication unit transmits synchronization adjustment processing data stored in the own-side synchronization register of the own control unit to the connection-destination control unit in the always-on frame, and is transmitted from the connection-destination control unit in the always-on frame. When the adjustment processing data is received, it is stored in the counterpart synchronization register of the own control unit ,
The processor stores data indicating the end of the arithmetic processing in the local synchronization register as synchronization processing data when a certain arithmetic processing of the own control unit is completed, and is stored in the counterpart synchronization register. when the synchronizing process data is data indicating the end of the arithmetic process of the control unit of the destination, the self side synchronization as the synchronizing process data data indicating the confirmation of synchronization between the connection destination of the control unit stored in the register, wherein when mating the synchronizing synchronization register Ru stored processed data is data indicating the confirmation of synchronization, that the own control unit and the control unit of the connection destination is determined to confirm the synchronization A control device characterized by. The control device according to claim 1 , wherein the communication unit adds check data for checking an error of data to be transmitted to the always-on frame.

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