JP4896322B2 - Sequencer and flat display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a flat display device such as a liquid crystal display device, and more specifically, a control signal generation circuit that supplies a predetermined control signal to a driver circuit that drives each pixel, a sequencer including the control signal generation circuit, and The present invention relates to a flat panel display device including the control signal generation circuit on the same substrate as a pixel and a driver circuit.
[0002]
[Prior art]
Conventionally, in a flat display device represented by a liquid crystal display device, a driver circuit for driving each pixel is often mounted by a TAB method. However, in recent years, due to demands for cost reduction and a narrow frame, the same substrate as the pixel is used. There are also products with driver circuits built on top. However, even in that case, most of the control signals of the driver circuit are supplied as external signals from the integrated LCD controller. Thus, conventionally, since the control signal generating circuit is made in the LCD controller made into an IC, the area of the IC itself is large and the cost is high. The control signal generation circuit is a circuit that generates a control signal for controlling the operation timing of the driver circuit.
[0003]
[Problems to be solved by the invention]
If this control signal generation circuit can be formed on the same substrate as the driver circuit, it can be manufactured by the same process as the driver circuit, and the LCD controller can be simplified, so that the cost can be reduced. However, since the layout area of the control signal generation circuit is large, there is a problem that it is difficult to narrow the frame. Normally, a counter circuit is required to produce a control signal generating circuit. However, a flat display device generally requires a counter circuit of several hundreds of digits, and it has been difficult to reduce the layout area. Here, if a binary counter is used to reduce the layout area, a hazard problem and a decoder circuit become complicated. If a Johnson counter is used to solve the hazard and decoder problems, the number of flip-flop circuits becomes enormous and the layout area cannot be reduced. Thus, it has been difficult to reduce the layout area of the control signal generation circuit without causing problems of hazards and decoders.
[0004]
On the other hand, digital / analog converters (hereinafter referred to as D / A converters), amplifier circuits, and the like included in driver circuits require delicate voltage settings. For this reason, TFT (thin film transistor) threshold voltages and electron mobility are required. Such characteristics need to be manufactured as designed. However, in actuality, it is difficult to manufacture as designed, and if these characteristics are different from the estimate at the time of design, the device does not operate correctly even if a control signal at the time of design is supplied, resulting in display defects. There was also. In such a case, it is necessary to redo the circuit design and improve the manufacturing process, resulting in a decrease in productivity and high cost.
[0005]
SUMMARY OF THE INVENTION A first object of the present invention is to provide a control signal generating circuit capable of reducing the layout area as compared with the prior art and a flat display device having the control signal generating circuit.
[0006]
A second object of the present invention is to provide a sequencer capable of operating a driver circuit correctly even when characteristics such as a threshold voltage are not manufactured as estimated at the time of design, and a flat display device including the sequencer There is to do.
[0007]
Furthermore, a third object of the present invention is to provide a control signal generation circuit capable of realizing a change in the generation timing of a control signal in a short time and a flat display device having the control signal generation circuit. .
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the invention of claim 1 outputs a control signal for controlling the operation of a driver circuit including at least a video data input interface, a gradation selection circuit, a digital / analog converter, and an amplifier circuit. Ru -A sequencer from the gradation selection circuit First Output signal potential And from the digital / analog converter Second Output signal potential And a first comparison circuit for outputting a first state comparison signal according to the comparison result, and from the digital / analog converter The second Output signal potential And from the amplifier circuit Third Output signal potential And a second comparison circuit for outputting a second state comparison signal corresponding to the comparison result When, in front No. 1 status comparison signal Indicates that the first output signal potential does not correspond to the second output signal potential, Digital / analog converter Of The operation timing First to correct Outputs control signals to the digital / analog converter And in front No. 2 status comparison signal Indicates that the second output signal potential does not correspond to the third output signal potential, The amplifier times Road The operation timing Second to correct Output the control signal to the amplifier circuit A control signal generating circuit It is characterized by.
[0011]
The invention of claim 2 is the method of claim 1, wherein Second Output signal potential Is converted into a data format that can be interpreted by the first comparison circuit, and is output to the first comparison circuit; and Third Output signal potential Is converted into a data format that can be interpreted by the second comparison circuit, and is output to the second comparison circuit.
[0020]
Claim 6 In the flat display device in which the pixel portion and the driver circuit are integrally formed on the substrate, the invention is provided as a circuit that generates a control signal for controlling the operation of the driver circuit. Any one of 1 to 5 The sequencer is integrally formed on the substrate.
[0021]
Claim 7 The invention of claim 6 A plurality of pixel electrodes, a switch element connected to each of these pixel electrodes via an electrode wiring, a driver circuit that drives the switch element and writes video data to the pixel electrode, and Any one of 1 to 5 A first electrode substrate on which the sequencer is integrally formed, a second electrode substrate on which counter electrodes opposed to the plurality of pixel electrodes are formed, and a display layer held between the two electrode substrates. It is what.
[0022]
Claim 8 The invention of claim 7 The display layer is a liquid crystal layer.
[0023]
Claim 9 The invention of claim 7 The display layer is an organic EL.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the case where the control signal generation circuit, the sequencer, and the flat display device according to the present invention are applied to the liquid crystal panel, the control signal generation circuit, and the sequencer will be described.
[0030]
First, the circuit configuration of the liquid crystal panel according to this embodiment will be described with reference to FIG. The liquid crystal panel 1 shown in FIG. 13 includes a pixel portion 100 in which a plurality of pixels 10 are formed, a scanning line driver circuit 200, a signal line driver circuit 300, and a control signal generation circuit 400.
[0031]
In this embodiment, the driver circuit integrated liquid crystal panel 1 in which the pixel unit 100, the scanning line driver circuit 200, the signal line driver circuit 300, and the control signal generation circuit 400 are integrally formed on the array substrate 101 is taken as an example. explain. Among these, only the control signal generation circuit 400 or the scanning line driver circuit 200, the signal line driver circuit 300, and the control signal generation circuit 400 may be externally attached.
[0032]
In the pixel portion 100, a plurality of signal lines 11 and a plurality of scanning lines 12 intersecting with the signal lines 11 are arranged in a matrix, and a TFT 13 as a switching element is disposed in the vicinity of the intersection of both lines. . The signal line 11 and the scanning line 12 are electrically insulated by an insulating film (not shown).
[0033]
The source electrode of the TFT 13 is connected to the signal line 11, and the drain electrode is connected to the pixel electrode 14. The counter electrode 15 arranged in parallel with the pixel electrode 14 is formed on a counter substrate (not shown). A liquid crystal 16 is sandwiched between the pixel electrode 14 and the counter electrode 15 to form a capacitor Clc. In addition, an auxiliary capacitor 17 is connected in parallel to the pixel electrode 14 in order to maintain a potential relationship with the counter electrode 15. The auxiliary capacitor 17 forms a capacitor Cs between the pixel electrode 14 and the auxiliary capacitor line 18. The auxiliary capacitance line 18 is electrically connected to the auxiliary capacitance 17 of all the pixels 10 and is given a constant potential from an external circuit (not shown).
[0034]
Similarly, a constant common voltage (Vcom) is applied to the counter electrode 15 from an external circuit (not shown) through a common wiring (not shown). The video data written through the signal line 11 is held for one frame scanning period by the capacitors Clc and Cs.
[0035]
The scanning line driver circuit 200 includes a shift register and a buffer circuit (not shown), and sequentially outputs a scanning signal to each scanning line 12 in accordance with a control signal supplied from a control signal generation circuit (not shown) formed on the array substrate 101. To do.
[0036]
The signal line driver circuit 300 includes a video data input interface, a gradation selection circuit, a D / A converter, and an amplifier circuit, which will be described later. Video signal conversion and signal lines 11 are performed according to control signals supplied from the control signal generation circuit 400. Is writing to.
[0037]
The control signal generation circuit 400 includes a counter circuit, which will be described later, and operates the driver circuit based on an input signal (start pulse) supplied from an external circuit (not shown) and a clock signal having a predetermined cycle. A control signal for controlling is generated and output to each driver circuit.
[0038]
In this embodiment, each of the scanning line driver circuit 200 and the signal line driver circuit 300 has a dedicated control signal generation circuit (not shown for the scanning line driver circuit 200), and these circuits are provided on the array substrate 101. It is assumed that they are integrally formed. In this embodiment, the circuit configuration of the control signal generation circuit 400 that controls the operation of the signal line driver circuit 300 will be described. However, the control signal generation circuits of the respective driver circuits may be integrated.
[0039]
The operation of the liquid crystal panel 1 shown in FIG. 13 will be briefly described. When video data is sequentially written from the signal line driver circuit 300 to the signal line 11 and a scanning signal is output from the scanning line driver circuit 200 to the scanning line 12 in synchronization therewith, all of the data present on the horizontal line are all output. The TFT 13 is turned on, and the video data written to the signal line 11 is applied to a predetermined pixel 10 through the TFT 13. This video data is charged as a signal voltage between the pixel electrode 14 and the counter electrode 15, and the liquid crystal 16 responds to this to display a gradation according to the signal voltage.
[0040]
Next, an embodiment of the control signal generation circuit 400 formed on the array substrate 101 will be described. In the following description, “front stage” and “rear stage” represent the positional relationship in the direction in which the output signal flows between the shift registers, and “middle stage” is output to a latch connected in the shift register. The positional relationship in the direction in which the signal flows is assumed. The “middle stage” includes the final stage.
[0041]
[Embodiment 1]
First, an embodiment of a control signal generation circuit using a Johnson counter, in which the problem of hazard and decoder is solved and the layout area is reduced, will be described.
[0042]
FIG. 2 is a circuit configuration diagram showing a connection relationship between the signal line driver circuit 300 and the control signal generation circuit 400. The signal line driver circuit 300 includes a video data input interface 301, a gradation selection circuit 302, a D / A converter 303, and an amplifier circuit 304.
[0043]
The video data input interface 301 receives video data input from outside via a video bus (not shown), rearranges the video data from serial digital data to parallel digital data, and latches the video data. At this time, the control signal generation circuit 400 outputs a control signal for sampling the video data. The gradation selection circuit 302 performs gradation selection (voltage selection) of the video data rearranged in parallel, and outputs the voltage (video data) obtained by the selection. At this time, the control signal generation circuit 400 outputs a control signal for selecting a gradation. The D / A converter 303 converts the digital video data selected for gradation into analog video data. At this time, the control signal generation circuit 400 outputs a control signal for converting a digital signal into an analog signal. In the amplifier circuit 304, the analog video data is boosted to a necessary potential and written to the signal line 11. At that time, the control signal generation circuit 400 outputs a control signal for controlling the operation of the amplifier circuit 304. In this embodiment, the D / A converter 303 is arranged after the gradation selection circuit 302. However, when the gradation selection circuit 302 selects a gradation, digital video data is converted into analog video data. In the case of conversion, the D / A converter 303 can be omitted.
[0044]
FIG. 3 is a circuit configuration diagram of the control signal generation circuit 400. The control signal generating circuit 400 outputs 2 (n + 1) signals and one weighting signal based on the input clock, and 4 (n) based on the 2 (n + 1) signals and the weighting signal. The decoder circuit 420 outputs n + 1) signals. The input clock signal is supplied from the outside.
[0045]
FIG. 1 is a circuit configuration diagram of the counter circuit 410 shown in FIG. The counter circuit 410 generates a (n + 1) -bit Johnson counter 411 that outputs signals Q0 to Qn based on an input clock signal, a set signal from the signals Q0 and Qn, and a reset source signal from the signals Qn-1 and Qn. And a D latch 413 that generates a reset signal based on the reset source signal, and an RS flip-flop 414 that inputs the set signal and the reset signal and outputs a weighting signal Qw. Of these, the sub-decoder 412, the D latch 413, and the RS flip-flop 414 generate weighting signals Qw for weighting at least two combinations of the signals Q0 to Qn output from the Johnson counter 411. A circuit 415 is configured. Although not shown, the Johnson counter 411 outputs signals Q0 to Qn to the decoder circuit 420, while the weighting signal generation circuit 415 generates signals Q0, Qn-1, Qn to generate the weighting signal Qw. Is output.
[0046]
Next, the operation of the counter circuit 410 configured as described above will be described. Here, the Johnson counter 411 is described as a 2 (n + 1) -ary counter. The Johnson counter 411 outputs signals Q0 to Qn based on the input clock signal. The sub decoder 412 generates a set signal from the signals Q0 and Qn among the signals output from the Johnson counter 411, and outputs the set signal to the set input (S) of the RS flip-flop 414. The sub-decoder 412 generates a reset source signal from the signals Qn−1 and Qn among the signals output from the Johnson counter 411 and outputs the reset source signal to the D latch 413. The D latch 413 delays the reset source signal for a predetermined time, and then outputs it as a reset signal to the reset input (R) of the RS flip-flop 414. The RS flip-flop 414 outputs a weighting signal Qw according to the set signal and reset signal that are input.
[0047]
FIG. 4 is a timing chart showing the signals Q0 to Qn output from the Johnson counter 411 and the weighting signal Qw output from the weighting signal generation circuit 415. As shown in FIG. 4, 4 (n + 1) states can be obtained by signals Q0, Q1,..., Qn-1, Qn, Qw.
[0048]
In the control signal generation circuit 400 according to the first embodiment, 4 (n + 1) pieces of Johnson counters 411 of (n + 1) bits, which normally have only 2 (n + 1) states, are combined with the weighting signal generation circuit 415. Can be obtained. That is, it is possible to obtain more states while using a Johnson counter with a small number of flip-flops, so that the layout area of the control signal generation circuit can be made smaller than in the conventional case. Therefore, cost reduction can be realized by forming the control signal generation circuit on the same substrate as the driver circuit. In this case, by using the Johnson counter, the decoder circuit 420 can be simplified, and the hazard can be caused only by the combination of the signals Qn and Qw, so that the countermeasure against the hazard can be facilitated.
[0049]
[Embodiment 2]
Next, an embodiment in which an appropriate control signal is always generated and supplied to a signal line driver circuit by a sequencer including a control signal generation circuit will be described.
[0050]
FIG. 5 is a circuit configuration diagram showing a connection relationship between the signal line driver circuit 310 and the sequencer 500 according to the second embodiment.
[0051]
The signal line driver circuit 310 includes a video data input interface 311, a gradation selection circuit 312, a D / A converter 313, and an amplifier circuit 314. Among these, the video data input interface 311 is the same as the video data input interface 301 of FIG.
[0052]
The gradation selection circuit 312 performs gradation selection of the input video data, and outputs the signal potential of the video data obtained by the selection to the D / A converter 313 and a D / A converter state comparison circuit 503 described later. To do. The D / A converter 313 converts the gradation-selected digital video data into analog video data, outputs the analog video data to the amplifier circuit 314, and outputs the converted signal potential to a D / A converter state knowledge circuit 501 described later. And output to the amplifier state comparison circuit 504. The amplifier circuit 314 boosts the analog video data to a necessary potential and writes it to the signal line 11, and outputs the write potential to the amplifier state function circuit 502 described later.
[0053]
The sequencer 500 includes a D / A converter state knowledge circuit 501, an amplifier state knowledge circuit 502, a D / A converter state comparison circuit 503, an amplifier state comparison circuit 504, and a control signal generation circuit 505.
[0054]
The D / A converter state knowledge circuit 501 converts the signal potential output from the D / A converter 313 into a data format interpretable by the D / A converter state comparison circuit 503 and outputs the data format. The amplifier state relation circuit 502 converts the write potential output from the amplifier circuit 314 into a data format that can be interpreted by the amplifier state comparison circuit 504 and outputs the data format. If the signal potential output from the D / A converter 313 is received by the D / A converter state comparison circuit 503 as it is, the D / A converter state detection circuit 501 can be omitted. Similarly, when the write state output from the amplifier circuit 314 is received by the amplifier state comparison circuit 504 as it is, the amplifier state relation circuit 502 can be omitted.
[0055]
The D / A converter state comparison circuit 503 compares the signal potential output from the gradation selection circuit 312 with the signal potential output from the D / A converter state knowledge circuit 501 and compares the signal potential according to the comparison result. 1 state comparison signal is output to the control signal generation circuit 505. The amplifier state comparison circuit 504 compares the signal potential output from the D / A converter 313 and the write potential output from the amplifier state relation circuit 502, and outputs a second state comparison signal corresponding to the comparison result. Output to the control signal generation circuit 505.
[0056]
Similar to the control signal generation circuit 400 of the first embodiment, the control signal generation circuit 505 includes a counter circuit 410 and a decoder circuit 420 as shown in FIG. 3, and is based on an input clock signal supplied from an external circuit (not shown). Thus, a control signal for controlling the operation of the driver circuit 310 is generated. Further, the control signal generation circuit 505 determines the operation timing in the D / A converter 313 based on the first state comparison signal output from the D / A converter state comparison circuit 503, and according to the determination result. Based on the function of outputting the appropriate control signal to the D / A converter 313 and the second state comparison signal output from the amplifier state comparison circuit 504, the operation timing in the amplifier circuit 314 is determined. An internal control circuit (not shown) having a function of outputting an appropriate control signal corresponding to the above to the amplifier circuit 314 is added.
[0057]
Next, the operation of the sequencer 500 configured as described above will be described. In the signal line driver circuit 310, video data input from the outside passes through the video data input interface 311, the gradation selection circuit 312, the D / A converter 313, and the amplifier circuit 314, and then a predetermined potential is signaled at a predetermined operation timing. Written on line 11. During this time, in the D / A converter state knowledge circuit 501, the signal potential output from the D / A converter 313 is converted into a data format that can be interpreted by the D / A converter state comparison circuit 503, and the D / A converter state comparison circuit 503. Is output. In the D / A converter state comparison circuit 503, the signal potential output from the gradation selection circuit 312 is compared with the signal potential output from the D / A converter state relation circuit 501, and the first corresponding to the comparison result. The state comparison signal is output to the control signal generation circuit 505.
[0058]
Since the D / A converter 313 performs digital / analog conversion corresponding to the signal potential output from the gradation selection circuit 312, the characteristics of the TFTs constituting the D / A converter 313 are manufactured as estimated at the time of design. If so, the operation timing in the D / A converter 313 is appropriate. Therefore, in the D / A converter state comparison circuit 503, the signal potential before D / A conversion input from the gradation selection circuit 312 and the signal after D / A conversion input through the D / A converter state knowledge circuit 501 The potential will correspond correctly. That is, the signal potential after D / A conversion substantially matches the value set as the signal potential to be output from the D / A converter 313 at the time of design (uniquely determined from the signal potential before D / A conversion). become. In this case, the first state comparison signal output from the D / A converter state comparison circuit 503 does not correct the timing of the control signal output from the control signal generation circuit 505 to the D / A converter 313.
[0059]
On the other hand, when the characteristics of the TFT constituting the D / A converter 313 are not manufactured as estimated at the time of design, the operation timing in the D / A converter 313 is inappropriate. Therefore, the signal potential before D / A conversion input from the gradation selection circuit 312 does not correspond to the signal potential after D / A conversion input through the D / A converter state knowledge circuit 501. That is, the signal potential after D / A conversion does not match the value set as the signal potential to be output from the D / A converter 313 at the time of design. In this case, the first state comparison signal output from the D / A converter state comparison circuit 503 is a signal corresponding to the difference in signal potential before and after the D / A conversion, and this signal causes the control signal generation circuit 505 to output a signal. The timing of the control signal output to the D / A converter 313 is corrected.
[0060]
For example, when the signal potential after D / A conversion is larger than the value set as the signal potential to be output from the D / A converter 313 at the time of design, the control signal generation circuit 505 causes the D / A converter 313 to perform digital When the video data is converted to analog video data, the timing of the control signal is corrected and output so that the operation timing is changed so that the value of the converted signal potential becomes small. The operation timing to be changed is appropriately selected from a plurality of set values according to the comparison result in the D / A converter state comparison circuit 503.
[0061]
Similarly, in the amplifier state relation circuit 502, the write potential to the signal line 11 output from the amplifier circuit 314 is converted into a data format that can be interpreted by the amplifier state comparison circuit 504 and output to the amplifier state comparison circuit 504. . In the amplifier state comparison circuit 504, the signal potential before boosting output from the D / A converter 313 and the write potential output from the amplifier state related circuit 502 are compared, and a second state corresponding to the comparison result is obtained. The comparison signal is output to the control signal generation circuit 505.
[0062]
In the amplifier circuit 314, an operation of boosting analog video data and writing it to the signal line 11 is performed. Therefore, if the characteristics of the TFTs constituting the amplifier circuit 314 are manufactured as estimated at the time of design, the amplifier circuit 314 Therefore, the signal potential before boosting output from the D / A converter 313 and the actual write potential input through the amplifier state knowledge circuit 502 correctly correspond to each other. In other words, the actual write potential substantially coincides with the value (uniquely determined from the signal potential before boosting) set as the write potential to be output from the amplifier circuit 314 at the time of design. In this case, the second state comparison signal output from the amplifier state comparison circuit 504 does not correct the timing of the control signal output from the control signal generation circuit 505 to the amplifier circuit 314.
[0063]
On the other hand, when the characteristics of the TFTs constituting the amplifier circuit 314 are not manufactured as estimated at the time of design, the operation timing in the amplifier circuit 314 is inappropriate, and thus the output from the D / A converter 313 is performed. The signal potential before boosting does not correspond to the actual write potential input through the amplifier state knowledge circuit 502. That is, the boosted write potential does not match the value set as the write potential to be output from the amplifier circuit 314 at the time of design. In this case, the second state comparison signal output from the amplifier state comparison circuit 504 is a signal corresponding to the difference in signal potential before and after boosting, and is output from the control signal generation circuit 505 to the amplifier circuit 314 by this signal. The timing of the control signal is corrected.
[0064]
For example, when the actual write potential value is smaller than the value set as the write potential to be output from the amplifier circuit 314 at the time of design, the control signal generation circuit 505 boosts analog video data by the amplifier circuit 314. At this time, the timing of the control signal is corrected and output so that the operation timing is changed so that the boosted write potential value becomes large. The operation timing to be changed is appropriately set from a plurality of set values according to the comparison result in the amplifier state comparison circuit 504.
[0065]
According to the sequencer 500 of the second embodiment, the characteristics such as the threshold voltage of the TFTs constituting the D / A converter 313 and the amplifier circuit 314 of the signal line driver circuit 310 are not manufactured as estimated at the time of design. However, appropriate control signals can always be sent to these circuits. For this reason, even if the characteristics of the manufactured driver circuit are different from the estimated values at the time of design, there is no need to redesign the circuit and improve the manufacturing process as in the past, thereby improving productivity and reducing costs. Can do.
[0066]
When the counter circuit (not shown) constituting the control signal generating circuit 505 is configured by the same counter circuit 410 as the control signal generating circuit 400 of the first embodiment, in addition to the effects of the second embodiment, Further, the layout area of the control signal generation circuit 505 can be reduced. Therefore, cost reduction can be realized by forming the sequencer 500 including the control signal generation circuit 505 on the same substrate as the driver circuit.
[0067]
[Embodiment 3]
Here, an embodiment in which a layout area is reduced in a control signal generation circuit using a shift register as a counter will be described.
[0068]
First, a conventional example will be described. FIG. 6 is a circuit diagram of a conventional control signal generating circuit using a shift register as a counter, and FIG. 7 is a timing chart showing its input / output waveforms.
[0069]
A control signal generation circuit 600 shown in FIG. 6 includes a shift register 610 and an RS latch circuit 620. The shift register 610 is composed of 21 stages of latches 611 (reference numerals are representatively represented) that operate with a clock signal having a period a (hereinafter referred to as a clock), and an input signal i serving as a start pulse is a. It is sequentially shifted rightward at the clock timing. The RS latch circuit 620 is configured by a six-stage RS latch 621 (a symbol is assigned as a representative). The RS latch circuit 620 takes an output signal 612 taken out from the intermediate stage of the latch 611 as a set signal or a reset signal, Control signals c1, c2, c3, c4, c5 and c6 are output.
[0070]
In FIG. 6, the input signal i is input to the shift register 610, the output signal 612 is extracted from the intermediate stage, and is input as a set signal or a reset signal of the RS latch circuit 620, whereby a control signal as shown in FIG. c1, c2, c3, c4, c5, c6 can be made. C1 to c6 in FIG. 6 correspond to the control signals c1 to c6 in FIG. As described above, an arbitrary control signal can be generated by the output signal 612 taken out from the intermediate stage of the latch 611 connected in series and the RS latch circuit 620. At this time, the rising timing of the set signal and the rising timing of the reset signal input to each RS latch 621 of the RS latch circuit 620 are the same as the rising timing and falling timing of the control signal.
[0071]
In the conventional example shown in FIG. 6, since the shift register 610 is configured by connecting 21 stages of latches 611 in series, the required number of latches is 21. As described above, since the conventional control signal generating circuit has a large layout area, it is difficult to build it on the same substrate as the driver circuit. In particular, when a shift register is used as a counter as in this example, the same number of latches as the number of counts are required. Therefore, even if the layout area of one latch is small, the layout area is very large as a counter. There was a problem.
[0072]
FIG. 8 is a circuit configuration diagram of the control signal generating circuit according to this embodiment, and FIG. 9 is a timing chart showing its input / output waveforms.
[0073]
A control signal generation circuit 700 shown in FIG. 8 includes shift registers 710 to 750 and an RS latch 760. The shift register 710 arranged in the preceding stage is a seven-stage latch 711 (the reference numeral is representatively attached) that operates with a clock signal of a period b (hereinafter referred to as b clock) having a period three times as long as a clock. The input signal i serving as a start pulse is sequentially shifted rightward at the timing of b clock. On the other hand, the shift registers 720, 730, 740, and 750 arranged in the subsequent stage are configured by latches 721, 731 and 732, 741 and 742, and 751 that operate at the a clock, respectively. The shift registers 720 to 750 are supplied with an output signal taken from the middle stage of the shift register 710 and shift this signal by a necessary amount at the timing of a clock. The RS latch circuit 760 is configured by a six-stage RS latch 761 (the reference numeral is representatively attached) as in FIG. 6, and an output signal extracted from the middle stage of the shift register 710 or the shift register 720. , 730, 740, and 750, the output signal taken out from the intermediate stage is fetched as a set signal or a reset signal, and control signals c1, c2, c3, c4, c5, and c6 are output.
[0074]
Next, the operation of the control signal generation circuit 700 shown in FIG. 8 will be described. The shift register 710 shifts the input signal i input as a start pulse by b clocks, extracts an output signal from the intermediate stage, and outputs it to the subsequent shift registers 720, 730, 740, and 750. In the shift registers 720 to 750, the output signal extracted from the intermediate stage of the shift register 710 is shifted by a clock, and the output signal is extracted from the intermediate stage and output to the RS latch circuit 760. In the RS latch circuit 760, the output signal extracted from the shift registers 710 to 750 is input as a set signal or a reset signal, and in response to this, the control signals c1, c2, and c3 as shown in FIG. , C4, c5, c6. C1 to c6 in FIG. 8 correspond to the control signals c1 to c6 in FIG.
[0075]
In this way, by combining the shift registers 720 to 750 operating with the a clock with the shift register 710 operating with the b clock having a period three times that of the a clock, the output signal is input to the RS latch circuit 760. Any control signal can be made. In the circuit configuration of this embodiment, seven stages of latches operating with the b clock are connected in series and six latches operating with the a clock are connected, so the total number of latches is 13. As described above, in the control signal generation circuit 700 according to the third embodiment, although the same control signals c1 to c6 can be generated, the number of latches is reduced by 8 compared with the control signal generation circuit 600 illustrated in FIG. be able to.
[0076]
Here, the number of latches required when a circuit is configured by combining a shift register that operates with an a clock and a shift register that operates with a b clock having a cycle of n times (n ≧ 2) will be described.
[0077]
In this example, a shift register that operates with a first clock (for convenience, a clock is assumed to have a period a) and a second clock having a period that is n times that of the shift register (b clock for convenience, with a period of n × a) The case where the circuit is configured by combining the shift registers operating in (1) will be described.
[0078]
When the set signal when the target control signal is generated by the RS latch is delayed by j from the input signal i, the number of latches operating at the b clock is the quotient when j is divided by n, and the latch operating at the a clock. The number is the remainder when j is divided by n. Similarly, when the reset signal is delayed by k from the input signal i, the number of latches operating at the b clock is a quotient when k is divided by n, and the number of latches operating at the a clock is when k is divided by n. The remainder.
[0079]
In the control signal generation circuit 700 of the third embodiment, an arbitrary control signal is generated by combining shift registers that operate with two clocks having different periods. According to this, the number of latches can be reduced as compared with the conventional case where a shift register is configured by connecting a plurality of latches in series. For this reason, the layout area of the control signal generation circuit using a shift register as a counter can be made smaller than the conventional one. Therefore, cost reduction can be realized by forming the control signal generation circuit 700 on the same substrate as the driver circuit.
[0080]
Further, since a shift register is used as a counter, power consumption can be suppressed.
[0081]
In this embodiment, the cycle of the a clock and the b clock is set to 1: 3. However, the cycle of the b clock may be n times (n ≧ 2) of the a clock, and operates in a clock cycle other than this embodiment. Arbitrary control signals can also be created by combining shift registers.
[0082]
Furthermore, the control signal generation circuit 700 of the third embodiment may be used as the control signal generation circuit (505) included in the sequencer 500 of the second embodiment.
[0083]
[Embodiment 4]
Next, when a circuit is configured by combining shift registers operating with two clocks having different periods as in the third embodiment, the layout area can be reduced by further reducing the number of latches. Will be described.
[0084]
First, a control signal generation circuit having a circuit configured according to the same rules as in the third embodiment will be described.
[0085]
FIG. 10 is a circuit configuration diagram of a control signal generation circuit configured with the same rules as in the third embodiment, and FIG. 11 is a timing chart showing input / output waveforms thereof.
[0086]
10 includes a shift register 810, shift registers 815, 820, 825, 830, 835, 840, 845, 850, 855, and 860, and an RS latch circuit 870. The shift register 810 arranged in the preceding stage is a 13-stage latch 811 (the reference numeral is representatively attached) that operates with a clock signal of a period b (hereinafter referred to as b clock) having a period three times that of a clock. The input signal i serving as a start pulse is sequentially shifted rightward at the timing of b clock. The output signal extracted from the middle stage of the shift register 810 is output to the shift registers 815 to 860 at the subsequent stage.
[0087]
The shift registers 815 to 860 arranged in the subsequent stage include latches 816 and 817, 821 and 822, 826 and 827, 831, 836 and 837, 841, 846 and 847, 851 and 852, 856 and 857, which operate with a clock. 861 and 862, respectively. The shift registers 815 to 860 shift the output signal extracted from the intermediate stage of the shift register 810 by a necessary amount at the timing of a clock and send it out. The RS latch circuit 870 is composed of a five-stage RS latch 871 (reference numeral is representatively represented), takes the output signals from the shift registers 815 to 860 as set signals or reset signals, and controls the control signal c1. , C2, c3, c4, and c5.
[0088]
In this control signal generation circuit 800, the shift register 810 shifts the input signal i, which is a start pulse, by b clocks, extracts an output signal from the intermediate stage, and outputs it to the shift registers 815 to 860 at the subsequent stage. The shift registers 815 to 860 shift the output signal extracted from the intermediate stage of the shift register 810 by a clock and output the output signal to the RS latch circuit 870. In the RS latch circuit 870, the output signals taken out from the shift registers 815 to 860 are input as set signals or reset signals, and the control signals c1, c2, c3 as shown in FIG. , C4, c5. C1 to c5 in FIG. 10 correspond to the control signals c1 to c5 in FIG.
[0089]
Next, a case where a circuit is configured according to the rules of the fourth embodiment will be described. FIG. 12 is a circuit configuration diagram of a control signal generation circuit according to the fourth embodiment. The timing chart showing the input / output waveforms of this circuit is the same as FIG.
[0090]
A control signal generation circuit 900 shown in FIG. 12 includes a shift register 910, shift registers 920, 930, 940, and 950, an RS latch circuit 960, and an AND circuit 970.
[0091]
The shift register 910 arranged in the preceding stage is composed of 13 stages of latches 911 (reference numerals are representatively shown) that operate at b clocks, and an input signal i serving as a start pulse is sent at the timing of b clocks. Shifting sequentially to the right. Output signals taken out from the middle stage of the shift register 910 are respectively output to the shift registers 920 to 950 and the RS latch circuit 960 in the subsequent stage. The configuration of the shift register 910 is the same as that of the shift register 810 in FIG.
[0092]
The shift registers 920 to 950 arranged in the subsequent stage are configured by latches 921 and 922, 931 and 932, 941 and 942, and 951, respectively, which operate with an a clock. The shift registers 920 to 950 shift the output signal extracted from the intermediate stage of the shift register 910 by a necessary amount at the timing of a clock and send it out.
[0093]
Here, the configuration of the shift registers 920 to 950 will be described in comparison with the shift registers 815 to 860 shown in FIG.
[0094]
In the shift registers 920 to 950 of this embodiment, the combination of the shift register that supplies the set signal and the shift register that supplies the reset signal is the same as viewed from each RS latch 961 of the RS latch circuit 960 that is the output destination of the output signal. Is common. For example, in FIG. 10, the combination of the shift registers 815 and 820 is a combination of a shift register that provides a set signal and a shift register that provides a reset signal, as viewed from the RS latch 871 that outputs the control signal c1. The shift registers 845 and 850 and the shift registers 855 and 860 which are different combinations are shared, and only the combination of the shift registers 920 and 930 is made as shown in FIG. Similarly, in FIG. 10, the combination of the shift registers 825 and 830 is a combination of a shift register that provides a set signal and a shift register that provides a reset signal when viewed from the RS latch 871 that outputs the control signal c2. The shift registers 835 and 840 having such a combination are shared, and only the combination of the shift registers 940 and 950 is made as shown in FIG.
[0095]
Along with this, the output from the middle stage of the shift register 910 operating with the b clock is transferred to the corresponding shift registers 920 to 950. That is, the output signal taken out from the intermediate stage of the shift register 910 is derived from the shift amount in a clock from the output of the shift register 910 to the set side input of the RS latch 961 of the RS latch circuit 960 and the output of the shift register 910. Each of them is passed to a shift register corresponding to a combination with a shift amount in a clock until the reset side input of the RS latch 961 of the RS latch circuit 960. For example, in the shift register 910 of FIG. 12, the outputs of the latches 911 at the 1st, 8th and 11th stages of the b clock are passed to the shift register 920, and the 2nd, 10th and 13th stages of the b clock. The output of each latch 911 at the stage is passed to the shift register 930. Similarly, the outputs of the latches 911 at the 3rd and 5th stages of the b clock are passed to the shift register 940, and the outputs of the latches 911 at the 4th and 7th stages of the b clock are sent to the shift register 950. Passed. On the other hand, the output from the intermediate stage of the shift register 910 is directly passed to the RS latch circuit 960 without passing through the shift registers 920 to 950.
[0096]
The RS latch circuit 960 is configured by a seven-stage RS latch 961 (a symbol is given as a representative), two of which output signals from the shift registers 920 to 950 are set signals or reset signals. As for the remaining five, the output signal taken out from the middle stage of the shift register 910 is taken in as a set signal or a reset signal.
[0097]
The AND circuit 970 is composed of a 5-stage AND gate 971 (the reference numeral is representatively attached). Each AND gate 971 outputs from the RS latch that uses the output signal from the shift registers 920 to 950 as a set signal or reset signal, and outputs from the RS latch that uses the output signal from the shift register 910 as a set signal or reset signal. , And the control signals c1, c2, c3, c4, and c5 are output by taking the logical product of the two inputs.
[0098]
In this control signal generation circuit 900, the shift register 910 shifts the input signal i, which is a start pulse, by b clocks, extracts an output signal from the middle stage thereof, and outputs it to the shift registers 920 to 950 at the subsequent stage. The shift registers 920 to 950 shift the output signal extracted from the intermediate stage of the shift register 910 by a clock, extract the output signal, and output it to the RS latch circuit 960. In the RS latch circuit 960, the output signal extracted from the shift registers 920 to 950 and the output signal extracted from the middle stage of the shift register 910 are input as a set signal or a reset signal, respectively. The output signal is taken out when the state of the latch 971 changes. This output signal is further input to an AND circuit 970, and the logical product of the inputs is obtained by each AND gate 971, thereby producing control signals c1, c2, c3, c4, and c5 as shown in FIG. C1 to c5 in FIG. 12 correspond to the control signals c1 to c5 in FIG.
[0099]
In the circuit configuration of this embodiment, 13 stages of latches 911 that operate with the b clock are connected in series, and seven latches 921 to 951 that operate with the a clock are connected, so the total number of latches is 20. . Thus, in the control signal generation circuit 900 of the fourth embodiment, the number of latches is reduced by 11 compared to the control signal generation circuit 800 shown in FIG. be able to.
[0100]
The control signal generation circuit 900 according to the fourth embodiment combines a shift register that operates with two clocks having different periods and uses a common shift register for the RS latch in a circuit configuration that generates an arbitrary control signal. It is what you do. According to this, since the number of latches can be further reduced as compared with the case where the circuit is configured according to the rule of the third embodiment, the layout area of the control signal generation circuit can be further reduced. As described above, the layout area of the control signal generation circuit using the shift register as the counter can be further reduced as compared with the conventional one. Therefore, the cost can be reduced by forming the control signal generation circuit 900 on the same substrate as the driver circuit. Can be realized.
[0101]
Note that the RS latch circuit 960 of the fourth embodiment has two more RS latches than the RS latch circuit 870 of the third embodiment, and is connected to an AND circuit 970 configured with five AND gates 971. However, since the increase in these elements is much smaller than the decrease in the number of latches, the layout area as a whole can be further reduced.
[0102]
Also in this embodiment, since a shift register is used as a counter, power consumption can be suppressed.
[0103]
In this embodiment, the example in which the period of the a clock and the b clock is 1: 3 is shown. However, the period of the b clock may be n times (n ≧ 2) of the a clock. Arbitrary control signals can also be created by combining shift registers that operate at a clock cycle of.
[0104]
Furthermore, the control signal generation circuit 800 of the fourth embodiment may be used as the control signal generation circuit (505) included in the sequencer 500 of the second embodiment.
[0105]
[Embodiment 5]
Next, an embodiment will be described in which a control signal generation timing can be changed by a simple operation in a control signal generation circuit using a shift register as a counter.
[0106]
FIG. 14 is a circuit configuration diagram showing a first connection form of the control signal generating circuit according to the fifth embodiment, and FIG. 15 is a timing chart showing its input / output waveforms.
[0107]
A control signal generation circuit 1000 shown in FIG. 14 includes shift registers 1010 and 1020 and an RS latch circuit 1040. Among these, the shift register 1010 arranged in the previous stage is composed of seven stages of latches 1011... 1016, 1017 that operate with a clock signal with a period b that is three times as long as a clock (hereinafter referred to as b clock). Thus, the input signal i1 serving as a start pulse is sequentially shifted rightward at the timing of b clock. The output signal extracted from the middle stage of the shift register 1010 is output to the middle stage of the subsequent shift register 1020. Although the output signals from the latches 1016 and 1017 are not used in FIG. 14, the reason why the latches 1016 and 1017 are necessary will be described later.
[0108]
On the other hand, the shift register 1020 arranged in the subsequent stage is composed of 18-stage latches 1021,. The shift register 1020 receives an output signal and an input signal i2 that are extracted from the middle stage of the shift register 1010. In the latch to which the output signal from the shift register 1010 is input, the input signal i2 is shifted by a necessary amount at the timing of a clock and sent out. Note that the input signal i2 may not exist depending on the generation timing of the control signal output from the RS latch circuit 1040. In FIG. 14, the latches 1032 to 1038 do not use output signals, but the reason why the latches 1032 to 1038 are necessary will be described later.
[0109]
The RS latch circuit 1040 includes three stages of RS latches 1041, 1042, and 1043, and an output signal extracted from a middle stage of the shift register 1020 or a middle part of the shift register 1010 (not shown in FIG. 14). An output signal from the stage is taken in as a set signal or a reset signal, and control signals c1, c2, and c3 are output.
[0110]
Next, the operation of the control signal generation circuit 1000 shown in FIG. 14 will be described. The shift register 1010 shifts the input signal i1 input as a start pulse by b clocks, extracts an output signal from the intermediate stage, and outputs it to the shift register 1020 at the subsequent stage. The shift register 1020 shifts the output signal extracted from the intermediate stage of the shift register 1010 by a clock, extracts the output signal from the intermediate stage, and outputs it to the RS latch circuit 1040. The output signal taken out from the shift registers 1010 and 1020 is input to the RS latch circuit 1040 as a set signal or a reset signal. In response to this, the RS latches 1041 to 1043 control the generation timing as shown in FIG. c1, c2, c3 can be made. Note that c1, c2, and c3 in FIG. 14 correspond to the control signals c1, c2, and c3 in FIG.
[0111]
Next, in the control signal generation circuit 1000 shown in FIG. 14, a case will be described in which it is necessary to change the generation timing of the control signal due to a change in the frame frequency or application to a product with different specifications.
[0112]
FIG. 16 is a circuit configuration diagram showing a second connection form of the control signal generating circuit according to the fifth embodiment, and FIG. 17 is a timing chart showing its input / output waveforms.
[0113]
In the control signal generation circuit 1100 shown in FIG. 16, the basic configuration of the shift registers 1110 and 1120 is the same as that of the shift registers 1010 and 1020 shown in FIG. 14, and the same parts are denoted by the same reference numerals. 14 differs from FIG. 14 in that the connection between the output terminal of the shift register 1110 and the input terminal of the shift register 1120, the connection between the output terminal of the shift register 1120 and the input terminal of the RS latch circuit 1140, and the latch that constitutes the shift register 1120. Only the positive / negative logic of the b clock input to the latch 1011 and the positive / negative logic of the a clock input to the latch 1021 are connected to each other. Here, the positive / negative logic of the b clock is the phase of the b clock input to the shift register 1011, and changing the positive / negative logic of the b clock is by changing the phase of the b clock input to the shift register 1011. is there. Similarly, the positive / negative logic of the a clock is the phase of the a clock input to the shift register 1021, and changing the positive / negative logic of the a clock is by changing the phase of the a clock input to the shift register 1021. is there. These three types of connections and the positive / negative logic of the b clock and the positive / negative logic of the a clock are connected as shown in FIG. 16, thereby generating control signals c1, c2, and c3 of the generation timing as shown in FIG. be able to. Note that c1, c2, and c3 in FIG. 17 correspond to the control signals c1, c2, and c3 in FIG.
[0114]
This control signal generation circuit 1100 uses latches 1016, 1017 and 1032, 1033, 1034 which are not used in the control signal generation circuit 1000 of FIG. In this way, by arranging the number of latches considered necessary in advance within the range allowed by the layout and appropriately setting the connection form according to the purpose of use, the generation timing of the control signal can be easily changed. it can. Further, the above three types of connection forms and the positive / negative logic of the b clock and the positive / negative logic of the a clock can be changed by modifying the electrode pattern formed on the first layer or the second layer on the substrate (not shown). . Therefore, since the mask correction in the manufacturing process only needs to be performed on the first layer or the second layer, the control signal generation timing can be easily changed.
[0115]
In the above example, with respect to the shift register 1120, a maximum of 18 latches may be prepared. This is because the number of RS latches is three, so six output signals are required from the shift register 1120, and for one signal, a maximum of three stages of latches can be shifted at a clock. is there.
[0116]
Here, a combination of a first shift register that operates with a clock having a cycle a, a second shift register that operates with b clock having a cycle of n × a, and an RS latch circuit that generates m types of control signals The number of RS latches will be described. Since the number of RS latches is m, the first shift register to be output to the RS latch needs 2 × m output signals, and a clock is output for one output signal. Since the maximum shift of n stages is required for the shift in the second shift register, the maximum number of latches of the second shift register is 2 × m × n stages.
[0117]
In the control signal generation circuit 1000 (and 1100) according to the fifth embodiment, the shift registers 1010 and 1110 (corresponding to the first shift register) and the shift registers 1020 and 1120 (corresponding to the second shift register) are necessary maximum. Since it is composed of a number of latches, all the connection modes can be set without arranging useless latches. Therefore, by making this control signal generation circuit 1000 (and 1100) on the same substrate as the driver circuit, it is possible to change the generation timing of the control signal at a low cost and in a short time.
[0118]
Also in this embodiment, since a shift register is used as a counter, power consumption can be suppressed.
[0119]
In this embodiment, the period of the a clock and the b clock is set to 1: 3. However, the period of the b clock may be n times (n ≧ 2) of the a clock, and the operation is performed with a clock period other than that of this embodiment. Arbitrary control signals can also be created by combining with a shift register. Also in this case, the connection form can be changed by correcting the electrode pattern formed in the first layer or the second layer on the substrate (not shown).
[0120]
Furthermore, the control signal generation circuits 1000 and 1100 of the fifth embodiment may be used as the control signal generation circuit (505) included in the sequencer 500 of the second embodiment.
[0121]
The embodiment in which the present invention is applied to a liquid crystal panel has been described above, but the present invention can also be applied to a display panel using organic EL as a display layer, for example.
[0122]
【Effect of the invention】
As described above, according to the present invention, the layout area of the control signal generation circuit can be made smaller than before, so that the cost reduction can be achieved by forming the control signal generation circuit on the same substrate as the driver circuit. Can be realized.
[0123]
Furthermore, according to the present invention, even when the characteristics of the driver circuit are not manufactured as estimated at the time of design, the driver circuit can be operated correctly, so that it is necessary to redesign the circuit and improve the manufacturing process as before. There is no need to improve productivity and reduce costs.
[0124]
Furthermore, according to the present invention, the control signal generation timing can be changed simply by correcting the electrode pattern formed on the first layer or the second layer on the substrate. The signal generation timing can be changed at low cost and in a short time.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of a counter circuit shown in FIG.
2 is a circuit configuration diagram showing a connection relationship between a signal line driver circuit and a control signal generation circuit in Embodiment 1. FIG.
FIG. 3 is a circuit configuration diagram of a control signal generation circuit shown in FIG. 2;
FIG. 4 is a timing chart showing a signal output from a Johnson counter and a weighting signal output from a weighting signal generation circuit.
FIG. 5 is a circuit configuration diagram showing a connection relationship between a signal line driver circuit and a sequencer in the second embodiment.
FIG. 6 is a circuit configuration diagram showing a conventional example of a control signal generation circuit using a shift register as a counter.
7 is a timing chart showing input / output waveforms in FIG. 6;
FIG. 8 is a circuit configuration diagram of a control signal generation circuit according to a third embodiment.
FIG. 9 is a timing chart showing input / output waveforms of FIG. 8;
FIG. 10 is a circuit configuration diagram of a control signal generation circuit in which a circuit is configured according to the same rule as in the third embodiment.
11 is a timing chart showing the input / output waveforms of FIG.
12 is a circuit configuration diagram of a control signal generation circuit in Embodiment 4. FIG.
FIG. 13 is a circuit configuration diagram of a liquid crystal panel according to the embodiment.
14 is a circuit configuration diagram showing a first connection form of a control signal generating circuit according to Embodiment 5. FIG.
FIG. 15 is a timing chart showing input / output waveforms of FIG. 14;
FIG. 16 is a circuit configuration diagram showing a second connection configuration of the control signal generation circuit according to the fifth embodiment;
FIG. 17 is a timing chart showing the input / output waveforms of FIG. 16;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Liquid crystal panel, 100 ... Pixel part, 200 ... Scan line driver circuit, 300 ... Signal line driver circuit, 400, 600, 700, 800, 900, 1000 ... Control signal generation circuit, 410 ... Counter circuit, 411 ... Johnson counter 412 ... sub-decoder, 413 ... D latch, 414 ... RS flip-flop, 415 ... weighting signal generation circuit, 500 ... sequencer, 501 ... D / A converter state knowledge circuit, 502 ... amplifier state knowledge circuit, 503 ... D / A Converter state comparison circuit, 504... Amplifier state comparison circuit, 610, 710, 810, 910, 1010, 1020, 1110, 1120 ... Shift register, 620, 760, 870, 960, 1040, 1140 ... RS latch circuit, 970 ... AND circuit

Claims (9)

At least, a Cie Kensa to output a control signal for controlling the operation of the driver circuit having the video data input interface, the gradation selection circuit, a digital / analog converter and an amplifier circuit,
A first output signal potential from the gradation selection circuit is compared with a second output signal potential from the digital / analog converter, and a first state comparison signal corresponding to the comparison result is output. A comparison circuit of
The second output signal potential from the digital / analog converter is compared with the third output signal potential from the amplifier circuit, and a second state comparison signal corresponding to the comparison result is output. A comparison circuit ;
If the previous SL first state comparison signal indicates that said second output signal voltage and the first output signal voltage do not correspond, first to modify the operation timing of the digital / analog converter It outputs a control signal to the digital / analog converter, before SL when the second condition comparison signal indicates that said third output signal voltage and the second output signal potential is not compatible, the amplifier times A control signal generating circuit for outputting a second control signal for correcting the operation timing of the path to the amplifier circuit ;
Sequencer and having a. A first conversion circuit that converts the second output signal potential into a data format that can be interpreted by the first comparison circuit, and outputs the data to the first comparison circuit;
A second conversion circuit that converts the third output signal potential into a data format that can be interpreted by the second comparison circuit and outputs the converted data to the second comparison circuit;
The sequencer according to claim 1, comprising: The control signal generation circuit operates with at least a first shift register that operates with a first clock signal and a second clock signal that has a period n (n ≧ 2) times the first clock signal. A counter circuit comprising a second shift register and an RS latch circuit comprising a plurality of RS latches;
A start pulse is shifted by the first and second shift registers by the first and second clock signals, and is extracted as an output signal from a predetermined stage of the first and second shift registers, and the output signal is 2. The sequencer according to claim 1, wherein the sequencer is inputted to an RS latch circuit, and an output from the RS latch circuit is taken out as a control signal. The control signal generation circuit operates with at least a first shift register that operates with a first clock signal and a second clock signal that has a period n (n ≧ 2) times the first clock signal. A counter circuit including a second shift register, an RS latch circuit including a plurality of RS latches, and an AND circuit including a plurality of AND gates;
The second shift register is arranged at the front stage and the first shift register is arranged at the rear stage, and the first shift register gives a set signal as seen from the RS latch of the RS latch circuit of the output destination. The same combination of the shift register and the shift register that gives the reset signal is shared,
The start pulse is shifted by the second shift register by the second clock signal, and an output signal taken from a predetermined stage of the second shift register is used as an input signal of the first shift register, and the first shift register The output signals respectively taken from the predetermined stages of the first and second shift registers are input to the respective RS latches of the RS latch circuit as set signals or reset signals, and the outputs from the respective RS latches are used as the output signals to perform the AND operation. 2. The sequencer according to claim 1, wherein the sequencer is inputted to a circuit and a logical product of the output signals is taken out as a control signal. The control signal generation circuit has at least a first shift register composed of a first latch group that operates with a first clock signal and a cycle n (n ≧ 2) times the first clock signal. A counter circuit composed of a second shift register composed of a second latch group operating with a second clock signal, and a control signal according to an output signal output from a predetermined stage of the first and second shift registers. An RS latch circuit comprising a plurality of generated RS latches,
The generation timing of the control signal in the RS latch circuit is set according to the connection form between the first shift register and the second shift register and between the first shift register and the RS latch circuit. The sequencer according to claim 1. In a flat display device in which a pixel portion and a driver circuit are integrally formed on a substrate,
6. A flat display device, wherein the sequencer according to claim 1 is integrally formed on the substrate as a circuit for generating a control signal for controlling the operation of the driver circuit.   A plurality of pixel electrodes, a switch element connected to each of these pixel electrodes via an electrode wiring, a driver circuit that drives the switch element and writes video data to the pixel electrode, and any one of claims 1 to 5 A first electrode substrate on which the described sequencer is integrally formed, a second electrode substrate on which counter electrodes opposed to the plurality of pixel electrodes are formed, and a display layer held between the two electrode substrates. The flat display device according to claim 6.   The flat display device according to claim 7, wherein the display layer is a liquid crystal layer.   The flat display device according to claim 7, wherein the display layer is an organic EL.

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