JP4896479B2 - Data erasing method of semiconductor memory device - Google Patents

Description

The present invention, together can write and rewrite the data using an external writing rewriting device through external write terminal, it relates to a data erase method for a semiconductor memory device capable of performing write and rewrite data by internal write rewriting circuit.

  Microcomputers are used to control various devices such as various electronic devices, watches and other measuring devices, communication devices, office devices, industrial devices, and entertainment devices. In the microcomputer, a CPU (Central Processing Unit) corresponding to a control circuit and a ROM (Read Only Memory) and a RAM (Random Access Memory) are generally used as semiconductor memories for storing operation programs and data. However, a nonvolatile memory such as an EEPROM that can electrically rewrite data and can retain data even in a non-powered state is also provided.

FIG. 8 shows a configuration example of a conventional general microcomputer.
The microcomputer 5 includes a control circuit (CPU) 50, a ROM 51 and a RAM 53 that are semiconductor memories, and an EEPROM 52 that is a nonvolatile memory, an A / D converter 54, and an I / O circuit 55. For example, an external sensor 6 is connected to the A / D converter 54, and the input unit 7 and the output unit 8 are connected to the I / O circuit 55.
The ROM 51 has a program area 51a and a non-rewritable data area 51b. In the manufacturing stage of the microcomputer 5, a control program used by the control circuit 50 is written in the program area 51a, and fixed data such as sensor correction data is stored. It is written in the non-rewritable data area 51b.

  When the microcomputer 5 is mounted on a controlled device and used, the control circuit 50 operates in accordance with a control program stored in the program area 51a of the ROM 51. For example, detection by the sensor 6 provided outside. The signal is converted into digital data by the A / D converter 54, stored in the rewritable data area 52a of the EEPROM 52, and the data is corrected and calculated using the correction data stored in the non-rewritable data area 51b of the ROM 51. Is performed using the working area of the RAM 53, and the result is output to the external output unit 8 through the I / O circuit 55.

In this example, the control program and fixed data stored in the ROM 51 are read-only data and cannot be rewritten after manufacture.
In addition, these semiconductor memories (especially nonvolatile memories) need to be tested for their operating state during the manufacturing process, and data write and erase tests are performed by applying a write voltage and an erase voltage from an external terminal. (For example, refer to Patent Documents 1 and 2.)

JP 62-128100 A (page 2-3, FIG. 1) Japanese Patent Laid-Open No. 11-283400 (page 3-4, FIG. 1)

At the time of the testing, the control program and fixed data can be written, but the retention of the data is not guaranteed, and the written data may be lost by processing in a later process.
In order to prevent the disappearance, if testing is performed with a sufficiently high write voltage, it becomes necessary to mount a high-breakdown-voltage transistor, and it becomes impossible to cope with miniaturization of the constituent elements. Further, as the miniaturization of the constituent elements advances, it becomes difficult to raise the boosted voltage in the booster circuit to the expected write voltage even when data is rewritten by the internal write / rewrite circuit.

Therefore, if the memory that writes data during testing and the memory that can write data during actual use are configured with different devices according to the respective specifications, the memory device that writes data during testing becomes a one-time ROM and is the same Since it is necessary to mount different devices in the chip, there arises a problem that the manufacturing process becomes long.
In addition, since the data cannot be rewritten with a one-time ROM, there is also a problem that it is impossible to respond to a data rewriting request often generated by testing at the early stage of product development.

  Although a mask ROM can be used as a memory for storing a control program, a process for forming the mask ROM is required, which increases the number of manufacturing steps. Moreover, there is a problem that the program required at the time of product development cannot be rewritten suddenly and the development period becomes long.

The present invention has been made to solve the above-described various problems in semiconductor memory devices.
Therefore, an object of the present invention is to make it possible to easily rewrite data and programs written in a memory device by testing at the development stage of a semiconductor memory device, thereby shortening the development period.

The present invention relates to an external write terminal, an internal write rewrite circuit, a first nonvolatile memory device in which data is written using an external write rewrite device through the external write terminal and holds the data, and the internal write rewrite and a second nonvolatile memory device is write and rewrite data by the circuit takes place, written in a semiconductor memory device in the first nonvolatile memory device and the second nonvolatile memory device are the same device structure This is a data erasing method for erasing data, and has the characteristics described later .

  The first nonvolatile memory device and the second nonvolatile memory device may be configured by different memory areas in a single nonvolatile memory device, and the boundary between the different memory areas may be variable.

  The memory cell of each non-volatile memory device may be a MONOS type memory.

A system IC can also be configured by the external write terminal, the internal write rewrite circuit, and the first and second nonvolatile memory devices. In that case, the active element of the internal rewrite circuit is a switching element having a MOS transistor structure, and the memory cells of the first and second nonvolatile memory devices are a nonvolatile memory element having a memory film having a multilayer structure. It is preferable that the address transistor has an MOS transistor structure, and the address transistor has the same structure as the switching element that constitutes the active element of the internal rewrite circuit.

  It is desirable that the external write terminal cannot be used after data is written to the first nonvolatile memory device using an external write rewrite device through the external write terminal.

The formed integrated on one semiconductor memory device and a semiconductor on one chip the control circuit, it is also possible to configure the system IC.

Data erase method of a semiconductor memory device according to the invention is a method for erasing data written in the semiconductor memory device described above, in the first nonvolatile memory device using the external write rewriting device through said external write terminal The write voltage value when writing data is Vwo, the erase voltage value when erasing data is Veo, the erase time is Teo,
Assuming that the write voltage value when writing data to the second nonvolatile memory device by the internal write rewrite circuit is Vwi, the erase voltage value when erasing data is Vei, and the erase time is Tei,
Veo> Vei and Teo <Tei
Meets the requirements of
Vwo> Veo and Vwi = Vei
It satisfies the following conditions.

According to the semiconductor memory device data erasing method of the present invention, it is possible to easily rewrite data and programs written in the memory device by testing at the development stage of the semiconductor memory device, and to shorten the development period. it can.

Hereinafter, the best mode for carrying out the present invention will be specifically described with reference to the drawings.
[ First Example of Semiconductor Memory Device ]
FIG. 1 is a block diagram showing a configuration of a first example of a system IC (semiconductor integrated circuit) including a semiconductor memory device used in the present invention.
A system IC 1 shown in FIG. 1 includes an external write terminal 15, an internal write rewrite circuit 17, a semiconductor memory device including a first nonvolatile memory device 11 and a second nonvolatile memory device 21, and a control circuit using a CPU. 10 and a peripheral circuit 18 controlled thereby.

The system IC 1 further includes address buffers 12 and 22, row decoders 13 and 23, and column decoders 14 and 24, respectively, for the first nonvolatile memory device 11 and the second nonvolatile memory device 21. Yes.
The first nonvolatile memory device 11 is a memory cell array in which data is written using the external write / rewrite device 3 through the external write terminal 15 and holds the data. The second nonvolatile memory device 21 is an internal write This is a memory cell array in which data is written and rewritten by the rewrite circuit 17. The first nonvolatile memory device 11 and the second nonvolatile memory device 21 have the same device structure.

  The address buffers 12 and 22 are controlled by the control circuit 10. Address data when data is written using the external write / rewrite device 3 and address data when data is written and rewritten by the internal write / rewrite circuit 17. Hold. The row decoder 13 and the column decoder 14 specify the row and column addresses of the first nonvolatile memory device 11 according to the address data, and the row decoder 23 and the column decoder 24 specify the second nonvolatile memory. Specifies the row and column addresses of device 21.

The memory cells of the first and second nonvolatile memory devices 11 and 21 are preferably MONOS type memories. The same applies to the nonvolatile memory device 30 in the second embodiment to be described later.
The MONOS type memory is a nonvolatile memory having a structure of metal, oxide film, oxide film, nitride film, oxide film, and semiconductor.
The structure of this MONOS type memory is shown in a schematic sectional view in FIG. In the MONOS type memory 40, a tunnel oxide film 42 made of a silicon oxide film, a nitride film 43 made of a silicon nitride film for accumulating charges, and a top oxide film 44 made of a silicon oxide film are sequentially formed on a silicon substrate 41 which is a semiconductor substrate. An ONO film 45 is formed by stacking, and a memory gate electrode 46 made of polysilicon or the like is formed on the top oxide film 44.

Then, a source (S) 47 and a drain (D) 48 are provided on the outer side from the portion in contact with both ends of the tunnel oxide film 42 on the upper surface of the silicon substrate 41.
The MONOS type memory 40 stores charges by accumulating electric charges in traps in the nitride film 43. The nitride film 43 that accumulates the charge is an insulating film, and is further sandwiched between the tunnel oxide film 42 and the top oxide film 44, which are insulating films. Therefore, even if a defect occurs in the thin tunnel oxide film 42, the charge is It is a robust and highly reliable memory cell that hardly leaks.
The nonvolatile memory device is a memory cell array formed by arranging a large number of memory cells of such a MONOS type memory on a common silicon substrate.

Data writing and erasing to the MONOS type memory having such a configuration are performed by changing voltages applied to the memory gate electrode 46, the source 47, the drain 48, and the silicon substrate 41.
For example, at the time of writing, by applying the write voltage Vw to the memory gate electrode 46 and setting the source 47, the drain 48 and the silicon substrate 41 to the ground potential, the charges near the surface of the silicon substrate 41 pass through the tunnel oxide film 42. , Accumulated in the nitride film 43.
At the time of erasure, the memory gate electrode 46 is set to the ground potential, and the erase voltage Ve is applied to the source 47, the drain 48 and the silicon substrate 41, whereby the charge accumulated in the nitride film 43 passes through the tunnel oxide film 42. The silicon substrate 41 is pulled out.

By the way, a system IC can also be constituted by the external write terminal 15, the internal write rewrite circuit 17, and the first and second nonvolatile memory devices 11 and 21. The active element of the internal rewrite circuit 17 is a switching element having a MOS transistor structure.
The memory cells of the first and second nonvolatile memory devices 11 and 21 are nonvolatile memory elements whose memory films have a multilayer structure (for example, a MONOS memory shown in FIG. 3), and addresses having a MOS transistor structure. The address transistor has the same structure as the switching element that constitutes the active element of the internal rewrite circuit 17.
This is because, when the MONOS type memory shown in FIG. 3 is used, the write voltage can be set to a low voltage (for example, 10 V or less), so that the MOS type transistor constituting the system has a special high breakdown voltage structure. The effect that there is no necessity to do is acquired. Therefore, the internal write circuit 17 can use a booster circuit using a normal MOS transistor.

FIG. 4 is a schematic cross-sectional view showing a structure example of the memory cell of the nonvolatile memory device in this case. This is a memory cell compatible with a multi-function IC. Here, the parts corresponding to those in FIG.
In this memory cell, an element area partitioned by a field oxide film 63 is provided on a p-well of a silicon substrate 41, and is composed of an ONO film 45 and a memory gate electrode 46, which are memory films having a multilayer film structure. A MONOS type memory 40 and an address transistor 60 having a MOS type transistor structure composed of a gate oxide film 61 and an address gate electrode 62 are formed. The MONOS type memory 40 is a nonvolatile memory element having a memory multilayer structure.

A drain 64 of the address transistor 60, a common electrode portion 65 of the source of the address transistor 60 and the drain of the MONOS type memory 40, and a source 66 of the MONOS type memory 40 are provided on the silicon substrate 41.
The active element of the internal rewrite circuit 17 is also composed of a switching element having a MOS transistor structure similar to the address transistor 60.

  FIG. 5 is a schematic cross-sectional view showing another structural example of the memory cell of the nonvolatile memory device. This is a memory cell compatible with a highly integrated IC. Again, parts corresponding to those in FIG. 3 are denoted by the same reference numerals, and an element area partitioned by a field oxide film 63 is provided on the p-well of the silicon substrate 41. The memory film having the multilayer film structure described above is provided there. A MONOS type memory 40 composed of an ONO film 45 and a memory gate electrode 46 and an address transistor 60 having a MOS type transistor structure composed of a gate oxide film 61 and an address gate electrode 62 are formed. However, the MONOS type memory 40 and the address transistor 60 are arranged in close proximity to each other, and a part of the memory gate electrode 46 is overlapped on the address gate electrode 62 of the address transistor 60 via an insulating film 67. .

A drain 68 of the address transistor 60 and a source 69 of the MONOS type memory 40 are provided on the silicon substrate 41.
When a large number of such memory cells are arranged on a common silicon substrate to form a memory cell array, high density can be achieved.

  In the manufacturing process of the system IC including the semiconductor memory device as described above, data such as a control program and fixed data is transferred to the first nonvolatile memory device 11 through the external write terminal 15 and using the external write / rewrite device 3. Is written, the external write terminal 15 is disabled. Thereby, the data written in the first nonvolatile memory device 11 can be reliably held and used in actual operation.

As a method for preventing the external write terminal 15 from being used, there are the following means.
(1) After data is written through the external write terminal 15, the external write terminal 15 is masked in a bump forming process, which is one of the mounting processes on the substrate, so that bumps are not formed.
(2) Wiring is formed of aluminum or polycrystalline silicon so that the external write terminal 15 can be laser trimmed, and the portion is cut by laser after writing.
(3) When the IC is mounted on the substrate, the wiring should be such that no contact is provided on the substrate side.

In this example, the semiconductor memory device including the first and second nonvolatile memory devices 11 and 21 and the internal write / rewrite circuit 17 and the control circuit 10 for controlling the semiconductor memory device are all shown in FIG. 1 on a one-chip semiconductor. A one-chip system IC is formed by integrating the two.

[ Second Example of Semiconductor Memory Device ]
FIG. 2 is a block diagram showing a configuration of a second example of a system IC (semiconductor integrated circuit) including a semiconductor memory device used in the present invention. In this figure, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.
In this second example , instead of the first nonvolatile memory device 11 and the second nonvolatile memory device 21 in the first example shown in FIG. 1, the nonvolatile memory device 30 of a single memory cell array is used. The function is given to different memory areas.

The memory area of the nonvolatile memory device 30 is divided into a program area 31 for storing a control program, a non-rewritable data area 32 for storing fixed data, and a rewritable data area 33 for writing and rewriting arbitrary data. It has been. The program area 31 and the non-rewritable data area 32 correspond to the first nonvolatile memory device 11, and the rewritable data area 33 corresponds to the second nonvolatile memory device 21.
For address control of the nonvolatile memory device 30, an address buffer 35, a row decoder 36, and a column decoder / multiplexer 37 are provided, and the column decoder / multiplexer 37 is also connected to a read circuit 38.

Data read from the nonvolatile memory device 30 by the read circuit 38 is output to the external output unit 4 through the output buffer 39.
In this embodiment, after the manufacture of the system IC, the control program and the sensor correction are made respectively in the program area 31 and the non-rewritable data area 32 of the nonvolatile memory device 30 by using the external write / rewrite device 3 through the external write terminal 15. Write fixed data such as data.

In the control program, a row address, a column address, and a read control signal for designating a memory cell position necessary for data reading by the read circuit 38 are included. For the rewritable data area 33, a write control signal is included in the control program.
As a result, individual addresses are assigned to the memory cells of the nonvolatile memory device 30. By storing the control program, the program area 31, the non-rewritable data area 32, and the rewritable data area 33 are changed. Can be divided freely. In other words, the boundary between different memory areas becomes variable, and the application is expanded with one system IC.

Various memory cell structures of the nonvolatile memory device described in the first example , structures of address transistors and switching elements of the internal write / rewrite circuit, and the like can also be applied to the second embodiment.
In order to satisfy the low voltage specification of the internal rewrite circuit 17, a MONOS type memory is optimal as the memory cell of the nonvolatile memory device. However, if the restrictions of the design rule are not considered, a general floating gate can be used. A type memory, a ferroelectric memory, or the like can also be used.

[Data writing method and data erasing method]
Next, a data writing method and a data erasing method for each of the semiconductor memory devices described above will be described.
When writing data to the semiconductor memory device described above, the data is written to the areas 31 and 32 of the first nonvolatile memory device 11 or the nonvolatile memory device 30 using the external write / rewrite device 3 through the external write terminal 15. The write voltage value is Vwo, the write time is Two, and the write voltage value when writing data to the area 33 of the second non-volatile memory device 21 or the non-volatile memory device 30 by the internal write / rewrite circuit 17 is Vwi. If the time is Twi,
Vwo> Vwi and Two <Twi
Meet the requirements of
In this data writing method, it is desirable that the threshold voltage Vth for guaranteeing the data retention characteristic after data writing is substantially the same value in any of the above writing.

When erasing data written in the semiconductor memory device described above , the first nonvolatile memory device 11 or the nonvolatile memory is used by using the external programming / rewriting device 3 through the external programming terminal 15 by the data erasing method according to the present invention. The write voltage value when writing data to the areas 31 and 32 of the volatile memory device 30 is Vwo, the erase voltage value when erasing data is Veo, and the erase time is Teo,
The write voltage value when writing data to the area 33 of the second nonvolatile memory device 21 or the nonvolatile memory device 30 by the internal write / rewrite circuit 17 is Vwi, the erase voltage value when erasing data is Vei, and the erase time Let Tei be
Veo> Vei and Teo <Tei
Meets the requirements of
Vwo> Veo and Vwi = Vei
Meet the requirements of
Each voltage value is a terminal voltage applied to the memory cell.

FIG. 6 is a diagram showing a write speed characteristic when data is written to the nonvolatile memory device 11, 21, or 30 described above.
The horizontal axis represents the writing time, and the vertical axis represents the threshold voltage Vth after data writing.
FIG. 6 shows the change in Vth with the write time from the erased state with the write voltage as a parameter. From this, in order to set 1.0 V, which is a sufficient writing Vth that guarantees the data retention characteristics, the writing time in the case of 9 V writing is 1 msec, and the writing time in the case of 7 V writing is 200 msec.

FIG. 7 is a diagram showing erase speed characteristics when data is erased from the above-described nonvolatile memory device 11, 21 or 30 according to the present invention .
The horizontal axis represents the erase time, and the vertical axis represents the threshold voltage Vth after data erase.
FIG. 7 shows the change in Vth with the erase time from the write state with the erase voltage as a parameter. Thus, in order to set −0.5V, which is a sufficient erase Vth that guarantees the data retention characteristics, the erase time in the case of 9V erase is 200 msec, and the erase time in the case of 7V erase is 1 sec.

  The writing voltage value or the erasing voltage value differs between the writing or erasing of data by the external writing / rewriting device 3 and the writing or erasing of data by the internal writing / rewriting circuit 17, but the threshold voltage Vth after writing or erasing is the data holding The writing or erasing time is adjusted so that the voltage value is almost the same as the value that guarantees the characteristic. The almost identical voltage values here include some differences such as slight variations.

The data erasing method of the semiconductor memory device according to the present invention can be widely used for various system ICs such as a microcomputer, and electronic devices and other devices equipped with the system ICs.
In addition, the semiconductor memory device can be efficiently used, improved in reliability, reduced in size, and shortened in the development period of the system IC.

1 is a block diagram showing a configuration of a first example of a system IC including a semiconductor memory device used in the present invention. It is a block diagram which shows the structure of the 2nd example of system IC containing the semiconductor memory device used for this invention. It is typical sectional drawing which shows the basic structure of the MONOS type | mold memory in the non-volatile memory device used for this invention. It is a typical sectional view showing other examples of a structure of a memory cell of a nonvolatile memory device similarly. FIG. 10 is a schematic cross-sectional view showing still another structural example of the memory cell of the nonvolatile memory device. It is a diagram showing a write speed characteristics when subjected to writing of data to the nonvolatile memory device in the semiconductor memory equipment. Is a graph showing the erasing speed characteristics when subjected to erasing data in the non-volatile memory device in a semiconductor memory device and more to the present invention. It is a block diagram which shows the structural example of the conventional common microcomputer.

Explanation of symbols

1, 2: System IC 3: External rewrite device 4: External output unit 10: Control circuit (CPU) 11: First nonvolatile memory device 21: Second nonvolatile memory device 30: Nonvolatile memory device 12, 22, 35: Address buffer 13, 23, 36: Row decoder 14, 24: Column decoder 15: External write terminal
17: Internal rewrite circuit 18: Peripheral circuit 31: Program area 32: Non-rewriteable data area
33: rewritable data area 37: column decoder / multiplexer 38: read circuit 39: output buffer 40: MONOS type memory 60: address transistor

Claims (1)

Data is written by an external write terminal, an internal write rewrite circuit, an external write rewrite device through the external write terminal using an external write rewrite device, and data is stored by the internal write rewrite circuit. A second non-volatile memory device that is written and rewritten, and the first non-volatile memory device and the second non-volatile memory device write data written in a semiconductor memory device having the same device structure. A data erasing method for erasing,
The external through said write terminal using the external write rewriting device first nonvolatile Vwo write voltage for writing data into the memory device, the erase voltage value at the time of erasing data Veo, the erase time and Teo ,
Assuming that the write voltage value when writing data to the second nonvolatile memory device by the internal write rewrite circuit is Vwi, the erase voltage value when erasing data is Vei, and the erase time is Tei,
Veo> Vei and Teo <Tei
Meets the requirements of
Vwo> Veo and Vwi = Vei
A method for erasing data in a semiconductor memory device, characterized in that :

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