JP4898246B2 - Pulse width modulation control method for inverter device. - Google Patents

Description

  The present invention relates to a control method for reducing switching loss of a three-phase inverter in a grid-connected inverter device.

  In the grid-connected inverter device, in order to efficiently supply the power generated by the solar panel to the three-phase power supply, the carrier frequency is lowered to reduce the switching loss even if the output control accuracy is lowered. Adopted the method.

  FIG. 8 is an electrical connection diagram of a conventional inverter device. In the figure, DCV is a direct current power source (for example, a solar panel). The first switching element TR1 to the sixth switching element TR6 are controllable elements that are turned on / off, and the feedback diode D1 to the feedback diode D6 are connected in reverse parallel to the first switching element TR1 to the sixth switching element TR6. Feedback the current. Further, a first arm composed of a second switching element TR2 connected in series to the first switching element TR1 and a second arm composed of a fourth switching element TR4 connected in series to the third switching element TR3. And a third arm composed of a sixth switching element TR6 connected in series to the fifth switching element TR5 to form a three-phase bridge connection to form a three-phase inverter circuit INV.

  The three-phase filter circuit ALC is formed by three reactors AL and three capacitors AC, and the three-phase filter circuit ALC removes the high-frequency component of the high-frequency pulse voltage output from the three-phase inverter circuit INV, and the fundamental wave component. Only the same frequency as the voltage of the three-phase system power supply (for example, 50 Hz or 60 Hz) is extracted.

  The transformer TRN boosts or steps down the AC output voltage of the three-phase inverter circuit INV determined by the voltage of the solar panel to a voltage substantially equal to the reference voltage of the three-phase system power supply.

  The output current detection circuit CT detects the U-phase output current output from the transformer TRN and outputs it as the first output current detection signal Iu, detects the V-phase output current, and outputs the second output current detection signal Iv. And the W-phase output current is detected and output as the third output current detection signal Iw.

  The high-frequency carrier signal generation circuit CR outputs a high-frequency (for example, 12 kHz) carrier signal Cr that is predetermined in a triangular waveform.

  The first arm pulse generation circuit is formed by a pulse width modulation circuit PWM, an output command setting circuit IR, and a feedback control circuit FB. The feedback control circuit FB includes a first output current detection signal Iu that is a feedback signal, and a target value. Is amplified and output as a feedback control signal Fbu, and the pulse width modulation circuit PWM is based on the comparison between the feedback control signal Fbu and the carrier signal Cr, and the first arm upper pulse width. The modulation signal Up1 and the first arm lower pulse width modulation signal Un1 are output.

  The second arm pulse generation circuit forms the same circuit as the first arm pulse generation circuit, the second output current detection signal Iv shifted by 120 ° with respect to the first output current detection signal Iu, and an output that is a target value. An error with the command setting signal Ir is amplified and output as a feedback control signal Fbv. Based on the comparison between the feedback control signal Fbv and the carrier signal Cr, the second arm upper side pulse width modulation signal Up2 and the second arm lower side The pulse width modulation signal Un2 is output.

  The third arm pulse generation circuit forms the same circuit as the first arm pulse generation circuit, and outputs a third output current detection signal Iw shifted by 240 ° with respect to the first output current detection signal Iu and a target value. An error with the command setting signal Ir is amplified and output as a feedback control signal Fbw. Based on the comparison between the feedback control signal Fbw and the carrier signal Cr, the third arm upper side pulse width modulation signal Up3 and the third arm lower side The pulse width modulation signal Un3 is output.

  The three-phase inverter drive circuit DR turns on / off the first switching element TR1 and the second switching element TR2 when the first arm upper pulse width modulation signal Up1 and the first arm lower pulse width modulation signal Un1 are input. The first switching signal Tr1 and the second driving signal Tr2 to be controlled are generated and output. When the second arm upper pulse width modulation signal Up2 and the second arm lower pulse width modulation signal Un2 are input, the third switching is performed. The third drive signal Tr3 and the fourth drive signal Tr4 for on / off control of the element TR3 and the fourth switching element TR4 are generated and output, and the third arm upper pulse width modulation signal Up3 and the third arm lower side When the pulse width modulation signal Un3 is input, the fifth switching element TR5 and the sixth switching element TR6 are turned on / off. 5 of the drive signal Tr5 and sixth generates a drive signal Tr6 outputted.

  FIG. 9 is a waveform diagram for explaining the operation of the first arm (U-phase) of the conventional inverter device shown in FIG. 8, and the second arm (V-phase) is phase-shifted by 120 ° with respect to the first arm. Since the third arm (W phase) performs the same operation with a phase shift of 240 ° with respect to the first arm, only the operation of the first arm (U phase) will be described and the second arm (V Phase) and the third arm (W phase) will be omitted.

  The waveform in FIG. 9A shows the feedback control signal Fbu and the carrier signal Cr, the waveform in FIG. 9B shows the first arm lower pulse width modulation signal Un1, and the waveform in FIG. 9C. Indicates the first arm upper side pulse width modulation signal Up1.

  The pulse width modulation circuit PWM shown in FIG. 8 compares the carrier signal Cr shown in FIG. 9A with the feedback control signal Fbu. When the carrier signal Cr is larger than the feedback control signal Fbu, the pulse width modulation circuit PWM shown in FIG. The first arm lower pulse width modulation signal Un1 shown becomes High level. The drive circuit DR outputs the second drive signal Tr2 to make the second switching element TR2 of the three-phase inverter circuit INV conductive while the first arm lower pulse width modulation signal Un1 is at a high level.

  Subsequently, in the pulse width modulation circuit PWM, when the carrier signal Cr is smaller than the feedback control signal Fbu, the first arm upper side pulse width modulation signal Up1 shown in FIG. 9C is at a high level. The drive circuit DR outputs the first drive signal Tr1 to turn on the first switching element TR1 of the three-phase inverter circuit INV during the period when the first arm upper pulse width modulation signal Up1 is at the high level, and the three-phase inverter The circuit INV is subjected to pulse width modulation for output control.

  As described above, in the conventional grid-connected inverter device, in order to efficiently convert the power generated by the solar panel and supply it to the three-phase system power supply, the carrier frequency of the three-phase inverter circuit INV is set. The switching loss is reduced by reducing the output current to a level that does not cause a decrease. (For example, Patent Document 1)

JP 11-53042 A

  In the grid-connected inverter device, it is required to efficiently convert the power generated by the solar panel or the like and supply it to the system power supply, and this conversion efficiency is improved by reducing the switching loss of the inverter device. Therefore, in the prior art, in order to reduce the switching loss, the carrier frequency of the inverter device is lowered to reduce the switching loss. However, the phase angles of the U-phase, V-phase, and W-phase of the three-phase AC voltage that is the output of the inverter device are around 30 ° to 60 °, 120 ° to 150 °, 210 ° to 240 °, and 300 ° to In the phase range near 330 °, the change amount (di / dt) of the output current value of the inverter device is very large. Therefore, if the carrier frequency is set lower than a predetermined frequency in this phase range, the output current value The inverter device does not sufficiently follow the amount of change (di / dt), and the output current becomes unstable. Therefore, there is a limit to the control method to reduce the carrier frequency uniformly over the entire phase angle of the U-phase, V-phase, and W-phase of the three-phase AC voltage, thereby reducing the switching loss and increasing the conversion efficiency of the inverter device.

  Therefore, the present invention provides a pulse width modulation control method for an inverter device in which the output current is stable even when the carrier frequency is lowered.

In order to solve the above-described problem, the first invention forms a three-phase bridge inverter from the first arm, the second arm, and the third arm connected to the output side of the DC power supply. The high-frequency component of the output high-frequency pulse voltage is removed by a three-phase filter, and only the fundamental wave component of the same frequency as the three-phase system power supply is extracted to output a three-phase AC voltage. In an output control method of an inverter device that controls output by pulse width modulation control based on a predetermined high frequency carrier frequency, a predetermined low frequency carrier frequency lower than the high frequency carrier frequency is provided, and the three-phase AC when U-phase voltage, the phase angle of the V-phase and W-phase is in the phase range of 60 ° to 120 ° and 240 ° to 300 ° is selected carrier frequency of the low frequency And, when said each phase angle is out of the phase range, selects the carrier frequency of the high frequency, it is a pulse width modulation control method for an inverter apparatus according to claim.

  According to the first aspect of the invention, when the output current value of the inverter device is in the phase range where the output current is small, the high frequency carrier frequency is adjusted to be high, so that the output current can be stably improved without greatly increasing the switching loss. Then, when the change amount (di / dt) of the output current value of the inverter device is in a large phase range, the output current value is adjusted to a predetermined high-frequency carrier frequency that stabilizes the output current. When the output current value is large but the change amount (di / dt) is in the phase range where the change amount (di / dt) is small, the high-frequency carrier frequency is adjusted to be lower, so that the switching loss is not reduced without reducing the output current stability. Can be reduced. As described above, when the carrier frequency is varied according to the phase angles of the U-phase, V-phase, and W-phase of the three-phase AC voltage that is the output of the inverter device, only the switching loss is reduced without reducing the stability of the output current. It becomes possible to improve the conversion efficiency of the apparatus.

  According to the second invention, when the phase angles of the U-phase, V-phase, and W-phase of the three-phase AC voltage are within a predetermined phase range centering on the phase 90 ° and the phase 270 °, the output current value However, since the change amount (di / dt) is small, even if the predetermined high-frequency carrier frequency is adjusted to be low, the conversion efficiency of the inverter device is reduced by reducing only the switching loss without reducing the stability of the output current. Therefore, it is possible to reduce the size of the cooling device without requiring a large change in the control circuit or the like.

[Embodiment 1]
FIG. 1 is an electrical connection diagram of an inverter device according to Embodiment 1 of the present invention. In the figure, components having the same reference numerals as those in the electrical connection diagram of the prior art inverter device shown in FIG. 8 perform the same operations, and thus description thereof will be omitted. Only components having different reference numerals will be described.

  The output voltage circuit VT detects the U-phase voltage of the three-phase AC voltage output from the transformer TRN and outputs it as the first output voltage detection signal Vu, detects the V-phase voltage, and detects the second output voltage. It outputs as the signal Vv, detects the W-phase voltage, and outputs it as the third output voltage detection signal Vw.

  The carrier signal generation circuit CR outputs a high frequency (for example, 12 KHz) carrier signal Cr, the carrier signal generation circuit CRH outputs a carrier signal Crh having a higher frequency (for example, 24 KHz), and the carrier generation circuit CRL The carrier signal Crl is output at a lower frequency (for example, 6 KHz).

  The frequency-corresponding first arm pulse generation circuit shown in FIG. 1 is formed by a pulse width modulation circuit PWM, an output command setting circuit IR, a feedback control circuit FB, a carrier signal selection circuit SE, and a phase range setting circuit PU. The frequency-corresponding second arm pulse generating circuit and the frequency-corresponding third arm pulse generating circuit have the same configuration as the above-described frequency-corresponding first arm pulse generating circuit, and therefore the description thereof will be omitted. Only will be described.

  FIG. 3 is a detailed diagram of the phase range setting circuit PU. The first base counter circuit BC1, the first mode selection circuit MS1, the first counter setting circuit CE1, the second base counter circuit BC2, the second mode selection circuit MS2, the second mode selection circuit MS2, and the second mode selection circuit MS2. 2 counter setting circuit CE2 and pulse generation circuit PG. Each waveform shown in FIG. 4 explains the operation of the phase range setting circuit PU. FIG. 4 (A) shows the waveform of the first output voltage detection signal Vu, and FIG. 4 (B) shows the pulse. FIG. 4C shows the first base counter signal Bc1, FIG. 4D shows the first mode selection signal Pua, and FIG. 4E shows the second base counter signal. Bc2 is shown, and FIG. 4F shows the second mode selection signal Pub.

  When the first output voltage detection signal Vu shown in FIG. 4A is input to the first base counter circuit BC1 and the second base counter circuit BC2 and crosses zero at time t = t0, the first base counter circuit BC1 and the second base counter circuit BC2 The base counter circuit BC2 is reset and counts the pulse generation signal Pg from the pulse generation circuit PG.

  The first counter setting circuit CE1 sets a predetermined first counter value and outputs it as a first counter setting signal Ce1. The first base counter circuit BC1 counts the pulse generation signal Pg, and outputs a first pulse first base counter signal Bc1 shown in FIG. 4C at time t = t1, based on the first counter setting signal Ce1. . The first mode selection circuit MS1 changes the first mode selection signal Pua shown in FIG. 4D from High level to Low level in response to the first base counter signal Bc1. From the above, the first mode selection circuit MS1 sets the phase range 0 ° to 30 ° of the U phase of the three-phase AC voltage.

  The second counter setting circuit CE2 sets a predetermined second counter value and outputs it as a second counter setting signal Ce2. The second base counter circuit BC2 counts the pulse generation signal Pg and outputs the one-pulse second base counter signal Bc2 shown in FIG. 4E at time t = t2 based on the second counter setting signal Ce2. . The second mode selection circuit MS2 sets the second mode selection signal Pub shown in FIG. 4F to High level in response to the second base counter signal Bc2. Subsequently, the second base counter circuit BC2 continues to count the pulse generation signal Pg and outputs the second base counter signal Bc2 of one pulse at time t = t3 based on the second counter setting signal Ce2. The second mode selection circuit MS2 changes the second mode selection signal Pub shown in FIG. 4F from High level to Low level in response to the second base counter signal Bc2. From the above, the second mode selection circuit MS2 sets the phase range 60 ° to 120 ° of the U phase of the three-phase AC voltage.

  The first base counter circuit BC1 continues to count the pulse generation signal Pg, and outputs the first base counter signal Bc1 of one pulse at time t = t4 based on the first counter setting signal Ce1. In response to the first base counter signal Bc1, the first mode selection circuit MS1 sets the first mode selection signal Pua shown in FIG. 4D to a high level.

  The first output voltage detection signal Vu shown in FIG. 4A changes from a positive polarity to a negative polarity at time t = t5.

  The first base counter circuit BC1 continues to count the pulse generation signal Pg, and outputs one pulse of the first base counter signal Bc1 at time t = t6 based on the first counter setting signal Ce1. The first mode selection circuit MS1 changes the first mode selection signal Pua shown in FIG. 4F from the High level to the Low level in response to the output of the first base counter signal Bc1. From the above, the first mode selection circuit MS1 sets the phase range 150 ° to 210 ° of the U phase of the three-phase AC voltage. Thereafter, the same operation as described above is performed, the second mode selection circuit MS2 sets the phase range 240 ° to 300 ° of the U phase of the three-phase AC voltage, and the first mode selection circuit MS1 has the phase range 330 ° to Set 360 °.

  FIG. 2 is a waveform diagram illustrating the operation of the first arm of the inverter device according to the first embodiment of the present invention shown in FIG. 1, and the second arm operates with a phase shift of 120 ° with respect to the first arm. Since the third arm performs the same operation with a phase shift of 240 ° with respect to the first arm, only the operation of the first arm will be described, and the description of the second arm and the third arm will be omitted.

  The waveform in FIG. 2A shows a high frequency (for example, 12 KHz) carrier signal Cr, and the waveform in FIG. 2B shows a carrier signal Crl with a low frequency (for example, 6 KHz). ) Shows the carrier signal Crh with a higher frequency (for example, 24 KHz). The waveform of FIG. 2D shows the carrier signal selection signal Se, the waveform of FIG. 2E shows the first arm lower pulse width modulation signal Un1, and the waveform of FIG. The one-arm upper side pulse width modulation signal Up1 is shown.

  The phase range setting circuit PU counts the phase angle of the U-phase first output voltage detection signal Vu detected by the output voltage circuit VT, and when time t = t1 (phase angle is 30 °) shown in FIG. The first mode selection signal Pua is changed from High level to Low level. The carrier signal selection circuit SE selects and outputs the carrier signal Crh shown in FIG. 2C (for example, 24 KHz) with the contact point set to the a side while the first mode selection signal Pua is at the High level.

  The pulse width modulation circuit PWM compares the carrier signal Crh and the feedback control signal Fbu shown in FIG. 2D. When the carrier signal Crh is larger than the feedback control signal Fbu, the first pulse shown in FIG. When the arm lower side pulse width modulation signal Un1 becomes High level and the carrier signal Crh is smaller than the feedback control signal Fbu, the first arm upper side pulse width modulation signal Up1 shown in FIG. 2F becomes High level. At this time, even if the carrier frequency is increased, the increase in switching loss is small and the control of the output current of the inverter device can be increased without lowering the power conversion efficiency.

  The phase range setting circuit PU counts the phase angle of the first output voltage detection signal Vu, and when the time t = t2 (phase angle is 60 °) shown in FIG. 2, the second mode selection signal Pub is set to the high level. To do. At this time, during the period of time t = t1 to t2, both the first mode selection signal Pua and the second mode selection signal Pub are at the low level. When the first mode selection signal Pua and the second mode selection signal Pub are both at the low level, the carrier signal selection circuit SE sets the contact point to the c side, and the carrier signal Cr (for example, 12 KHz) shown in FIG. Select to output.

  The pulse width modulation circuit PWM compares the carrier signal Cr with the feedback control signal Fbu during the period of time t = t1 to t2, and when the carrier signal Cr is greater than the feedback control signal Fbu, it is shown in FIG. When the first arm lower pulse width modulation signal Un1 is at high level and the carrier signal Cr is smaller than the feedback control signal Fbu, the first arm upper pulse width modulation signal Up1 shown in FIG. 2 (F) is at high level. . At this time, since the change amount (di / dt) of the output current value of the inverter device is large, if the carrier frequency is increased, the increase in switching loss is increased, so that the carrier frequency (for example, 12 KHz) is maintained.

  The phase range setting circuit PU counts the phase angle of the first output voltage detection signal Vu, and sets the second mode selection signal Pub to the low level at time t = t3 (phase angle is 120 °) shown in FIG. To do. At this time, during the period from time t = t2 to t3, the second mode selection signal Pub becomes High level. When the second mode selection signal Pub is at a high level, the carrier signal selection circuit SE selects the carrier signal Crl shown in FIG.

  The pulse width modulation circuit PWM compares the carrier signal Crl and the feedback control signal Fbu during the period of time t = t2 to t3, and when the carrier signal Crl feedback control signal Fbu is greater than the time shown in FIG. When the one-arm lower pulse width modulation signal Un1 is at a high level and the carrier signal Crl is smaller than the feedback control signal Fbu, the first arm upper pulse width modulation signal Up1 shown in FIG. 2 (E) is at a high level. At this time, since the output current value is large but the change amount (di / dt) of the output current value is small, even if the carrier frequency of the high frequency is lowered, the control of the output current of the inverter device is not lowered and only the switching loss value is obtained. Decrease.

  The phase range setting circuit PU counts the phase angle of the first output voltage detection signal Vu, and sets the first mode selection signal Pua to the High level again at time t = t4 (phase angle is 150 °). At this time, during the period from time t = t3 to t4, both the first mode selection signal Pua and the second mode selection signal Pub are at the low level. When both the first mode selection signal Pua and the second mode selection signal Pub are at the Low level, the carrier signal selection circuit SE selects the carrier signal Cr shown in FIG. .

  The pulse width modulation circuit PWM compares the carrier signal Cr with the feedback control signal Fbu during the period of time t = t3 to t4, and when the carrier signal Cr is greater than the feedback control signal Fbu, the pulse width modulation circuit PWM is shown in FIG. When the first arm lower pulse width modulation signal Un1 is at high level and the carrier signal Cr is smaller than the feedback control signal Fbu, the first arm upper pulse width modulation signal Up1 shown in FIG. 2 (F) is at high level. .

  The phase range setting circuit PU counts the phase angle of the first output voltage detection signal Vu and sets the first mode selection signal Puaw level at time t = t6 (phase angle is 210 °). At this time, during the period from time t = t4 to t5, the first mode selection signal Pua is at a high level. The carrier signal selection circuit SE selects and outputs the carrier signal Crh shown in FIG. 2C with the contact point set to the a side while the first mode selection signal Pua is at the High level.

  The first pulse width modulation circuit PWM1 compares the carrier signal Crh with the feedback control signal Fbu during the period of time t = t4 to t6, and when the carrier signal Crh is greater than the feedback control signal Fbu, FIG. When the first arm lower pulse width modulation signal Un1 shown in FIG. 2 becomes High level and the carrier signal Crh is smaller than the feedback control signal Fbu, the first arm upper pulse width modulation signal Up1 shown in FIG. Become a level.

  Thereafter, time t = t6 to t7 is the same as time t = t1 to t2, time t = t7 to t8 is the same as time t = t2 to t3, and time t = t8 to t9 is time t = Since the same operation as t3 to t4 is performed, the description is omitted.

  As described above, the power conversion efficiency of the inverter device can be increased by appropriately changing the high-frequency carrier frequency according to the phase angles of the U-phase, V-phase, and W-phase of the three-phase AC voltage.

[Embodiment 2]
FIG. 5 is an electrical connection diagram of the inverter device according to the second embodiment of the present invention. In the figure, components having the same reference numerals as those in the electrical connection diagram of the inverter device according to the second embodiment shown in FIG. 1 and the electrical connection diagram of the prior art inverter device shown in FIG. Only components having different reference numerals will be described.

  The phase range setting circuit PU of the second embodiment shown in FIG. 5 has the same configuration as the phase range setting circuit PU shown in FIG. 3, but the first base counter circuit BC1, the first mode selection circuit MS1, and the first counter setting circuit. CE1 is not used, and only the second base counter circuit BC2, the second mode selection circuit MS2, the second counter setting circuit CE2, and the pulse generation circuit PG are used.

  7A shows the waveform of the first output voltage detection signal Vu, FIG. 7B shows the pulse generation signal Pg, FIG. 7C shows the second base counter signal Bc2, and FIG. (D) shows the second mode selection signal Pub.

  When the first output voltage detection signal Vu shown in FIG. 7A is input to the second base counter circuit BC2 shown in FIG. 3 and the input signal crosses zero at time t = t0, the second base counter circuit BC2 is reset. The pulse generation signal Pg from the pulse generation circuit PG is counted.

  The second counter setting circuit CE2 sets a predetermined counter value and outputs it as a second counter setting signal Ce2. The second base counter circuit BC2 counts the pulse generation signal Pg and outputs the second base counter signal Bc2 shown in FIG. 7C at time t = t2 based on the second counter setting signal Ce2. The second mode selection circuit MS2 sets the second mode selection signal Pub shown in FIG. 7D to High level in response to the second base counter signal Bc2. Subsequently, the second base counter circuit BC2 continues to count the pulse generation signal Pg, and outputs the second base counter signal Bc2 at time t = t3 based on the second counter setting signal Ce2. The second mode selection circuit MS2 changes the second mode selection signal Pub shown in FIG. 7D from High level to Low level in accordance with the second base counter signal Bc2. Thereafter, the same operations as described above are performed at times t = t7 and t8, and thus the description thereof is omitted.

  FIG. 6 is a waveform diagram for explaining the operation of the first arm of the inverter device according to the second embodiment of the present invention shown in FIG. 5, in which the second arm operates in a state shifted by 120 ° with respect to the first arm. Since the third arm performs the same operation with a phase shift of 240 ° with respect to the first arm, only the operation of the first arm will be described, and the description of the second arm and the third arm will be omitted.

  The waveform in FIG. 6A shows the waveform of the carrier signal Cr having a high frequency (for example, 12 KHz), and the waveform in FIG. 6B shows the carrier signal Crl having a low frequency (for example, 6 KHz). The waveform in FIG. 6C shows the first output voltage detection signal Vu, the waveform in FIG. 6D shows the carrier signal selection signal Se, and the waveform in FIG. 6E shows the lower side of the first arm. The pulse width modulation signal Un1 is shown, and the waveform of FIG. 6F shows the first arm upper pulse width modulation signal Up1.

  The phase range setting circuit PU counts the phase angle of the first output voltage detection signal Vu, and sets the second mode selection signal Pub to High level at time t = t2 (phase angle is 60 °) shown in FIG. To do. At this time, during the period from time t = t0 to t2, the second mode selection signal Pub is at the low level. When the second mode selection signal Pub is at the low level, the carrier signal selection circuit SE selects the carrier signal Cr (for example, 12 KHz) shown in FIG.

  The pulse width modulation circuit PWM compares the carrier signal Cr with the feedback control signal Fbu during the period of time t = t0 to t2, and when the carrier signal Cr is greater than the feedback control signal Fbu, it is shown in FIG. When the first arm lower pulse width modulation signal Un1 is at high level and the carrier signal Cr is smaller than the feedback control signal Fbu, the first arm upper pulse width modulation signal Up1 shown in FIG. 6 (F) is at high level. .

  The phase range setting circuit PU counts the phase angle of the first output voltage detection signal Vu and sets the second mode selection signal Pub to the low level at time t = t3 (phase angle is 120 °) shown in FIG. To do. At this time, during the period from time t = t2 to t3, the second mode selection signal Pub becomes High level. The carrier signal selection circuit SE selects and outputs the carrier signal Crl shown in FIG. 6B with the contact point set to the b side when the second mode selection signal Pub is at a high level.

  The pulse width modulation circuit PWM1 compares the carrier signal Crl and the feedback control signal Fbu during the period of time t = t2 to t3, and when the carrier signal Crl is larger than the feedback control signal Fbu, the pulse width modulation circuit PWM1 is shown in FIG. When the first arm lower pulse width modulation signal Un1 becomes High level and the carrier signal Crl is smaller than the feedback control signal Fbu, the first arm upper pulse width modulation signal Up1 shown in FIG. 6F becomes High level. .

  The phase range setting circuit PU counts the phase angle of the first output voltage detection signal Vu, and sets the second mode selection signal Pub to the high level again at time t = t7 (phase angle is 240 °) shown in FIG. To. At this time, during the period from time t = t3 to t7, the second mode selection signal Pub is at the low level. When the second mode selection signal Pub is at a low level, the carrier signal selection circuit SE selects the carrier signal Cr shown in FIG.

  The pulse width modulation circuit PWM compares the carrier signal Cr with the feedback control signal Fbu during the period of time t = t3 to t7, and when the carrier signal Cr is greater than the feedback control signal Fbu, the pulse width modulation circuit PWM is shown in FIG. When the first arm lower pulse width modulation signal Un1 is at high level and the carrier signal Cr is smaller than the feedback control signal Fbu, the first arm upper pulse width modulation signal Up1 shown in FIG. 6 (F) is at high level. .

  The phase range setting circuit PU counts the phase angle of the first output voltage detection signal Vu, and sets the second mode selection signal Pub to Low level at time t = t8 (phase angle is 300 °) shown in FIG. To do. At this time, during the period from time t = t7 to t8, the second mode selection signal Pub becomes High level. The carrier signal selection circuit SE selects and outputs the carrier signal Crl shown in FIG. 6B with the contact point set to the b side when the second mode selection signal Pub is at a high level.

  The pulse width modulation circuit PWM1 compares the carrier signal Crl and the feedback control signal Fbu during the period of time t = t7 to t8, and when the carrier signal Crl feedback control signal Fbu is larger than the first signal shown in FIG. When the one-arm lower pulse width modulation signal Un1 is at a high level and the carrier signal Crl is smaller than the feedback control signal Fbu, the first arm upper pulse width modulation signal Up1 shown in FIG. 6 (F) is at a high level.

  From the above, when the phase angles of the U-phase, V-phase, and W-phase of the three-phase AC voltage are within a predetermined phase range centering on the phase 90 ° and the phase 270 °, the high-frequency carrier frequency is lowered. It is possible to reduce the switching loss and increase the power conversion efficiency of the inverter device.

It is an electrical connection figure of the inverter apparatus which concerns on Embodiment 1 of this invention. FIG. 3 is a waveform diagram for explaining the operation of the inverter device according to the first embodiment. FIG. 2 is a detailed diagram of a phase range setting circuit shown in FIG. 1. It is a wave form diagram explaining operation | movement of the phase range setting circuit shown in FIG. FIG. 5 is an electrical connection diagram of an inverter device according to a second embodiment. FIG. 6 is a waveform diagram for explaining the operation of the inverter device according to the second embodiment. FIG. 6 is a waveform diagram for explaining the operation of a phase range setting circuit used in the second embodiment. It is an electrical connection figure of the inverter apparatus of a prior art. It is a wave form diagram explaining operation | movement of the inverter apparatus of a prior art.

Explanation of symbols

AC capacitor AL reactor BC1 first base counter circuit BC2 second base counter circuit Bc1 first base counter signal Bc2 second base counter signal CT output current detection circuit CR carrier signal generation circuit CRH carrier signal generation circuit CRL carrier signal generation circuit CE1 first 1 counter setting circuit Ce1 first counter setting signal CE2 second counter setting circuit Ce2 second counter setting signal Cr carrier signal (for example, 12 KHz)
Crh carrier signal (eg 24KHz)
Crl carrier signal (eg 6KHz)
DR drive circuit D1 feedback diode D2 feedback diode D3 feedback diode D4 feedback diode D5 feedback diode D6 feedback diode DCV DC power supply (solar panel)
FB feedback control circuit Fbu feedback control signal IR output command setting circuit Iru output command setting signal Iu first output current detection signal Iv second output current detection signal Iw third output current detection signal MS1 first mode selection circuit PWM first pulse width Modulation circuit PU Phase range setting circuit Pua First mode selection signal Pub Second mode selection signal PG pulse generation circuit Pg pulse generation signal SE carrier signal selection circuit TR1 first switching element TR2 second switching element TR3 third switching element TR4 4th switching element TR5 5th switching element TR6 6th switching element Tr1 1st drive signal Tr2 2nd drive signal Tr3 3rd drive signal Tr4 4th drive signal Tr5 5th drive signal Tr6 5th 6 drive No. TRN Transformer Un1 First arm lower pulse width modulation signal Up1 First arm upper pulse width modulation signal Un2 Second arm lower pulse width modulation signal Up2 Second arm upper pulse width modulation signal Un3 Third arm Lower side pulse width modulation signal Up3 Third arm upper side pulse width modulation signal VT Output voltage detection circuit Vu First output voltage detection signal Vv Second output voltage detection signal Vw Third output voltage detection signal

Claims (1)

A three-phase bridge inverter is formed from the first arm, the second arm and the third arm connected to the output side of the DC power supply, and the high-frequency component of the high-frequency pulse voltage output from the three-phase inverter is removed by a three-phase filter. Only the fundamental wave component of the same frequency as the three-phase system power supply is extracted to output a three-phase AC voltage, and the arm of each phase of the three-phase inverter is subjected to pulse width modulation control based on a predetermined high-frequency carrier frequency. In the output control method of the inverter device for controlling the output, a predetermined low-frequency carrier frequency lower than the high-frequency carrier frequency is provided, and the phase angles of the U-phase, V-phase, and W-phase of the three-phase AC voltage are When in the phase range of 60 ° to 120 ° and 240 ° to 300 °, when the carrier frequency of the low frequency is selected and each phase angle is out of the phase range , It selects the carrier frequency of the high frequency pulse width modulation control method for an inverter apparatus, characterized in that.

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