JP4900470B2 - Moving picture coding apparatus and moving picture coding method - Google Patents

Description

  The present invention relates to MPEG-1, MPEG-2, MPEG-4, H.264. The present invention relates to a moving image encoding apparatus and a moving image encoding method compliant with a moving image encoding standard such as H.264 / AVC and WMV.

  Recently, moving image reproduction systems are demanding reproduction of high-quality moving images such as high-definition (high resolution, low noise, high frame rate, etc.). When reproducing a high-resolution moving image, it is necessary to process a larger amount of data than when reproducing a low-resolution moving image, so that a large memory capacity and memory access are required. In high-resolution video decoding processing, when decoding encoded data generated by encoding processing using motion compensation, which is one of the elemental technologies of video encoding technology, a reference image is loaded. A large amount of processing is performed. The process of reading the reference image from the external memory leads to a decrease in the frame rate and an increase in power consumption of the video decoding device (processor). As a method for avoiding this problem, there is a method of providing a cache memory in the moving picture decoding apparatus.

  For details of video coding technology (motion compensation, etc.), please refer to standards such as “Recommendation ITU-T H.262” and “Point Graphical Newest MPEG Textbook” (supervised by Hiroshi Fujiwara, ASCII Publishing Bureau). Since it is described in general books, a detailed description thereof is omitted here. The details of the cache memory are described in general books such as “Computer Configuration and Design 3rd Edition” (by David A. Patterson, John L. Hennessy, Nikkei Business Publications). The detailed description of is omitted.

  FIG. 15 shows the decoding processing order and the cache memory status when decoding the encoded data in the prior art. When decoding the encoded data in the prior art, first, the first row (FIG. 15 (1)) of the reference image P is decoded in order from the macroblock MB in the first column (left end). Then, when the decoding of the macroblock MB in the last column (right end) in the first row of the reference image P is completed, the macroblock MB in the first column in order from the macroblock MB in the first column in the second row of the reference image P (FIG. 15 (2)). Decrypted. Thereafter, similarly, the macroblock MB in the third row (FIG. 15 (3)), the fourth row (FIG. 15 (4)),..., The nth row (FIG. 15 (n)) of the reference image P Decrypted in order.

  When the decoding of the macroblock MB in the first row of the reference image P is completed and the process proceeds to the decoding of the macroblock MB in the second row of the reference image P, the capacity of the cache memory is small and exists in the cache memory. Assuming that the reference image data is only the data corresponding to the shaded portion in FIG. 15, the reference image data in the vicinity of the macro block MB in the second row of the reference image P does not exist in the cache memory. A load cache miss occurs.

  A load cache miss does not occur if the capacity of the cache memory is sufficiently increased with respect to the resolution (image size) of the moving picture. However, if the capacity of the cache memory is increased, an increase in load latency and a moving picture decoding apparatus (processor). Disadvantages such as increased power consumption and increased chip area. Also, the higher the resolution of the moving image, the larger the capacity of the cache memory is to suppress the occurrence of load cache misses. For example, when the resolution of the moving image is HD size (vertical 1920 pixels × horizontal 1080 pixels), a cache memory having a capacity of about 90 Kbytes is required.

Patent Document 1 discloses a technique for reducing overhead time associated with access to a cache memory regarding still image reproduction processing including corner turn processing (vertical / horizontal transposition processing) of a Synthetic Aperture Radar (SAR) image. Is disclosed.
JP 2001-109880 A

  As described above, in the video decoding device, when the capacity of the cache memory is increased in order to suppress the occurrence of a load cache miss, the load latency increases, the power consumption of the video decoding device (processor) and the chip area are reduced. There was a problem that disadvantages such as an increase occurred.

  An object of the present invention is to suppress the occurrence of a load cache miss when decoding encoded data without increasing the capacity of the cache memory even when the resolution of the moving image is high.

In one aspect of the present invention, a moving image encoding apparatus divides an image division number setting unit for setting the number of image divisions, an encoding target image constituting the moving image into partial images having the same number as the number of image divisions, And an encoding unit that performs an encoding process using motion compensation for each image. The image division number setting unit is used for decoding the encoding result of the image information setting unit that sets the image size, luminance color difference format, macroblock size, or number of reference images of the encoding target image, and the encoding unit. A cache information setting unit that sets a capacity of a cache memory or a cache method, and an image division number calculation unit that calculates an image division number based on information set by the image information setting unit and the cache information setting unit.
In the technology related to the present invention , the moving image encoding apparatus includes an image division number setting unit and an encoding unit. The image division number setting unit sets the image division number (image division number setting step). An encoding part divides | segments the encoding object image which comprises a moving image into the partial image of the same number as an image division | segmentation number, and implements the encoding process using motion compensation for every partial image (encoding process).

  For example, the partial image includes a first partial image and a second partial image. The encoded data generated by the encoding process has a structure in which the encoded data of the first partial image is followed by the encoded data of the second partial image. The encoding unit performs the encoding process of the second partial image after performing the encoding process of the first partial image.

  Preferably, the image division number setting unit sets the number of processors used when decoding the encoding result of the encoding unit as the image division number.

  Alternatively, the image division number setting unit includes an image information setting unit, a cache information setting unit, and an image division number calculation unit. The image information setting unit sets information related to the encoding target image (image information setting step). The cache information setting unit sets information related to the cache memory used when decoding the encoding result of the encoding unit (cache information setting step). The image division number calculation unit calculates the image division number based on information set by the image information setting unit and the cache information setting unit (image division number calculation step).

  Alternatively, the image division number setting unit includes a processor number setting unit, an image information setting unit, a cache information setting unit, and an image division number calculating unit. The processor number setting unit sets the number of processors used when decoding the encoding result of the encoding unit (processor number setting step). The image information setting unit sets information related to the encoding target image (image information setting step). The cache information setting unit sets information related to the cache memory used when decoding the encoding result of the encoding unit (cache information setting step). The image division number calculation unit calculates the image division number based on information set by the processor number setting unit, the image information setting unit, and the cache information setting unit (image division number calculation step).

  In the moving image encoding apparatus as described above, the encoding processing order of the encoding unit can be changed according to the number of image divisions set by the image division number setting unit, so that the encoding result of the encoding unit can be decoded. Even when the capacity of the cache memory used is not sufficiently large with respect to the resolution of the moving image, the occurrence of a load cache miss can be suppressed.

  According to the present invention, even when the resolution of a moving image is high, it is possible to suppress occurrence of a load cache miss when decoding encoded data without increasing the capacity of the cache memory.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a first embodiment of the present invention. A moving image encoding apparatus 10 according to the first embodiment includes an image division number setting unit 11 and an encoding unit 12. For example, the moving image encoding device 10 is implemented by a semiconductor device. The image division number setting unit 11 sets the number of image divisions. The encoding unit 12 acquires the number of image divisions held by the image division number setting unit 11 and divides the encoding target image constituting the input data (moving image) into the same number of partial images as the number of image divisions. Encoding processing using motion compensation is performed for each partial image to generate encoded data.

FIG. 2 shows the operation of the video encoding apparatus in the first embodiment. In the video encoding device 10 having the above-described configuration, the encoding unit 12 determines the number of image divisions held by the image division number setting unit 11 as the input data is received by the video encoding device 10. Obtain (step S11). Then, the encoding unit 12 divides the encoding target image into the same number of partial images as the number of image divisions, and performs an encoding process using motion compensation for each partial image (step S12 ).

  FIG. 3 shows an encoding processing order and encoded data structure (when the number of image divisions is 2) in the first embodiment. As shown in FIG. 3 <A>, in the encoding process by the encoding unit 12, when the number of image divisions is 2, the encoding target image P is divided into partial images P1 and P2. First, the partial image P1 is selected as the processing target partial image, and the first row (FIG. 3 (1)) of the partial image P1 is sequentially encoded from the macroblock MB in the first column (left end). Then, when the encoding of the macroblock MB in the last column (right end) in the first row of the partial image P1 is completed, the macroblock MB in the first column in order from the macroblock MB in the first column in the second row of the partial image P1 (FIG. 3 (2)). Encoded. Thereafter, similarly, the macroblock MB in the third row (FIG. 3 (3)), the fourth row (FIG. 3 (4)),..., The nth row (FIG. 3 (n)) of the partial image P1 Encoded in order.

  When the encoding of the macroblock MB of the last column in the nth row of the partial image P1 is completed, the partial image P2 is selected as the processing target partial image, and the first column of the first row (FIG. 3 (n + 1)) of the partial image P2 is selected. Are encoded sequentially from the macroblock MB. When the encoding of the macroblock MB in the last column in the first row of the partial image P2 is completed, the second row (FIG. 3 (n + 2)) in the partial image P2 is encoded in order from the macroblock MB in the first column. The Thereafter, similarly, the macroblock MB in the third row (FIG. 3 (n + 3)), the fourth row (FIG. 3 (n + 4)),..., The n-th row (FIG. 3 (n + n)) of the partial image P2 Encoded in order. The encoded data generated by the encoding process in such a processing order has a structure as shown in FIG. Note that the encoded data in the prior art has a structure as shown in FIG.

  FIG. 4 shows the encoding processing order and the structure of encoded data (when the number of image divisions is 3) in the first embodiment. As shown in FIG. 4A, in the encoding process by the encoding unit 12, when the number of image divisions is 3, the encoding target image P is divided into partial images P1, P2, and P3. First, the partial image P1 is selected as the processing target partial image, and the first row (FIG. 4 (1)) of the partial image P1 is encoded sequentially from the macroblock MB in the first column. When the encoding of the last row of macroblocks MB in the first row of the partial image P1 is completed, the second row of the partial image P1 (FIG. 4 (2)) is sequentially encoded from the macroblock MB of the first row. The Thereafter, similarly, the macroblock MB in the third row (FIG. 4 (3)), the fourth row (FIG. 4 (4)),..., The nth row (FIG. 4 (n)) of the partial image P1 is obtained. Encoded in order.

  When the encoding of the macroblock MB in the last column in the nth row of the partial image P1 is completed, the partial image P2 is selected as the processing target partial image, and the first column in the first row (FIG. 4 (n + 1)) of the partial image P2 Are encoded sequentially from the macroblock MB. When the encoding of the macroblock MB of the last column in the first row of the partial image P2 is completed, the second row (FIG. 4 (n + 2)) of the partial image P2 is encoded sequentially from the macroblock MB of the first column. The Thereafter, similarly, the macroblock MB in the third row (FIG. 4 (n + 3)), the fourth row (FIG. 4 (n + 4)),..., The n-th row (FIG. 4 (n + n)) of the partial image P2 Encoded in order.

  When the encoding of the macroblock MB in the last column in the nth row of the partial image P2 is completed, the partial image P3 is selected as the processing target partial image, and the first column in the first row (FIG. 4 (2n + 1)) of the partial image P3. Are encoded sequentially from the macroblock MB. When the encoding of the last row of macroblocks MB in the first row of the partial image P3 is completed, the second row of the partial image P3 (FIG. 4 (2n + 2)) is sequentially encoded from the macroblock MB of the first row. The Thereafter, similarly, the macroblock MB in the third row (FIG. 4 (2n + 3)), the fourth row (FIG. 4 (2n + 4)),..., The n-th row (FIG. 4 (2n + n)) of the partial image P3. Encoded in order. The encoded data generated by the encoding process of such processing order has a structure as shown in FIG. 4 <B>. Note that the encoded data in the prior art has a structure as shown in FIG.

  FIG. 5 shows an example of the encoding process in the first embodiment. Steps S101 to S108 in FIG. 5 are performed in step S12 in FIG.

  In step S101, the encoding unit 12 creates various headers. Thereafter, the encoding process proceeds to step S102.

  In step S102, the encoding unit 12 creates a slice header. Thereafter, the encoding process proceeds to step S103.

  In step S103, the encoding unit 12 encodes the processing target macroblock in the processing target row of the processing target partial image. Thereafter, the encoding process proceeds to step S104.

  In step S <b> 104, the encoding unit 12 determines whether or not the processing target macroblock is the macroblock in the last column in the processing target partial image. If the processing target macroblock is not the macroblock of the last column in the processing target partial image, the encoding process proceeds again to step S103 in order to encode the macroblock of the next column in the processing target row of the processing target partial image. To do. On the other hand, when the processing target macroblock is the macroblock of the last column in the processing target partial image, the encoding process proceeds to step S105.

  In step S <b> 105, the encoding unit 12 determines whether or not the processing target macroblock is the macroblock of the last row in the processing target partial image. When the processing target macroblock is not the macroblock of the last row in the processing target partial image, the encoding process proceeds to step S106. On the other hand, when the processing target macro block is the macro block of the last row in the processing target partial image, the encoding process proceeds to step S107.

  In step S106, the encoding unit 12 changes the processing target row to the next row in the processing target partial image. Thereafter, the encoding process proceeds to step S102 again.

  In step S107, the encoding unit 12 determines whether there is input data that has not been read from the reception buffer for temporarily storing the input data. If there is input data that has not been read from the reception buffer, the encoding process proceeds to step S108. On the other hand, when there is no input data that has not been read from the reception buffer, the encoding process is completed.

  In step S108, the encoding unit 12 changes the processing target partial image to the next partial image. Thereafter, the encoding process proceeds to step S102 again.

  FIG. 6 shows another example of the encoding process in the first embodiment. Steps S101 to S108 in FIG. 6 are performed in step S12 in FIG. 2 in the same manner as steps S101 to S108 in FIG. The example of the encoding process illustrated in FIG. 6 is the same as the example of the encoding process illustrated in FIG. 5 except that the encoding process shifts to step S103 instead of step S102 after the execution of step S106. In the example of the encoding process shown in FIG. 6, a slice header is created every time the partial image to be processed is changed. Therefore, a slice header is created every time the target row is changed (shown in FIG. 5). Compared to the example of encoding processing, the amount of encoded data is reduced.

  FIG. 7 shows the decoding processing order and the cache memory status (when the number of image divisions is 2) when decoding the encoded data in the first embodiment. When decoding the encoded data (when the number of image divisions is 2) in the first embodiment, first, the first row of the first row (FIG. 7 (1)) in the partial image P1 of the reference image P Decoding is performed sequentially from the macroblock MB. When the decoding of the macroblock MB of the last column in the first row of the partial image P1 is completed, the second row (FIG. 7 (2)) of the partial image P1 is sequentially decoded from the macroblock MB of the first column. The Thereafter, similarly, the macroblock MB in the third row (FIG. 7 (3)), the fourth row (FIG. 7 (4)),..., The nth row (FIG. 7 (n)) of the partial image P1. Decrypted in order.

  When the decoding of the macroblock MB in the n-th row of the partial image P1 is completed, the macroblock MB in the first row (FIG. 7 (n + 1)) of the partial image P2 of the reference image P is sequentially decoded. When the decoding of the macroblock MB of the last column in the first row of the partial image P2 is completed, the second row of the partial image P2 (FIG. 7 (n + 2)) is sequentially decoded from the macroblock MB of the first column. The Thereafter, similarly, the macroblock MB in the third row (FIG. 7 (n + 3)), the fourth row (FIG. 7 (n + 4)),..., The n-th row (FIG. 7 (n + n)) of the partial image P2 Decrypted in order.

  Assuming that the capacity of the cache memory of the video decoding device (processor) for decoding the encoded data is ½ of the horizontal size of the reference image P, the macroblock MB in the first row of the partial image P1 When the decoding of the macroblock MB in the second row in the partial image P1 is completed and the reference image data in the vicinity of the macroblock MB in the second row of the partial image P1 (shading in FIG. 7) is completed. Since the data corresponding to the portion is present in the cache memory, the number of occurrences of load cache misses is reduced.

  FIG. 8 shows the decoding processing order and the cache memory status (when the number of image divisions is 3) when decoding the encoded data in the first embodiment. When decoding the encoded data (when the number of image divisions is 3) in the first embodiment, first, the first row of the first row (FIG. 8 (1)) in the partial image P1 of the reference image P is displayed. Decoding is performed sequentially from the macroblock MB. When the decoding of the macroblock MB in the last column in the first row of the partial image P1 is completed, the second row (FIG. 8 (2)) in the partial image P1 is sequentially decoded from the macroblock MB in the first column. The Thereafter, similarly, the macroblock MB in the third row (FIG. 8 (3)), the fourth row (FIG. 8 (4)),..., The nth row (FIG. 8 (n)) of the partial image P1. Decrypted in order.

  When the decoding of the macroblock MB in the nth row of the partial image P1 is completed, the macroblock MB in the first row (FIG. 8 (n + 1)) of the partial image P2 of the reference image P is sequentially decoded. When the decoding of the macroblock MB of the last column in the first row of the partial image P2 is completed, the second row of the partial image P2 (FIG. 8 (n + 2)) is sequentially decoded from the macroblock MB of the first column. The Thereafter, similarly, the macroblock MB in the third row (FIG. 8 (n + 3)), the fourth row (FIG. 8 (n + 4)),..., The n-th row (FIG. 8 (n + n)) of the partial image P2 Decrypted in order.

  When the decoding of the macroblock MB in the nth row of the partial image P2 is completed, the macroblock MB in the first row (FIG. 8 (2n + 1)) of the partial image P3 of the reference image P is sequentially decoded. When the decoding of the macroblock MB of the last column in the first row of the partial image P3 is completed, the second row (FIG. 8 (2n + 2)) of the partial image P3 is sequentially decoded from the macroblock MB of the first column. The Thereafter, similarly, the macroblock MB in the third row (FIG. 8 (2n + 3)), the fourth row (FIG. 8 (2n + 4)),..., The nth row (FIG. 8 (2n + n)) of the partial image P3. Decrypted in order.

  Assuming that the capacity of the cache memory of the video decoding device (processor) is 1/3 of the horizontal size of the reference image P, the decoding of the macroblock MB in the first row of the partial image P1 is completed and the partial image When shifting to the decoding of the macroblock MB in the second row in P1, the reference image data (data corresponding to the shaded portion in FIG. 8) in the vicinity of the macroblock MB in the second row of the partial image P1 is cache memory. Therefore, the number of load cache miss occurrences is reduced.

  As described above, in the first embodiment, since the encoding processing order of the encoding unit 12 can be changed according to the number of image divisions set by the image division number setting unit 11, the encoded data (the encoding of the encoding unit 12) The occurrence of a load cache miss can be suppressed even when the capacity of the cache memory used for decoding the conversion result is not sufficiently large with respect to the resolution of the moving image.

  FIG. 9 shows a second embodiment of the present invention. In the description of the second embodiment, the same reference numerals as those used in the first embodiment are used for the same elements as those described in the first embodiment, and detailed description thereof is omitted.

  A video encoding device 20 according to the second embodiment is configured by replacing the image division number setting unit 11 with an image division number setting unit 21 in the video encoding device 10 according to the first embodiment (FIG. 1). The image division number setting unit 21 includes a processor number setting unit 21a. The processor number setting unit 21a sets the number of processors constituting a moving image decoding device (not shown) for decoding encoded data generated by the moving image encoding device 20 (encoding unit 12). To do.

  FIG. 10 shows the operation of the video encoding apparatus in the second embodiment. In the video encoding device 20 having the above-described configuration, the encoding unit 12 is held by the processor number setting unit 21 a of the image division number setting unit 21 in accordance with the reception of input data by the video encoding device 20. The number of existing processors is acquired as the number of image divisions (step S21). Then, as in the first embodiment, the encoding unit 12 divides the encoding target image into the same number of partial images as the number of image divisions, and performs an encoding process using motion compensation for each partial image (step). S22). Even in the second embodiment, the same effect as that of the first embodiment can be obtained.

  FIG. 11 shows a third embodiment of the present invention. In the description of the third embodiment, the same reference numerals as those used in the first embodiment are used for the same elements as those described in the first embodiment, and detailed description thereof is omitted.

  The moving image encoding device 30 of the third embodiment is configured by replacing the image division number setting unit 11 with an image division number setting unit 31 in the moving image encoding device 10 of the first embodiment (FIG. 1). The image division number setting unit 31 includes an image information setting unit 31a, a cache information setting unit 31b, and an image division number calculation unit 31c. The image information setting unit 31a sets information (image size, luminance color difference format, macroblock size, number of reference images, etc.) related to the encoding target image. The cache information setting unit 31b relates to a cache memory of a processor constituting a moving image decoding device (not shown) for decoding encoded data generated by the moving image encoding device 30 (encoding unit 12). Set information (capacity, method, etc.).

Image dividing number calculating unit 31c obtains the information held by the image information setting unit 31a and the cache information setting unit 31b, the image dividing number based on the information acquired from the image information setting unit 31a and the cache information setting unit 31b Is calculated. For example, for the image division number divnum calculated by the image division number calculation unit 31c, when the luminance color difference format is 4: 2: 0 format, the round-up function ceiling (), the horizontal image size hsize, the macroblock vertical size mbvsize, reference This is expressed by equation (1) using the number of images refnum and the cache size (cache memory capacity) csize.
divnum = ceiling ((1.5 x mbvsize x refnum x hsize) / csize) (1)
FIG. 12 shows the operation of the video encoding apparatus in the third embodiment. In the video encoding device 30 having the above-described configuration, the image division number calculation unit 31c receives the information and cache held by the image information setting unit 31a as the input data is received by the video encoding device 30. Information held by the information setting unit 31b is sequentially acquired (steps S31 and S32). Next, the image division number calculation unit 31c calculates the image division number based on the information acquired from the image information setting unit 31a and the cache information setting unit 31b (step S33). Then, the encoding unit 12 acquires the number of image divisions calculated by the image division number calculation unit 31c of the image division number setting unit 31 (step S34). After that, as in the first embodiment, the encoding unit 12 divides the encoding target image into the same number of partial images as the number of image divisions, and performs an encoding process using motion compensation for each partial image ( Step S35 ). Even in the third embodiment, the same effect as in the first embodiment can be obtained.

  FIG. 13 shows a fourth embodiment of the present invention. In describing the fourth embodiment, the same elements as those described in the first to third embodiments are denoted by the same reference numerals as those used in the first to third embodiments. Description is omitted.

  The moving image encoding device 40 of the fourth embodiment is configured by replacing the image division number setting unit 11 with an image division number setting unit 41 in the moving image encoding device 10 of the first embodiment (FIG. 1). The image division number setting unit 41 includes a processor number setting unit 21a (second embodiment (FIG. 9)), an image information setting unit 31a and a cache information setting unit 31b (third embodiment (FIG. 11)), and an image division. And a number calculation unit 41a.

The image division number calculating unit 41a acquires information held by the processor number setting unit 21a, the image information setting unit 31a, and the cache information setting unit 31b, and the processor number setting unit 21a, the image information setting unit 31a, and the cache information setting unit. The number of image divisions is calculated based on the information acquired from the unit 31b. For example, for the image division number divnum calculated by the image division number calculation unit 41a, when the luminance color difference format is 4: 2: 0 format, the round-up function ceiling (), the horizontal image size hsize, the macroblock vertical size mbvsize, reference It is expressed by equation (2) using the number of images refnum, the cache size csize, and the number of processors pnum.
divnum = ceiling ((1.5 × mbvsize × refnum × hsize / pnum) / csize) × pnum (2)
FIG. 14 shows the operation of the video encoding apparatus in the fourth embodiment. In the moving image encoding device 40 having the above-described configuration, the image division number calculating unit 41a receives information and images held by the processor number setting unit 21a in accordance with the reception of input data by the moving image encoding device 40. The information held by the information setting unit 31a and the information held by the cache information setting unit 31b are sequentially acquired (steps S41, S42, S43). Next, the image division number calculation unit 41a calculates the image division number based on the information acquired from the processor number setting unit 21a, the image information setting unit 31a, and the cache information setting unit 31b (step S44). Then, the encoding unit 12 acquires the number of image divisions calculated by the image division number calculation unit 41a of the image division number setting unit 41 (step S45). After that, as in the first embodiment, the encoding unit 12 divides the encoding target image into the same number of partial images as the number of image divisions, and performs an encoding process using motion compensation for each partial image ( Step S46). Even in the fourth embodiment, the same effect as that of the first embodiment can be obtained.

  In the third embodiment (FIG. 12), an example in which the image division number calculation unit 31c acquires information from the cache information setting unit 31b after acquiring information from the image information setting unit 31a has been described. It is not limited to the embodiment, and it goes without saying that the image division number calculation unit 31c may acquire information from the image information setting unit 31a after acquiring information from the cache information setting unit 31b.

  Similarly, in the fourth embodiment (FIG. 14), the image division number calculation unit 41a acquires information from the image information setting unit 31a after acquiring information from the processor number setting unit 21a, and receives information from the image information setting unit 31a. However, the present invention is not limited to such an embodiment, and the image division number calculation unit 41a includes the processor number setting unit 21a and the image information setting unit. Needless to say, the order of obtaining information from the unit 31a and the cache information setting unit 31b may be changed.

Regarding the above embodiment, the following additional notes are disclosed.
(Appendix 1)
An image division number setting unit for setting the number of image divisions;
A moving image comprising: an encoding unit that divides an encoding target image constituting a moving image into the same number of partial images as the number of image divisions, and performs an encoding process using motion compensation for each partial image. Image encoding device.
(Appendix 2)
In the moving image encoding device according to attachment 1,
The moving picture encoding apparatus, wherein the image division number setting unit sets the number of processors used when decoding the encoding result of the encoding unit to the image division number.
(Appendix 3)
In the moving image encoding device according to attachment 1,
The image division number setting unit includes:
An image information setting unit for setting information on the encoding target image;
A cache information setting unit that sets information about a cache memory used when decoding the encoding result of the encoding unit;
A moving picture encoding apparatus comprising: an image division number calculating unit that calculates the image division number based on information set by the image information setting unit and the cache information setting unit.
(Appendix 4)
In the moving image encoding device according to attachment 1,
The image division number setting unit includes:
A processor number setting unit for setting the number of processors used when decoding the encoding result of the encoding unit;
An image information setting unit for setting information on the encoding target image;
A cache information setting unit that sets information about a cache memory used when decoding the encoding result of the encoding unit;
A moving picture coding apparatus comprising: an image division number calculation unit that calculates the image division number based on information set by the processor number setting unit, the image information setting unit, and the cache information setting unit .
(Appendix 5)
In the moving image encoding device according to attachment 1,
The partial image includes a first partial image and a second partial image,
The encoded data generated by the encoding process has a structure in which encoded data of the first partial image is followed by encoded data of the second partial image.
(Appendix 6)
In the moving image encoding device according to attachment 1,
The partial image includes a first partial image and a second partial image,
The moving image encoding apparatus, wherein the encoding unit performs the encoding process of the second partial image after performing the encoding process of the first partial image.
(Appendix 7)
An image division number setting step for setting the image division number;
A moving image comprising: an encoding step of dividing an encoding target image constituting a moving image into the same number of partial images as the number of image divisions, and performing an encoding process using motion compensation for each partial image. Image coding method.
(Appendix 8)
In the moving image encoding method according to attachment 7,
In the image division number setting step, the number of processors used when decoding the encoding result of the encoding step is set to the image division number.
(Appendix 9)
In the moving image encoding method according to attachment 7,
The image division number setting step includes:
An image information setting step for setting information on the encoding target image;
A cache information setting step for setting information relating to the cache memory used when decoding the encoding result of the encoding step;
A moving picture encoding method comprising: an image division number calculating step of calculating the image division number based on information set by the image information setting step and the cache information setting step.
(Appendix 10)
In the moving image encoding method according to attachment 7,
The image division number setting step includes:
A processor number setting step of setting the number of processors used when decoding the encoding result of the encoding step;
An image information setting step for setting information on the encoding target image;
A cache information setting step for setting information relating to the cache memory used when decoding the encoding result of the encoding step;
A moving picture encoding method comprising: an image division number calculating step for calculating the image division number based on information set by the processor number setting step, the image information setting step, and the cache information setting step. .
(Appendix 11)
In the moving image encoding method according to attachment 7,
The partial image includes a first partial image and a second partial image,
The encoded image data generated by the encoding process has a structure in which encoded data of the first partial image is followed by encoded data of the second partial image.
(Appendix 12)
In the moving image encoding method according to attachment 7,
The partial image includes a first partial image and a second partial image,
In the encoding step, the encoding process for the second partial image is performed after the encoding process for the first partial image is performed.

  As mentioned above, although this invention was demonstrated in detail, the above-mentioned embodiment and its modification are only examples of this invention, and this invention is not limited to these. Obviously, modifications can be made without departing from the scope of the present invention.

  The present invention is useful when applied to a moving picture coding apparatus that performs coding processing using motion compensation.

1 is a block diagram showing a first embodiment of the present invention. It is a flowchart which shows operation | movement of the moving image encoder in 1st Embodiment. It is a conceptual diagram which shows the encoding process order in 1st Embodiment, and the structure of encoding data (when the number of image divisions is 2). It is a conceptual diagram which shows the encoding process order in 1st Embodiment, and the structure of encoded data (when the number of image divisions is 3). It is a flowchart which shows an example of the encoding process in 1st Embodiment. It is a flowchart which shows another example of the encoding process in 1st Embodiment. It is a conceptual diagram which shows the decoding process order at the time of decoding the encoding data in 1st Embodiment, and the condition of a cache memory (when the number of image divisions is 2). It is a conceptual diagram which shows the decoding process order at the time of decoding the encoding data in 1st Embodiment, and the condition of a cache memory (when the number of image divisions is 3). It is a block diagram which shows 2nd Embodiment of this invention. It is a flowchart which shows operation | movement of the moving image encoder in 2nd Embodiment. It is a block diagram which shows 3rd Embodiment of this invention. It is a flowchart which shows operation | movement of the moving image encoder in 3rd Embodiment. It is a block diagram which shows 4th Embodiment of this invention. It is a flowchart which shows operation | movement of the moving image encoder in 4th Embodiment. It is a conceptual diagram which shows the decoding process order at the time of decoding the encoding data in a prior art, and the condition of a cache memory.

10, 20, 30, 40... Video encoding device; 11, 21, 31, 41... Image division number setting unit; 12 .. encoding unit; 21a .. processor number setting unit; Cache information setting unit; 31c, 41a... Image division number calculating unit

Claims (6)

An image division number setting unit for setting the number of image divisions;
An encoding unit that divides an encoding target image constituting a moving image into the same number of partial images as the number of image divisions, and performs an encoding process using motion compensation for each partial image ;
The image division number setting unit includes:
An image information setting unit for setting the image size, luminance color difference format, macroblock size, or reference image number of the encoding target image;
A cache information setting unit for setting a capacity of a cache memory used when decoding an encoding result of the encoding unit, or a cache method;
A moving picture encoding apparatus comprising: an image division number calculating unit that calculates the image division number based on information set by the image information setting unit and the cache information setting unit . The moving image encoding device according to claim 1,
The image division number setting unit further includes a processor number setting unit that sets the number of processors used when decoding the encoding result of the encoding unit,
The image division number calculating unit calculates the image division number based on information set by the processor number setting unit, the image information setting unit, and the cache information setting unit. . The moving image encoding device according to claim 1,
The partial image includes a first partial image and a second partial image,
The encoded data generated by the encoding process has a structure in which encoded data of the first partial image is followed by encoded data of the second partial image . The moving image encoding device according to claim 1,
The partial image includes a first partial image and a second partial image,
The moving image encoding apparatus , wherein the encoding unit performs the encoding process of the second partial image after performing the encoding process of the first partial image . An image division number setting step for setting the image division number;
An encoding step of dividing an encoding target image constituting a moving image into the same number of partial images as the number of image divisions, and performing an encoding process using motion compensation for each partial image,
The image division number setting step includes:
An image information setting step for setting the image size, luminance color difference format, macroblock size, or reference image number of the encoding target image;
A cache information setting step for setting a cache memory capacity or a cache method used when decoding the encoding result of the encoding step;
A moving picture encoding method comprising: an image division number calculating step of calculating the image division number based on information set by the image information setting step and the cache information setting step . In the moving image encoding method according to claim 5 ,
The image division number setting step further includes a processor number setting step for setting the number of processors used when decoding the encoding result of the encoding step,
Wherein the image dividing number calculating process, the processor number setting process, the image information setting step and the moving picture coding method and calculating the dividing number of image based on the information set by the cache information setting step .

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