JP4900879B2 - MRAM and method of operating the same - Google Patents

Abstract

An MRAM is formed by a plurality of symbols. Each of the symbols is formed by a plurality of bits. The MRAM uses an error correction code capable of error correction in a symbol unit for error detection and error correction. The MRAM includes: a first data cell for storing some bits of a data symbol among the symbols; and a peripheral circuit for reproducing the data symbol by adding a predetermined dummy bit to the some bits and performing error detection and error correction by using the reproduced data symbol.

Description

  The present invention relates to a magnetic random access memory (MRAM), and more particularly to an MRAM in which the efficiency of a burst error correction code is improved.

  The MRAM is a nonvolatile memory capable of high-speed writing / reading, and research and development for practical use has been actively conducted in recent years.

  Most typically, an MRAM includes a magnetoresistive element composed of a magnetization free layer in which magnetization can be reversed, a magnetization fixed layer in which magnetization is fixed, and a nonmagnetic layer interposed therebetween. Use as Data is stored as the magnetization direction of the magnetization free layer. When the nonmagnetic layer is made of an extremely thin insulator, the magnetoresistive element exhibits a TMR (tunnel magnetoresistance) effect, and the magnetoresistive element thus configured is often called an MTJ (magnetic tunnel junction) element. . On the other hand, when the nonmagnetic layer is made of a nonmagnetic conductor, the magnetoresistive element exhibits a GMR (giant magnetoresistance) effect, and the thus configured magnetoresistive element is a CPP-GMR (current perpendicular). to-plane giant magnetoresistive) element.

Data writing is most commonly performed by applying a magnetic field to the magnetization free layer by passing a write current through a word line and a bit line provided in the vicinity of the memory cell. This is done by flipping in the direction.
On the other hand, the magnetoresistive effect exhibited by the magnetoresistive element is used for reading data. Regardless of whether the TMR effect or the GMR effect is used, the resistance of the memory cell changes depending on the magnetization direction of the magnetization free layer. This change in resistance of the memory cell appears as a change in current flowing through the memory cell or a voltage drop generated in the memory cell. Data of the memory cell is determined by detecting a change in the current flowing through the memory cell or a voltage drop generated in the memory cell.

  In order to determine the data in the memory cell, a reference cell in which prescribed data is written in advance is often used. Hereinafter, in order to distinguish from the reference cell, a cell actually used for storing data among the memory cells may be referred to as a data cell. In an MRAM provided with a reference cell, data in a data cell is determined by generating a reference signal using the reference cell and comparing the data signal obtained from the data cell with the reference signal. Most typically, a pair of reference cells is used to generate a reference signal. Data “1” is written in one reference cell, and data “0” is written in the other reference cell. When a predetermined voltage or a predetermined current is supplied to the two reference cells, two signals having different signal levels are obtained. From these two signals, a signal having their average level is generated and used as a reference signal.

  As is well known to those skilled in the art, one problem with MRAM is the selectivity of memory cells in a write operation. In a conventional MRAM, data can be written to a half-selected memory cell, that is, a memory cell in which a write current is supplied only to one of a corresponding word line and bit line due to variations in characteristics of the memory cell. This undesirably reduces the reliability of the operation of the MRAM.

  One method for improving the selectivity of the write operation of the MRAM is a toggle write method (see US Pat. No. 6,545,906). The toggle writing method is a technique for performing a writing operation with high selectivity by using SAF (synthetic antiferromagnet) for the magnetization free layer; where SAF is an adjacent structure composed of a plurality of ferromagnetic layers. This is a structure in which the ferromagnetic layers to be coupled are magnetically antiferromagnetically coupled.

  FIG. 1 is a plan view showing a typical configuration of an MRAM employing a toggle writing method. In the memory array of the MRAM, a bit line 102 and a word line 103 orthogonal to the bit line 102 are extended. A magnetoresistive element 101 used as a memory cell intersects the bit line 102 and the word line 103. It is provided at each of the positions. As shown in FIG. 2, the magnetoresistive element 101 is composed of a magnetoresistive element including an antiferromagnetic layer 111, a magnetization fixed layer 112, a barrier layer 113, and a magnetization free layer 114. Returning to FIG. 1, the magnetoresistive element 101 is arranged so that the easy axes of the magnetization fixed layer 112 and the magnetization free layer 114 form an angle of 45 ° with the bit line 102 and the word line 103, that is, the longitudinal direction of the magnetoresistive element 101. Are arranged at an angle of 45 ° with the bit line 102 and the word line 103. Referring to FIG. 2 again, the magnetization free layer 114 includes ferromagnetic layers 121 and 122 and a nonmagnetic layer 123 interposed therebetween. The overall residual magnetization of the magnetization free layer 114 (that is, the magnetization of the entire magnetization free layer 114 when the external magnetic field is 0) is as close to 0 as possible. This is important for SAF to develop a spin flop. This condition can be satisfied, for example, by forming the two ferromagnetic layers 121 and 122 with the same material and the same film thickness.

  3A to 3E are conceptual diagrams for explaining the procedure of the toggle writing method. FIGS. 4A and 4B show waveforms of currents flowing through the bit line 102 and the word line 103 when data writing is performed by toggle writing. FIG. It should be noted in FIG. 3 that the magnetizations of the ferromagnetic layers 121 and 122 of the magnetization free layer 114 are referred to by symbols M1 and M2, respectively.

  Data writing by the toggle writing method is performed by rotating the direction of the magnetic field applied to the magnetization free layer 114 in the plane and inverting the magnetization of the ferromagnetic layers 121 and 122 constituting the magnetization free layer 114 by this magnetic field. Is called. Specifically, first, a write current is supplied to the word line 103, whereby a magnetic field HWL is generated in a direction perpendicular to the word line 103 (time t1). Subsequently, the write current is supplied to the bit line 102 while the write current is supplied to the word line 103 (time t2). As a result, a magnetic field HWL + HBL is generated in a direction that forms an angle of 45 ° with both the word line 103 and the bit line 102. Subsequently, the supply of the write current to the word line 103 is stopped while the write current is supplied to the bit line 102 (time t3). As a result, a magnetic field HBL is generated in a direction perpendicular to the bit line 102 (that is, a direction parallel to the word line 103). By applying a write current to the word line 103 and the bit line 102 in such a procedure, the magnetic field applied to the magnetization free layer 114 is rotated, whereby the ferromagnetic layers 121 and 122 constituting the magnetization free layer 114 are rotated. Can be rotated 180 °.

  It should be noted that the data writing by the toggle writing method can only reverse the magnetization, that is, the data. For example, when data “0” is to be written in a certain target memory cell, data is first read from the target memory cell. Only when the read data is “1”, toggle writing is performed on the target memory cell, and data “0” is stored in the target memory cell. When the read data is “0”, writing to the target memory cell is not performed.

  Like many other memory devices, MRAM inevitably encounters memory cell data errors. For example, it is unavoidable that a write error in which desired data is not written in a write operation or a soft error caused by a thermal disturbance, that is, an undesirable reversal of magnetization due to a thermal disturbance occurs stochastically. In order to deal with such data errors, it is desirable to employ error correction in the MRAM as well as in many other memory devices. For example, as disclosed in JP2003-68096A, JP2003-115195A, JP2003-115197A, JP2005-56556A, and JP2005-85464A, In an MRAM that employs error correction, error correction encoding is performed on write data when data is written, and the error correction encoded data is written to the memory array. At the time of data reading, a syndrome is calculated from the data read from the memory array, and when a data error is found, the corrected data is output to the outside. At this time, the data stored in the memory array is also corrected.

  One useful error correction code is a burst error correction code in which one block is composed of a plurality of symbols, each symbol is composed of a plurality of bits, and error correction in symbol units is possible. The Reed-Solomon code and the Fire code are a kind of such a burst error correction code. The usefulness of the burst error correction code in MRAM is that it enables error correction when a data error occurs in a reference cell. When a data error occurs in the reference cell, a burst error often occurs in the read data. If a burst error correction code is employed, there is a high possibility that read data can be corrected correctly even if a data error occurs in the reference cell.

One problem in using burst error correction codes for memory array error correction is that the code structure may not fit the number of inputs and outputs of the MRAM. Considering the MRAM architecture, it is preferable that the number of external input and output pins are ^the 2 ^n. For example, an external interface of a typical MRAM has 16 (= 2 ⁴ ) input / output pins DQ0 to DQ15. However, in the known burst error correction encoding scheme, the code construction, a situation that is not suitable for MRAM number of external input and output pins are ^the 2 ⁿ may occur. Hereinafter, a Reed-Solomon code will be described as an example.

In the known Reed-Solomon coding, one block is composed of data symbols and parity symbols. A data symbol is a symbol that includes data that is actually used, and a parity symbol is a symbol that is used for error detection and error correction. When one symbol is composed of M bits, the maximum allowable number of data symbols included in one block is 2 ^M −1 . For example, when one symbol is composed of 4 bits, one block can be configured to include a maximum of 15 data symbols. A Reed-Solomon code in which the total number of symbols included in one block is J and the number of data symbols is K is referred to as a (J, K) Reed-Solomon code.

  The number of parity symbols included in one block affects the error correction capability. In the Reed-Solomon code, one block needs to include 2t parity symbols in order to enable error correction of t symbols of symbols included in one block.

It is critical in MRAM design that the maximum number of data symbols contained in a block is reduced by 2 ^M to 1. In order to simplify the architecture of the MRAM, it is preferable to assign each data symbol of one block to each input / output pin of the MRAM. However, in order to the number of external input and output pins to ^the 2 ⁿ is must wastefully increasing the number of bits included in one symbol. That is, in the Reed-Solomon code, for the maximum number of data symbols in the case where one symbol is composed of n bits is less by only one from 2 ^n, the one the 2 ⁿ input and output pins of the MRAM block In order to assign to each of 2 ⁿ data symbols, one symbol needs to be composed of (n + 1) bits. This is undesirable because it reduces the efficiency of the code structure. This is especially critical for implementing an MRAM with 16 input / output pins. Obviously, the fact that the number of bits contained in one symbol is a number represented by a power of 2 facilitates MRAM address assignment. For example, it is preferable that the number of bits included in one symbol is 4 in order to facilitate address allocation. However, the problem is that when one symbol is composed of 4 bits, the maximum number of data symbols included in one block is 15. If one symbol is composed of 4 bits, the number of data symbols is insufficient by one to realize an MRAM having 16 input / output pins. Therefore, in a general Reed-Solomon encoding method, in order to realize an MRAM having 16 input / output pins, it is necessary to configure one symbol with 5 bits. This is not preferable because it reduces the efficiency of the code structure and complicates the address assignment.

  From such a background, it is desired to provide a technique for adapting the code configuration of the error correction code to the number of inputs and outputs of the MRAM. In particular, it is desired to provide a technique for realizing an MRAM having 16 input / output pins while one symbol is substantially composed of 4 bits.

  An object of the present invention is to provide a technique for adapting the code configuration of a burst error correcting code to the number of inputs and outputs of an MRAM, thereby improving the efficiency of the code configuration.

In one aspect, the MRAM according to the present invention is composed of a plurality of symbols, each symbol is composed of a plurality of bits, and an error correction code capable of error correction in symbol units is used for error detection and error correction. MRAM. The MRAM reads out a part of bits of a data symbol of the symbol, reads the part of the bit from the first data cell, and adds a predetermined dummy bit to the part of the bit. And a peripheral circuit for reproducing the data symbol and performing error detection and error correction using the reproduced data symbol.
The MRAM further includes a second data cell that stores some bits of a parity symbol of the symbols, and a first reference cell and a second reference cell that are selected simultaneously with the first data cell during a read operation. It comprises. In this case, the second reference cell is used for storing a residual bit of the parity symbol and generating a reference signal used for reading data from a data cell different from the first data cell; The first reference cell may be used to generate a reference signal used for reading data from the first data cell and the second reference cell.
The second reference cell includes a first cell and a second cell that store complementary data. In this case, it is preferable that the predetermined dummy bit is determined so that the remaining bits stored in the first memory cell and the second memory cell are complementary to each other.
Preferably, when the peripheral circuit detects a data error in both the data symbol read from the first data cell and the residual bit read from the second reference cell, the peripheral circuit Correct the data stored in. In this case, when the peripheral circuit detects a data error in the data symbol read from the first data cell and does not detect a data error in the remaining bits read from the second reference cell, Preferably, the data stored in the first data cell is corrected. The peripheral circuit detects a data error in the remaining bits read from the second reference cell, and detects no data error in the data symbol read from the first memory cell. Preferably, the remaining bits stored in the second reference cell are corrected.

In another aspect, the MRAM according to the present invention generates a data symbol by adding a plurality of data cells and a predetermined dummy bit to the write data, calculates a parity symbol using the generated data symbol, A peripheral circuit for writing only the bit corresponding to the write data in the data symbol to the first data cell of the plurality of data cells.
The MRAM further includes a first reference cell and a second reference cell that are selected simultaneously with the first data cell during a read operation. In this case, the peripheral circuit writes some bits of the parity symbol to a second data cell of the plurality of data cells, and writes the remaining bits of the parity symbol to the second reference cell. One reference cell is used to generate a reference signal used to read data from the first data cell and the second reference cell.
When the second reference cell includes a first cell and a second cell that store complementary data, the predetermined dummy bit is the remaining bit stored in the first cell and the second cell. Are preferably determined to be complementary to each other.

In still another aspect, the MRAM according to the present invention includes a first data cell used for storing a bit of a data symbol of the plurality of symbols, and a part of a parity symbol of the plurality of symbols. A second data cell used to store bits, a first reference cell used to generate a reference signal used to read data from the first data cell, and the first data cell. And a second reference cell used for generating a reference signal used for reading data from another data cell. The second reference cell is used to store the remaining bits of the parity symbol.
Preferably, the first reference cell is used to generate a reference signal used for reading data from the second reference cell as well as the first data cell.
It is preferable that only a part of the data symbols is stored in the first data cell. In this case, the peripheral circuit of the MRAM reproduces the data symbol by adding a predetermined dummy bit to the partial bit, and reads the parity symbol from the second data cell and the second reference cell, It is preferable to perform error detection and error correction using the reproduced data symbol and the read parity symbol.

  According to the present invention, the code configuration of a burst error correction code can be adapted to the number of inputs and outputs of the MRAM, thereby improving the efficiency of the code configuration.

FIG. 1 is a plan view showing a configuration of a conventional MRAM corresponding to toggle writing. FIG. 2 is a cross-sectional view showing a configuration of a conventional MRAM corresponding to toggle writing. 3A to 3E are conceptual diagrams showing the procedure of toggle writing. 4A and 4B are timing charts showing waveforms of write currents that flow through the word lines and bit lines in toggle writing. FIG. 5 is a block diagram showing the configuration of the MRAM according to one embodiment of the present invention. FIG. 6 is a block diagram showing a configuration of an MRAM data array and sense amplifier circuit according to an embodiment of the present invention. FIG. 7 is a conceptual diagram showing the configuration of an MRAM data array according to an embodiment of the present invention. FIG. 8 is a block diagram showing another configuration of the data array and parity array of the MRAM according to one embodiment of the present invention. FIG. 9A is a diagram illustrating a code configuration of an MRAM according to an embodiment of the present invention. FIG. 9B is a diagram illustrating a code configuration of the MRAM according to an embodiment of the present invention. FIG. 10 is a flowchart illustrating the read operation of the MRAM according to one embodiment of the present invention. FIG. 11A is a conceptual diagram illustrating the error correction operation of the MRAM according to one embodiment of the present invention. FIG. 11B is a conceptual diagram illustrating the error correction operation of the MRAM according to one embodiment of the present invention. FIG. 11C is a conceptual diagram illustrating the error correction operation of the MRAM according to one embodiment of the present invention. FIG. 12 is a flowchart illustrating the write operation of the MRAM according to one embodiment of the present invention.

Hereinafter, a magnetic random access memory (MRAM) according to the present invention will be described in detail with reference to the accompanying drawings.
In the MRAM of the present invention, data stored in the memory array is encoded using the (18, 16) Reed-Solomon code. That is, in the embodiment of the present invention, the number of data symbols included in one block is 16 and the number of parity symbols is 2. This means that error correction of one symbol out of 18 symbols included in one block is possible.
As described above, in order to reduce the number of data symbols to 16, the number of bits included in one symbol must be 5 in the known Reed-Solomon encoding method. However, in this embodiment, by adopting the following code configuration, the incompatibility between the code configuration of the error correction code and the number of inputs and outputs of the MRAM is eliminated:
(1) 4 bits out of 5 bits constituting each data symbol and parity symbol are stored in a data cell of the memory array.
(2) A predetermined value is used as the remaining 1 bit of each data symbol and is not stored in the data cell.
(3) The remaining 1 bit of each parity symbol is stored in the reference cell.
As a result, an MRAM having 16 inputs / outputs is realized while the number of bits included in one data symbol is substantially four. The MRAM according to the embodiment of the present invention will be described in detail below.

FIG. 5 is a block diagram showing the configuration of the MRAM 10 according to one embodiment of the present invention. The MRAM 10 includes a plurality of memory arrays in which memory cells configured by magnetoresistive elements are arranged in a matrix.
There are two types of memory arrays of the MRAM 10, data arrays 1 ₀ to 1 ₁₅ and parity arrays 2 ₀ and 2 ₁ . In the following description, the data arrays 1 ₀ to 1 ₁₅ are collectively referred to as the data array 1 and the parity arrays 2 ₀ and 2 ₁ are referred to as the parity array 2 when they are not distinguished from each other. Data array 1 is used to store data symbols and parity array 2 is used to store parity symbols. Data arrays 1 ₀ to ₁₇ are respectively associated with data inputs / outputs DQ ₀ to DQ 15 of the MRAM 10. At the time of data writing, information symbols are formed from the write data input to the data input / outputs DQ0 to DQ15 and stored in the data arrays 1 ₀ to 1 ₁₅ , while parity symbols are generated from the information symbols to generate the parity array 2 _0. 2 is stored in ₁ .

  Access to the data array 1 and the parity array 2 is performed using peripheral circuits, specifically, a row decoder 3, a column decoder 4, a write circuit 5, a sense amplifier (SA) circuit 6, and a controller 7. Done. The row decoder 3 and the column decoder 4 are used for selecting a memory cell to be accessed. The write circuit 5 generates a write current used for writing data to the selected memory cell. In the present embodiment, data writing is performed by the above-described toggle writing. The sense amplifier circuit 6 is used for identifying data stored in the memory cell. The controller 7 has a function of controlling the row decoder 3, the column decoder 4, the write circuit 5, and the sense amplifier circuit 6. The controller 7 further has a function of performing various operations for error correction, such as Reed-Solomon coding and error detection.

Figure 6 is a block diagram showing a detailed configuration of the sense amplifier circuit 6 provided corresponding to the data array 1 ₀ and the data array 1 ₀ of the present embodiment. The memory cells arranged in the data array 1 _0, there are two types of data cell 11 and the reference cell 12. As shown in FIG. 7, the data cell 11 and the reference cell 12 are arranged at a position where the word line 13 and the bit line 14 intersect. The word line 13 is selected according to the X address, and the bit line 14 is selected according to the Y address.
Returning to FIG. 6, the data array _{1 0} has two areas 15A, is divided into 15B. The area 15A is an area used for storing even-numbered Y address data, and the area 15B is an area used for storing odd-numbered Y address data. A row of one memory cell is designated by one X address, whereas a column of four data cells 11 is designated by one Y address. That is, when a set of X address and Y address is designated, four data cells 11 located in the same row are selected. As will be described later, these four data cells 11 are used for storing one data symbol.

  In the description of this embodiment, a Q address may be used to distinguish the columns of the data cells 11. The addresses Q0 to Q3 correspond to the Y address “0”, and the addresses Q4 to Q7 correspond to the Y address “1”. Further, the addresses Q8 to Q11 correspond to the Y address “2”, and the addresses Q12 to Q15 correspond to the Y address “3”. The same applies to other Q addresses.

  Two columns of reference cells 12 are provided in each of the areas 15A and 15B. The reference cell provided in the area 15A is hereinafter referred to as a reference cell 12A, and the reference cell 12 provided in the area 15B is referred to as a reference cell 12B. Complementary data is written in the two reference cells 12A located in the same memory cell row (that is, connected to the same word line 13). When data is read from the data cell 11 located in the area 15A, a current is passed through the two reference cells 12A located in the same row as the data cell 11, and a reference signal is generated from these currents. This reference signal is generated so as to have a signal level corresponding to the middle of the signal level corresponding to the data “1” and the signal level corresponding to the data “0”. By comparing the reference signal and a data signal generated when a current flows through the data cell 11, the data of the data cell 11 is determined.

The two reference cells 12A located in the same memory cell row need only store data complementary to each other, and data “1” and “0” are recorded in any of the two reference cells 12A. Note that it is also good. If the difference between the characteristics of the two reference cells 12A is sufficiently small, data reading is not affected even if data “1” and “0” are recorded in any of the two reference cells 12A. That is, the two reference cells 12A are allowed to take either a state of storing data “1” and “0” and a state of storing data “0” and “1”, respectively.
Similarly, complementary data is written in two reference cells 12B located in the same memory cell row (that is, connected to the same word line 13). When reading data from the data cell 11 located in the area 15B, two reference cells 12B located in the same row as the data cell 11 are used.

  The sense amplifier circuit 6 includes two 4-bit sense amplifiers 16A and 16B and two 2-bit sense amplifiers 17A and 17B. The 4-bit sense amplifier 16A is used for identifying data stored in the data cell 11 located in the area 15A. Specifically, the 4-bit sense amplifier 16A generates a reference signal from the signal received from the reference cell 12A located in the area 15A, and is stored in the data cell 11 located in the area 15A using the reference signal. Identify the data. Similarly, the 4-bit sense amplifier 16B is used for identifying data stored in the data cell 11 located in the area 15B.

  On the other hand, the 2-bit sense amplifiers 17A and 17B are used for identifying data stored in the reference cells 12A and 12B. As will be described later, unlike a general MRAM, the reference cells 12A and 12B are not simply used for generating a reference signal. The reference cells 12A and 12B are used for storing a part of the bits of the parity symbol together with the generation of the reference signal. The 2-bit sense amplifier 17A generates a reference signal from the signal received from the reference cell 12B located in the area 15B, and identifies data of the reference cell 12A located in the area 15A using the reference signal. Similarly, the 2-bit sense amplifier 17B generates a reference signal from the signal received from the reference cell 12A located in the area 15A, and identifies the data of the reference cell 12B located in the area 15B using the reference signal.

In one embodiment, the other data arrays 1 ₁ to 1 ₁₅ and the parity arrays 2 ₀ and 2 ₁ , and the sense amplifier circuit 6 provided corresponding to them also have the configuration shown in FIG . However, the other data arrays 1 ₁ to 1 ₁₅ and parity arrays 2 ₀ , 2 ₁ are, as shown in FIG. 8, data cells 11 arranged in a matrix and reference cells 12 arranged in two columns. It is also possible to consist of In this case, the sense amplifier circuit 6 is composed of a 4-bit sense amplifier. Similarly to the data array 10, a row of memory cells is selected by one X address, and four columns of memory cells are selected by one Y address. That is, when a set of X address and Y address is designated, four data cells 11 and two reference cells 12 located in the same row are selected. The 4-bit sense amplifier generates a reference signal using signals supplied from the two reference cells 12 located in the row of the selected memory cell, and identifies data in the data cell 11 using the reference signal. .

  Next, data allocation in the present embodiment will be described. In this embodiment, one set of X address and Y address corresponds to one block. That is, when an X address and a Y address are specified at the time of access, access to one block corresponding to the X address and the Y address is performed.

  9A and 9B are conceptual diagrams showing a code configuration of a burst error correction code in the present embodiment. FIG. 9A illustrates the code configuration of a block corresponding to an even-numbered Y address by taking a Y address “0” as an example, and FIG. 9B illustrates the code configuration of a block corresponding to an odd-numbered Y address to a Y-address “1”. Is shown as an example.

As shown in FIGS. 9A and 9B, each block is composed of 16 data symbols and two parity symbols. The 16 data symbols are respectively associated with the inputs / outputs DQ0 to DQ15 of the MRAM 10, that is, the data arrays 1 ₀ to 1 ₁₅ respectively. Hereinafter, the data symbols associated with the inputs / outputs DQ0 to DQ15 may be referred to as data symbols DQ0 to DQ15, respectively. Further, the two parity symbols are associated with the parity arrays 2 ₀ and 2 ₁ , respectively. Hereinafter, the parity symbols associated with the parity arrays 2 ₀ and 2 ₁ may be referred to as parity symbols P0 and P1, respectively.

Data arrays 1 ₀ to 1 ₁₅ are used to store data symbols DQ0 to DQ15, respectively. However, all the bits of the data symbol DQ0~DQ15 is not being stored in the data array _{1 0-1 15.} The upper 4 bits of the 5 bits constituting each of data symbols DQ0 to DQ15 are stored in data arrays 1 ₀ to 1 ₁₅ , respectively. The remaining lower 1 bits are fixed to a predetermined value and are not actually stored in the data arrays 1 ₀ to 1 ₁₅ . The bits of the data symbols DQ0 to DQ15 that are not actually stored in the data arrays 1 ₀ to 1 ₁₅ are hereinafter referred to as dummy bits.

Similarly, the parity arrays 2 ₀ and 2 ₁ are used to store parity symbols P0 and P1, respectively. However, all bits of the parity symbols P0 and P1 are not stored in the parity arrays 2 ₀ and 2 ₁ . Of the 5 bits constituting the parity symbols P0 and P1, 4 bits are stored in the parity arrays 2 ₀ and 2 ₁ , respectively. The remaining 1 bit data array 1 ₀ of the reference cell 12A, is stored in 12B. The remaining 1 bit that is not stored in the parity arrays 2 ₀ and 2 ₁ will be referred to as a remaining bit below. More specifically, the remaining bits of the parity symbols P0, P1 of the block corresponding to the even Y address with certain X address, the reference cell 12B which is located in the row of memory cells corresponding to the X address of the data array 1 ₀ Remembered. In FIG. 6 and FIG. 9A, the remaining bits stored in the reference cell 12B are referred to as Qref0. On the other hand, the remaining bits of the parity symbols P0, P1 of the odd Y address block of a X address is stored in the reference cells 12A, located in a row of memory cells corresponding to the X address of the data array 1 _0. 6 and 9B, the remaining bits stored in the reference cell 12A are referred to as Qref1.

  As described above, two reference cells 12A corresponding to the same X address must have one data “1” and the other data “0”, and 2 corresponding to the same X address. The same applies to the two reference cells 12B. Therefore, substantially one bit of data can be stored in two reference cells 12A (or two reference cells 12B). In this case, it may be considered that the remaining bits of the two parity symbols P0 and P1 cannot be stored.

However, such a problem can be avoided by appropriately determining dummy bits of the data symbols DQ0 to DQ15. Specifically, by setting the odd number of dummy bits of the data symbols DQ0 to DQ15 to “1”, the remaining bits of the two parity symbols P0 and P1 are set to “1” and “0”, respectively. It can be limited to a combination or a combination of “0” and “1”. This is because, when the values of the data symbols DQ0 to DQ15 are D0 to D15 and the values of the parity symbols P0 and P1 are P0 and P1, respectively, the following formula is established in the Reed-Solomon code:
D0 + D1 + D2 + ... + D15 + P0 + P1 = 0
Note that D0 to D15 and P0 and P1 are elements of the Galois field GF ( 2 ⁵ ), and the addition is defined as an operation on the Galois field GF ( 2 ⁵ ). The above equation means that if the odd number of the least significant bits of the data symbols DQ0 to DQ15 is 1, one of the parity symbols P0 and P1 must be “0” and the other must be “1”. ing. This means that the remaining bits of the two parity symbols P0 and P1 can be stored in two reference cells 12A (or two reference cells 12B) in which one stores data “1” and the other stores data “0”. Yes.

Hereinafter, a read operation and a write operation corresponding to the code configuration illustrated in FIGS. 9A and 9B will be described.
(Read operation)
Referring to FIG. 10, in the read operation, first, the data symbols and parity symbol data of the block corresponding to the selected X address and Y address are read from parity arrays 2 ₀ and 2 ₁ (step S01).
More specifically, when the read operation is started, four data selected by the set of the selected X address and Y address in each of the data arrays 1 ₀ to 1 ₁₅ and the parity arrays 2 ₀ and 2 _1. 4-bit data is read from the cell 11. Specifically, when the Y address is an even Y address, data is read from the data cell 11 located in the area 15A using the reference signal generated using the reference cell 12A located in the area 15A. In the case of an odd Y address, data is read from the data cell 11 located in the area 15B using a reference signal generated using the reference cell 12B located in the area 15B. Hereinafter, a reference cell used for generating a reference signal used for reading data is referred to as a selected reference cell.
Furthermore, the remaining bits of the parity symbols P0, P1 is read from the reference cell 12 of the data array _{1 0.} If the designated Y address is an even Y address, 2-bit data is read from the two reference cells 12B corresponding to the designated X address using the reference signal generated using the reference cell 12A. It is. On the other hand, in the case of an odd Y address, 2-bit data is read from the two reference cells 12A corresponding to the designated X address using the reference signal generated using the reference cell 12B. Hereinafter, the reference cell from which the remaining bits of the parity symbols P0 and P1 are read is referred to as a non-selected reference cell.
Controller 7, the 4-bit data read from the data array 1 _{0-1 15} adds a predetermined dummy bit to reproduce 16 data symbols. Further, the controller 7 adds the remaining bits read from the unselected reference cells to the 4-bit data read from the parity arrays 2 ₀ and 2 ₁ to reproduce two parity symbols.

Subsequently, the controller 7 performs error detection using the reproduced 16 data symbols and 2 parity symbols (step S02).
If no error is detected (step S03), the controller 7 outputs a read data read from the data array 1 _{0-1 15} directly (step S04), the read operation is completed.

On the other hand, if an error is detected, the controller 7 determines whether error correction is possible (step S05). In this embodiment, when an error is detected in one symbol, error correction is possible regardless of the number of bits of the error. If error correction is impossible, the controller 7 outputs an error signal and completes the read operation (step S12).
Where possible error correction, the controller 7 corrects the data read from the data array 1 _{0-1 15,} and outputs the corrected read data (step S06).

Further, the controller 7 performs an error correction operation on the data arrays 1 ₀ to 1 ₁₅ and the parity arrays 2 ₀ and 2 ₁ (steps S07 to S11). One subject of this error correction operation is a data cell 11, a selected reference cell (a reference cell used to generate a reference signal), and a non-selected reference cell (a reference cell from which the remaining bits of the parity symbol are read). Which of these should be corrected. Even if a data error is detected in the data cell 11 and the unselected reference cell, the data actually stored in the data cell 11 and the unselected reference cell does not necessarily have an error. Even when there is a data error in the selected reference cell used to generate the reference signal, the data error can be detected in the data cell 11 and the non-selected reference cell. In this embodiment, appropriate memory cell data is corrected according to the content of the error pattern detected in error detection.

Specifically, in this embodiment, when a data error is detected in both the data cell 11 and the non-selected reference cell, the data in the corresponding selected reference cell is inverted and corrected. This is because when a data error is detected in both the data cell 11 and the non-selected reference cell in a situation where the data error rate of the memory cell is sufficiently reduced, a data error in the selected reference cell has occurred. This is because the probability is the highest. On the other hand, if a data error is detected only in the data cell 11, the data in the data cell 11 is corrected. If a data error is detected only in the non-selected reference cell, the data in the non-selected reference cell is corrected. The
More specifically, if an error is detected and no error is detected in the unselected reference cell (ie, a data error is detected only in the data cell 11), as shown in FIG. The data in the data cell 11 in which an error is found is inverted, thereby correcting the data in the data cell 11 (step S11).

  On the other hand, when an error is detected in the non-selected reference cell (step S07) and an error is also detected in the data cell 11 (step S08), the controller 7 selects the reference as shown in FIG. 11B. It is determined that there is an error in the cell, and the corresponding selected reference cell is corrected. The correction of the selected reference cell is performed by inverting the data of only one of the two reference cells used for generating the reference signal. The state in which the selected reference cell has an error is a state in which the same data is written in two reference cells (although it is unknown whether the data is “1” or data “0”). The selected reference cell can be corrected by inverting only one data.

  Furthermore, when an error is detected in the non-selected reference cell (step S07) and no error is detected in the data cell 11 (step S08), as shown in FIG. It is determined that there is an error in the selected reference cell, and the non-selected reference cell in which the data error is detected is corrected.

  According to such a read operation, data written in the data cell 11 and the reference cell 12 can be corrected with high probability.

(Light operation)
As described above, in toggle writing, data reading is performed before the writing operation. Even if there is an error in the read data, if the data in the data cell 11 and the unselected reference cell are incorrect, the error in the data cell 11 and the unselected reference cell is automatically corrected by performing a write operation. can do. However, if the data of the selected reference cell is incorrect, erroneous data is read from the target memory cell in this data read, and as a result, there is a possibility that the incorrect data is written to the target memory cell. Therefore, in toggle writing, it is important that data can be written correctly even if the data stored in the selected reference cell is incorrect. In the write operation of the present embodiment, if there is an error in the selected reference cell, the selected reference cell is corrected, and then toggle writing to the data cell 11 is performed. Specifically, the write operation is performed according to the following procedure.

  When 4-bit write data is given per one data input / output, the write data is encoded (step S21). Specifically, the controller 7 adds data bits DQ0 to DQ15 by adding 1-bit dummy bits to the 4-bit write data applied to the data inputs / outputs DQ0 to DQ15. Further, the controller 7 calculates parity symbols P0 and P1 from the data symbols DQ0 to DQ15. As described above, the dummy bits of the data symbols DQ0 to DQ15 are determined so that one of the remaining bits (least significant bits) of the parity symbols P0 and P1 is data “0” and the other is data “1”. ing.

Further, data symbols and parity symbol data of blocks corresponding to the selected X address and Y address are read from the data arrays 1 ₀ to 1 ₁₅ and the parity arrays 2 ₀ and 2 ₁ (step S22). Data reading in step S22 is performed in the same manner as in step S01 described above. That is, in each of the data arrays 1 ₀ to 1 ₁₅ and the parity arrays 2 ₀ , 2 ₁ , 4-bit data is read from the four data cells 11 selected by the selected X address / Y address pair. Furthermore, the corresponding non-selected reference parity symbols from the cell P0, P1 remaining bits of the data array 1 ₀ is read. The controller 7 reproduces the data symbol by adding a dummy bit to 4-bit data read from each of the data arrays 1 _{0-1 15.} Further, the controller 7 regenerates the parity symbol by adding the remaining bits read from the non-selected reference cells to the 4-bit data read from each of the parity arrays 2 ₀ and 2 ₁ .

In the following, in order to distinguish the data symbols calculated from the write data from the data symbols reproduced from the data read from the data arrays 1 ₀ to 1 ₁₅ and the parity arrays 2 ₀ and 2 ₁ , the former is written. The data symbol and the latter will be referred to as a read data symbol. Further, in order to distinguish the parity symbol calculated from the write data from the parity reproduced from the data read from the data arrays 1 ₀ to 1 ₁₅ , the parity arrays 2 ₀ and 2 ₁ , the former is a write parity symbol, The latter will be described as a read parity symbol.

Subsequently, the controller 7 uses the read data symbols DQ0 to DQ15 and the read parity symbols P0 and P1 to detect errors in the data stored in the data arrays 1 ₀ to 1 ₁₅ and the parity arrays 2 ₀ and 2 _1. This is performed (step S23).

If no error is detected (step S24), the controller 7 writes the write data and the calculated write parity symbol to the corresponding memory cell by the toggle write operation (step S31). Writing data, the data array 1 _{0-1 15} selected X address, is written to the data cell 11 is selected by a set of Y-address. Whole write data symbols not written to the data cell 11 of the data array 1 _{0-1 15,} only 4 bits of the write data is written into data cell 11. Further, the upper 4 bits of the write parity symbol are written into the data cells 11 of the parity arrays 2 ₀ and 2 ₁ , and the least significant bit (remaining bit) is written into the non-selected reference cells of the data array 10.

  More specifically, when the bit of the write data symbol does not match the bit of the corresponding read data symbol read in step S22, the controller 7 permits the supply of the write current to the corresponding data cell 11. . Similarly, if the bit of the write parity symbol does not match the bit of the corresponding read parity symbol, the controller 7 permits the supply of the write current to the corresponding data cell 11. Further, a write current is supplied to the target data cell 11, whereby the data in the data cell 11 is inverted by toggle writing. When the bit of the read data symbol after error correction matches the bit of the corresponding write data symbol, and when the bit of the read parity symbol after error correction matches the bit of the corresponding write parity symbol No toggle writing is done.

On the other hand, when a data error is detected in step S23, the controller 7 determines whether error correction is possible (step S25). In this embodiment, when an error is detected in one symbol, error correction is possible regardless of the number of bits of the error. If error correction is impossible, the controller 7 outputs an error signal and completes the write operation (step S30 ).

  When error correction is possible, the controller 7 performs different operations depending on the error pattern obtained by error detection. When there is no data error in the non-selected reference cell despite the detection of the data error (that is, when the data error is detected only in the data cell 11), data writing is performed in the same procedure as in step S31. The state in which there is a data error in the data cell 11 is automatically eliminated by the data writing.

If a data error is detected in the non-selected reference cell (step S26) and no data error is detected in the data cell 11 (step S27) , data writing is performed in the same procedure as in step S31. (Step S29) . Simultaneously with data writing to the data cell 11, data writing to the non-selected reference cell is performed. The state in which there is a data error in the data cell 11 is automatically eliminated by the data writing.

  On the other hand, when a data error is detected in the non-selected reference cell (step S26) and a data error is also detected in the data cell 11 (step S27), the data in the selected reference cell is corrected (step S27). S28). As described above, the correction of the selected reference cell is performed by inverting the data of only one of the two reference cells used for generating the reference signal.

  Simultaneously with correction of the selected reference cell, data writing to the data cell 11 is performed. The controller 7 performs error correction on the read data symbol and the read parity symbol, and writes data to the data cell 11 using the read data symbol and read parity symbol after the error correction, and the write data symbol and write parity symbol. I do. If the bit of the write data symbol does not match the bit of the corresponding read data symbol after error correction, the controller 7 permits the supply of the write current to the corresponding data cell 11. Further, a write current is supplied to the target data cell 11, whereby the data in the data cell 11 is inverted by toggle writing. Toggle writing when the bit of the write data symbol and the corresponding bit of the read data symbol after error correction match, and when the bit of the write parity symbol matches the bit of the read parity symbol after error correction Is not done.

  Unlike the data writing in step S31, the data symbol used for data writing is not the data of the read data symbol and the read parity symbol read in step S22 but the data symbol after error correction generated by the controller 7. Note that the data is parity symbols. If there is an error in the selected reference cell, the data symbol and parity symbol data read in step S22 are different from the data actually stored in the data cell 11. Therefore, when there is an error in the selected reference cell, using the read data symbol and read parity symbol read using the selected reference cell for data writing will cause erroneous data to be written into the data cell 11. In the present embodiment, the data of the read data symbol and the read parity symbol after error correction (this data matches the data actually stored in the data cell 11) is used for data writing, so that correct data is obtained. Write can be realized.

  By performing the write operation according to the above procedure, data can be written while the selected reference cell is correctly corrected with high probability.

Claims (10)

An MRAM that uses an error correction code that is composed of a plurality of symbols, each symbol is composed of a plurality of bits, and that is capable of error correction in symbol units, for error detection and error correction,
A first data cell storing bits of a part of a data symbol of the symbols;
The partial bits are read from the first data cells, the data symbols are reproduced by adding predetermined dummy bits to the partial bits, and error detection and error correction are performed using the reproduced data symbols. Peripheral circuits to perform,
A second data cell storing a bit of a part of a parity symbol of the symbols;
A first reference cell and a second reference cell selected simultaneously with the first data cell during a read operation;
Equipped with,
The second reference cell is used to store a remaining bit of the parity symbol and generate a reference signal used for reading data from a data cell different from the first data cell;
The first reference cell is an MRAM used to generate a reference signal used for reading data from the first data cell and the second reference cell. The MRAM according to claim 1,
The second reference cell includes a first cell and a second cell that store complementary data,
The predetermined dummy bit is determined such that the remaining bits stored in the first cell and the second cell are complementary to each other. The MRAM according to claim 1 ,
When the peripheral circuit detects a data error in both the data symbol read from the first data cell and the remaining bit read from the second reference cell, the peripheral circuit is stored in the first reference cell. MRAM which corrects the data which is. The MRAM according to claim 3 , wherein
When the peripheral circuit detects a data error in the data symbol read from the first data cell and does not detect a data error in the remaining bits read from the second reference cell, MRAM that corrects data stored in one data cell. The MRAM according to claim 3 , wherein
The peripheral circuit detects a data error in the remaining bits read from the second reference cell, and detects no data error in the data symbol read from the first memory cell. 2. An MRAM that corrects the remaining bits stored in a reference cell. An MRAM that uses an error correction code that is composed of a plurality of symbols, each symbol is composed of a plurality of bits, and that is capable of error correction in symbol units, for error detection and error correction,
Multiple data cells,
A data symbol is generated by adding a predetermined dummy bit to the write data, a parity symbol is calculated using the generated data symbol, and only the bit corresponding to the write data among the data symbols A peripheral circuit for writing to the first data cell of the data cells;
A first reference cell and a second reference cell selected simultaneously with the first data cell during a read operation ;
Equipped with,
The peripheral circuit writes some bits of the parity symbol to a second data cell of the plurality of data cells, and writes the remaining bits of the parity symbol to the second reference cell;
The first reference cell is an MRAM used to generate a reference signal used for reading data from the first data cell and the second reference cell. The MRAM according to claim 6 , wherein
The second reference cell includes a first cell and a second cell that store complementary data,
The predetermined dummy bit is determined such that the remaining bits stored in the first cell and the second cell are complementary to each other. An MRAM that uses an error correction code that is composed of a plurality of symbols, each symbol is composed of a plurality of bits, and that is capable of error correction in symbol units, for error detection and error correction,
A first data cell used to store a bit of a data symbol of the plurality of symbols;
A second data cell used to store bits of a part of a parity symbol of the plurality of symbols;
A first reference cell used to generate a reference signal used for reading data of the first data cell;
A second reference cell used to generate a reference signal used for reading data of a data cell different from the first data cell;
The second reference cell is an MRAM used to store the remaining bits of the parity symbol. The MRAM according to claim 8 , wherein
The first reference cell is an MRAM used to generate a reference signal used for reading data from the second reference cell. The MRAM according to claim 8 , wherein
Furthermore,
With peripheral circuits,
In the first data cell, only some bits of the data symbol are stored,
The peripheral circuit reads the part of the bits from the first data cell, reproduces the data symbol by adding a predetermined dummy bit to the part of the bit, and the second data cell and the second data cell. 2. An MRAM that reads the parity symbol from two reference cells and performs error detection and error correction using the reproduced data symbol and the read parity symbol.

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