JP4903733B2 - ATM communication equipment - Google Patents

Description

  The present invention relates to an ATM communication apparatus that mainly uses an ATM communication system.

In the prior art, a conversion method required for connection between networks by different methods using an ATM (Asynchronous Transfer Mode) communication technology has been reported.
For example, a method related to connection between an ATM network and an STM (Synchronous Transfer Mode) network that defines and uses a communication band (for example, Patent Document 1, Patent Document 2, etc.), or connection between an ATM network and another ATM network There is a report about a technique that uses an ATM communication method such as a method of improving transmission efficiency by multiplexing ATM cells having a 24-octet structure on ATM cells when relaying (for example, Patent Document 3).

In a transmission device of an ATM communication system connected to an ATM network and a packet network, a problem solving technique for reducing a processing load in the protocol conversion process is reported in Patent Document 4 and the like accompanied with the protocol conversion process.
In Patent Document 4, in order to distribute the load of the processor included in the data link processing unit that centrally performs the protocol processing inside the transmission apparatus connected to the ATM network and the packet network, it is connected to the bus of the data link unit described above. There has been introduced a method of reducing the load on processor processing by a method of relaying ATM cells via a bus without relaying between an ATM line connection unit and a packet line connection unit by a data link unit.

In the ATM communication system, since the header information given to each ATM cell has individual information as an ATM cell, processing for each ATM cell is required.
In the case of connecting an ATM network and a packet network, a configuration method in the prior art based on a method in which protocol conversion is provided for each line module will be described with reference to FIG. FIG. 7 is a schematic block diagram of the prior art.

The ATM communication device 2 relays communication between two communication networks connected by two physical lines 411 and 412.
Here, the physical line 411 is connected to the ATM network and performs communication in the ATM communication system. The physical line 412 is connected to, for example, a packet network conforming to the Ethernet (registered trademark) or the IEEE 802.3 standard, and performs communication using a packet communication method.

  In the line module 13 connected to the physical line 411 which is an ATM line, the physical line accommodation unit 701 accommodates the physical line 411, performs physical condition conversion in the TRCV unit 731, and inputs received data to the FRAMER unit 721. To do. The physical condition conversion performed by the TRCV unit 731 is to convert various conditions of the physical line 411, that is, electric / optical / line frequency, etc. into electric signals that can be processed inside the apparatus.

The FRAMER unit 721 checks and shapes the arrived SONET / SDH frame (Synchronous Optical NETwork / Synchronous Digital Hierarchy frame), extracts ATM cells from the SONET / SDH frame, and performs error correction processing when an error is detected. The ATM cell that has been subjected to error correction processing is input to the protocol processing unit 801.
Here, the check is to determine the normality of the data by recalculating and collating a parity code or the like included in the data frame. In addition, shaping means performing calculation of an ATM cell position in a SONET / SDH frame.
The ATM cell format here is a 53-octet fixed-length cell format as shown in FIGS. 8 (a) and 8 (b). 8A is a UNI (User Network Interface) format, and FIG. 8B is an NNI (Network Node Interface) format, depending on the type of the ATM network to be connected. Applies.

The PROC (processor) unit 821 of the protocol processing unit 801 has a data exchange function for performing an exchange process, which is the main function of the ATM communication apparatus 2, and an ATM header extraction unit 824 for extracting a destination address and the like from the ATM header. SAR processing unit 822 that reassembles a plurality of ATM cells and converts them into a packet that conforms to the IEEE 802.3 standard, analyzes a packet that conforms to the IEEE 802.3 standard, determines an output port in the apparatus, and transmits it to the FAP unit 831 A packet processing unit 823.
Here, the SAR (Segmentation and Reassembly sub-layer) function of the SAR processing unit 822 is a function of dividing a packet conforming to the IEEE 802.3 standard into ATM cells and transmitting the ATM cell to the ATM network and its inverse conversion function. is there.

  The ATM header extraction unit 824 extracts a destination VPI / VCI from the ATM cell input to the PROC unit 821 and searches for a destination address to be transmitted to the SAR processing unit 822. The ATM cell is assigned destination information. In this state, the data is input to the SAR processing unit 822.

  The SAR processing unit 822 converts the ATM cell into a packet conforming to the IEEE 802.3 standard and inputs the packet to the packet processing unit 823.

  The packet processing unit 823 determines to which port in the apparatus to transmit based on the destination address information of the packet conforming to the IEEE 802.3 standard, stores the destination information in the data packet, and then stores the packet in FAP ( (Fabric access processor) unit 831.

  The FAP unit 831 is a processor that is connected to another protocol processing unit 802 via a transmission line and performs data exchange. The FAP unit 831 sends a data packet whose destination port number is determined to another protocol processing unit 802 in which the destination port exists. Enter it.

The FAP unit 832 in the protocol processing unit 802 to which the data packet is input inputs the input data packet to the PROC unit 841 that is the output destination.
The PROC unit 841 performs protocol processing such as address conversion and outputs the result to the physical line accommodation unit 702 that accommodates the physical line 412 of the packet communication specification.
The physical line accommodation unit 702 physically converts the input packet information and transmits the packet information to the physical line 412.

Next, transmission processing to the ATM line in the prior art will be described.
The physical line accommodating unit 702 connected to the physical line 412 which is a packet communication specification line performs physical conversion processing of packet information received through the physical line 412 and inputs the packet information to the protocol processing unit 802.
The PROC unit 841 of the protocol processing unit 802 extracts that the communication destination is the line module 13 from the input packet information, and inputs the packet information to the FAP unit 832.
The FAP unit 832 inputs the input data packet to the line module 13.
The FAP unit 831 of the line module 13 inputs the input packet information to the PROC unit 821.

  Based on the packet information input to the PROC unit 821, the packet processing unit 823 performs a packet extraction process that conforms to the IEEE 802.3 standard, extracts a destination address from a packet header that conforms to the IEEE 802.3 standard, and The destination information is attached to the packet and input to the SAR processing unit 822.

The SAR processing unit 822 divides a packet conforming to the IEEE 802.3 standard into ATM cells and inputs the ATM cell to the physical line accommodating unit 701.
The ATM cell input to the physical line accommodating unit 701 is input to the FRAMER unit 721. The FRAMER unit 721 inserts the ATM cell into the SONET / SDH frame and inputs it to the TRCV unit 731.
The TRCV unit 731 converts the physical line condition of the input ATM cell and transmits it to the physical line 411.

As described above, in any of the transmission and reception processes, the PROC unit 821 concentrates the extraction / analysis of the destination information and the addition of the destination information.
Japanese Patent Laid-Open No. 06-169320 Japanese Patent Laid-Open No. 05-022404 Japanese Patent Laid-Open No. 07-095215 JP 11-196104 A

  However, when processing is performed by a processor of a relay processing unit that performs ATM header exchange processing, the size of the ATM cell is defined as a short length of 53 octets, thereby increasing the communication speed to be used. Along with this, the amount of processing spent on the ATM cell exchange processing increases, and there is a problem in that the processing load by the processor of the relay processing unit increases.

  In addition to the exchange process, the processing required for the communication process tends to increase due to diversification of functions required for the communication process.

  In such a situation, in the exchange process that refers to the ATM header information, the following process is performed as the ATM header extraction process, which increases the load on the processor of the relay processing unit.

The reason why the processing load on the processing of the ATM header extraction unit 824 provided in the PROC unit 821 is high and causes a problem in apparatus mounting will be described with reference to FIGS.
As shown in FIG. 9, since the ATM header extraction unit 824 needs to handle the two types of cells shown in FIGS. 8A and 8B, it is necessary to divide the process into two types. is there.

In the case of a UNI cell, a GFC (Generic Flow Control) part is extracted as an information element allocated to 4 bits in the first octet from the beginning of the ATM header and stored in a GFC storage register (in the case of a NNI cell, there is no GFC field) Therefore, no extraction process is required).
Furthermore, although there are differences in the position and information size of information allocated to the two formats, the following information elements VPI (Virtual Path Identifier) / VCI (Virtual Channel Identifier) / PT (Payload Type) / CLP (Cell Loss Priority) is extracted and stored in each storage register.

Here, each storage register can be key information for a normal address search engine, and needs to be stored in a bit 0 position or a bit position depending on the processor architecture.
Therefore, as shown in FIG. 8, in the ATM cell format, information is allocated with 4 bits as a boundary. Therefore, a bit shift process is indispensable from each information extraction to storage, and the burden of the process related to information extraction is increased. It is getting bigger.

Furthermore, it has become easy to construct using the packet switching technology in the switching processing in the apparatus due to the spread of the packet communication technology. However, there is a problem that it is difficult to handle with a packet switching technique in which 53-octet ATM cells handled in the ATM communication system normally handle a packet length of 64 octets or more.
When a processor that focuses on packet processing conforming to the IEEE 802.3 standard is adopted, there are many examples in which the packet size is a variable length of 64 octets or more, and processing cannot be performed with a fixed-length cell of 53 octets. . For this reason, functions are realized using a processing method dedicated to ATM processing, and therefore, in an apparatus that performs packet processing, simplification of the realizing method is a problem.

  The present invention has been made to solve the above problems, and its purpose is to reduce the processing of a relay processing unit that performs ATM cell header processing according to the ATM communication method, and to provide an ATM communication device having high affinity with packet communication technology. It is to provide.

  In order to solve the above problems, the present invention provides an ATM line connection unit connected to an ATM line connected to an ATM network, and information contained in an ATM cell input from the ATM line connection unit received from the ATM line. An ATM header converter that outputs the ATM header information extracted from the header part of the ATM cell to the fixed length packet in units of octets for each information element, and the fixed length packet output from the ATM header converter. An ATM communication apparatus comprising: a relay processing unit that relays packets.

  The present invention is characterized in that the length of the fixed-length packet is 64 octets.

  The present invention is characterized in that the ATM header converter assigns information elements common to UNI ATM header information and NNI ATM header information to a common position in the fixed-length packet.

  The present invention is characterized in that the ATM header conversion unit extracts information on ATM cells allocated to fixed-length packets input from the relay processing unit as ATM cells and outputs the ATM cells to the ATM line connection unit. .

According to the present invention, an ATM communication device includes an ATM line connection unit connected to an ATM line connected to an ATM network, and information contained in an ATM cell input from the ATM line connection unit received from the ATM line. An ATM header conversion unit that outputs ATM header information extracted from the header portion of the ATM cell for each information element in a fixed-length packet in units of octets, and a packet of the fixed-length packet output from the ATM header conversion unit And a relay processing unit for relaying.
Thereby, it is possible to distribute the load of the relay processing unit related to the ATM processing, and there is an effect of improving the processing speed of the processor.

According to the present invention, the fixed-length packet has a length of 64 octets.
As a result, there is an effect that the means used in packet processing can be applied even when ATM processing is required.

Further, according to the present invention, the ATM header conversion unit assigns information elements common to UNI ATM header information and NNI ATM header information to common positions in the fixed-length packet.
As a result, it is possible to provide means that can perform processing in common in two different ATM interface specifications.

Further, according to the present invention, the ATM header conversion unit extracts the information of the ATM cell assigned to the fixed-length packet input from the relay processing unit as an ATM cell and outputs it to the ATM line connection unit. .
This makes it possible to perform ATM cell processing using a relay processing unit based on fixed-length packet processing.

(First embodiment)
Hereinafter, an embodiment of the present invention will be described with reference to FIG.
FIG. 1 is a schematic block diagram showing an ATM communication apparatus 1 according to an embodiment of the present invention.

  The ATM communication device 1 is connected to two communication networks connected by two physical lines 401 and 402.

  Here, it is assumed that the physical line 401 is connected to an ATM network and is serviced by ATM communication. The physical line 402 is connected to a packet network conforming to, for example, Ethernet (registered trademark) or IEEE 802.3 standard, and is serviced by a packet communication method.

The ATM communication device 1 includes line modules 11 and 12 that accommodate physical lines, and performs communication between two line modules by connection within the ATM communication device 1.
The ATM communication specification line module 11 is connected to a physical line 401 that is an ATM line, and the packet communication specification line module 12 is connected to a physical line 402 that is a packet line.

  The line module 11 includes a physical line accommodation unit 101 and a protocol processing unit 201.

(Physical line accommodation)
The physical line accommodating unit 101 is connected to the physical line 401 connected to the ATM communication apparatus 1, converts and relays information received from the ATM network connected by the physical line 401, and inputs the information to the protocol processing unit 201. Information input from the protocol processing unit 201 is converted and relayed and transmitted to the ATM network connected by the physical line 401.

The physical line accommodation unit 101 includes a TRCV unit 131, a FRAMER unit 121, and an ATM header conversion unit 141.
The TRCV unit 131 accommodates the physical line 401 connected to the physical line accommodation unit 101.
The TRCV unit 131 performs physical condition conversion for handling a signal adapted to the physical line 401. In addition, the TRCV unit 131 inputs information received from the physical line 401 to the FRAMER unit 121, and transmits information input from the FRAMER unit 121 to the physical line 401.
The physical condition conversion performed in the TRCV unit 131 is to convert various conditions of the physical line 401, that is, electric / optical / line frequency, etc. into electric signals that can be processed inside the apparatus.

The FRAMER unit 121 checks and shapes a SONET / SDH frame (Synchronous Optical NETwork / Synchronous Digital Hierarchy frame: a SONET / SDH frame is a physical layer protocol specification for transmitting ATM cells) input / output to / from the TRCV unit 131, Extraction processing and insertion processing of ATM cells transmitted in the SONET / SDH frame, error correction processing when a transmission error is detected, and the like are performed.
The FRAMER unit 121 extracts ATM cells from the SONET / SDH frame input from the TRCV unit 131 and inputs them to the ATM header conversion unit 141.
Further, the FRAMER unit 121 inserts the ATM cell input from the ATM header conversion unit 141 into the SONET / SDH frame and inputs the cell to the TRCV unit 131.
Here, the check is to determine the normality of the data by recalculating and collating a parity code or the like included in the data frame. In addition, shaping means performing calculation of an ATM cell position in a SONET / SDH frame.

The ATM header conversion unit 141 performs conversion processing between ATM cells and 64-octet fixed-length packets. Further, the ATM header conversion unit 141 is a connection unit with the protocol processing unit 201 in the physical line accommodation unit 101.
The ATM header conversion unit 141 adds the extended ATM header information based on the information by the ATM cell input from the FRAMER unit 121, converts the information into information by a fixed length packet of 64 octets, and inputs the information to the protocol processing unit 201. To do.
Also, the ATM header conversion unit 141 converts the information of a 64-octet fixed-length packet input from the protocol processing unit 201 into information of an ATM cell and inputs the information to the FRAMER unit 121.

(Protocol processing part)
The protocol processing unit 201 includes a PROC (processor) unit 221 including a SAR processing unit 222 and a packet processing unit 223, and an FAP (fabric access processor) unit 231.

  The PROC unit 221 has a data exchange function for performing an exchange process, which is a main function of the ATM communication apparatus 1, and performs a conversion process between information by an ATM cell and information by a packet compliant with the IEEE 802.3 standard.

In the PROC unit 221, the SAR processing unit 222 performs conversion processing between information using a plurality of ATM cells and information using packets. Processing corresponding to a general SAR (Segmentation and Reassembly sub-layer) function in the ATM communication system is performed.
The SAR processing unit 222 handles information by ATM cells allocated to fixed-length packets of 64 octets input from the physical line accommodation unit 101. The SAR processing unit 222 extracts information transmitted by payload portions of a plurality of input ATM cells and performs packetization processing. The SAR processing unit 222 refers to the extended ATM header portion attached to the input fixed-length packet, extracts the destination information included in the ATM cell, adds the extracted information, and inputs it to the packet processing unit 223.
Also, the SAR processing unit 222 decomposes the information from the packet input from the packet processing unit 223, adds the destination information to form an ATM cell, allocates it to a fixed-length packet of 64 octets, and assigns it to the physical line accommodating unit 101. Output.

The packet processing unit 223 performs conversion processing between packet information that is packetized from an ATM cell and input by the SAR processing unit 222 and information that is handled as a packet that conforms to the IEEE 802.3 standard.
The packet processing unit 223 adds information such as a destination address to be handled as a packet conforming to the IEEE 802.3 standard to the packet information input from the SAR processing unit 222 and inputs the packet information to the FAP unit 231.
Further, the packet processing unit 223 extracts the destination address from the information handled as a packet conforming to the IEEE 802.3 standard input by the FAP unit 231, converts the packet into packet information to which the destination information is added, and inputs the packet information to the SAR processing unit 222. To do.

The FAP unit 231 is a processor that is connected to the line module 12 via a transmission line to exchange data.
The FAP unit 231 determines an output destination based on the destination port number designated by the protocol processing unit 201, and inputs a data packet to the line module 12 in which the destination port exists.
In addition, the FAP unit 231 inputs the data packet input from the line module 12 to the protocol processing unit 201 that is the designated destination.

The line module 12 is different from the ATM line specification line module 11 described above in that the applied physical line 402 is a packet line specification line. Therefore, the line module 12 does not require ATM processing, and relays between the line module 11 and the physical line 402 by packet processing.
The line module 12 includes a physical line accommodation unit 102 and a protocol processing unit 202.

  The physical line accommodation unit 102 accommodates the physical line 402, connects the physical line 402 and the protocol processing unit 202, and converts physical conditions applied to the physical line 402.

The protocol processing unit 202 relays communication between the physical line accommodating unit 102 and the line module 11 by packet processing.
The protocol processing unit 202 includes a PROC unit 241 and an FAP unit 232.

The PROC unit 241 extracts the address information of the destination from the packet information from the physical line accommodating unit 102, adds it to the packet information, and inputs it to the FAP unit 232.
Further, packet information to which the destination address information is added is generated based on the destination information added to the packet information input from the FAP unit 232, and is input to the physical line accommodating unit 102.

The FAP unit 232 is a processor that is connected to the line module 11 via a transmission line to exchange data.
The FAP unit 232 determines an output destination based on the destination port number designated by the protocol processing unit 202, and inputs a data packet to the line module 11 in which the destination port exists.
Further, the FAP unit 232 inputs the data packet input from the line module 11 to the protocol processing unit 202 that is the designated destination.

Next, the ATM header converter 141 will be described with reference to FIG.
First, conversion processing from an ATM cell received from an ATM line to a fixed-length packet will be described.
FIG. 2 is a block diagram of a conversion unit from an ATM cell to a fixed-length packet in the ATM header conversion unit 141.

The ATM header conversion unit 141 includes an IGBT unit 10 and an IGCELL unit 20.
The IGBUF unit 10 receives the ATM cell from the FRAMER unit 121 in FIG. 1 as an input, records the input ATM cell as a temporary storage area for processing by the IGCELL unit 20, and records the recorded ATM cell information. Read processing is performed.

The IGBT unit 10 includes input buffer units 11 and 12 that function as reception buffers for temporary storage areas, and a switcher 13 that switches between reading from the input buffer units 11 and 12.
The IGBUF unit 10 records the ATM cell in the input buffer unit 11 (or 12) when the ATM cell is input from the FRAMER unit 121. The IGBUF unit 10 notifies the IGCELL unit 20 that an ATM cell has been input, triggered by the input of the ATM cell.
The IGBUF unit 10 switches the switch 13 to the input buffer unit 11 (or 12) side in accordance with the IGCELL unit 20, reads the ATM cell stored in the input buffer unit 11 (or 12), and sends the ATM cell to the IGCELL unit 20 Output the cell.

  The IGCELL unit 20 includes a read control unit 21, a header buffer unit 22, a payload buffer unit 23, an extension header generation unit 24, output buffer units 25 and 26, and a switch 27.

  The read control unit 21 receives a notification that an ATM cell has been input to the input buffer unit 11 (or 12) in the IGBT unit 10. Further, the read control unit 21 notifies the IGBT BUFFER 10 of a read start notification for reading the stored ATM cell from the input buffer unit 11 (or 12) and inputting it to the IGCELL unit 20.

  The header buffer unit 22 temporarily holds the ATM cell header (4 octets) input from the IGBT unit 10 and inputs the ATM cell header to the extension header generation unit 24. Also, the ATM header information of the output buffer unit 25 (or 26) Record in the header.

  The payload buffer unit 23 temporarily holds the ATM cell payload (48 octets) input from the IGBT unit 10 and records it in the ATM payload information recording unit (payload) of the output buffer unit 25 (or 26).

  The extension header generation unit 24 rearranges the information so that the header information of the ATM cell input from the header buffer unit 22 is placed at a predetermined position in the output buffer unit 25 (or 26), and outputs the output buffer unit 25. (Or 26) is recorded in the extended ATM header information recording section (ext # header).

The output buffer units 25 and 26 are output buffers serving as temporary storage areas having fixed-length packets of 64 octets, and are switched and used according to the information input status.
The output buffer units 25 and 26 hold ATM information to be relayed and extended ATM header information.

  When the header buffer unit 22, the payload buffer unit 23, and the extension header generation unit 24 record information to the output buffer unit 25 (or 26) from the respective units, the switching unit 27 outputs the information from the output buffer 25 (or 26) that has the complete information. Reading is performed and output to the protocol processing unit 201 is performed.

With reference to FIG. 3 and FIG. 4, a description will be given of a process for allocating a fixed-length packet of ATM cells 64 octets defined by the UNI format.
FIG. 3 shows an ATM cell 151 defined by UNI and a fixed-length packet 251 to which ATM cell information is allocated.

The UNI ATM cell 151 has an information amount of 52 octets, and an ATM header 156 (4 octets) excluding HEC (Header Error Control) information (1 octet) corresponding to the fifth octet in the ATM cell header information and a payload 157 ( 48 octets).
GFC (Generic Flow Control) 152, VPI (Virtual Path Identifier) 153, VCI (Virtual Channel Identifier) 154, PT (Payload Type) / CLP (Cell Loss Priority) 155, and Payload 157 are assigned in order from the first octet without any gaps. It has been.

The fixed-length packet 251 has an information amount of 64 octets, defines the first to eighth octets as an extended ATM header 258, rearranges the information allocated to the ATM header 156, and creates a new information element Define as
Information to be rearranged in the extended ATM header 258 is information on the GFC 152, VPI 153, VCI 154, and PT / CLP 155 extracted from the information included in the ATM header 156.
For the rearrangement in the extended ATM header 258, GFC252 is assigned to the first octet, VPI253 is assigned to the second octet, VCI254 is assigned to the fourth to fifth octets, and PT / CLP255 is assigned to the sixth octet in this order. Alignment processing is performed in units of octets at the allocation position of information element rearrangement. Therefore, the fixed-length packet 251 includes unused bits at the location of the GFC 252 and PT / CLP 255 defined by 4 bits.

  The GFC 252, VPI 253, VCI 254, and PT / CLP 255 that are information elements of the extended ATM header 258 have the same values as the GFC 152, VPI 153, VCI 154, and PT / CLP 155 extracted from the information included in the ATM header 156.

In the fixed-length packet 251, an ATM header 256 and a payload 257 are arranged following the extended ATM header 258. The ATM header 256 and the payload 257 assign the ATM header 156 and the payload 157 in the ATM cell 151 as they are.
By arranging the ATM header 256 and the payload 257 side by side, the fixed-length packet 251 has an effect that it can be read and used as it is without re-conversion in an application using the ATM cell structure.
With the above allocation, the fixed-length packet 251 includes the preliminary information 261 to 264. Note that a predetermined value is assigned as the value of the preliminary information 261 to 264.

Next, the reception process of the ATM communication device 1 will be described with reference to FIG.
FIG. 4 is a flowchart showing a process for converting the ATM cell shown in FIG. 3 into a fixed-length packet in the ATM header converter 141 shown in FIG.

First, the TRCV unit 131 of the physical line accommodating unit 101 receives a signal input from the physical line 401.
The TRCV unit 131 performs physical condition conversion on the signal input from the physical line 401 and inputs information received from the physical line 401 to the FRAMER unit 121.

  The FRAMER unit 121 inputs termination processing of the input SONET / SDH frame and ATM cells extracted from the SONET / SDH frame to the ATM header conversion unit 141.

  The ATM header converter 141 converts the input ATM cell into a 64-octet fixed length packet according to the format shown in FIG.

  In the ATM header conversion unit 141, the ATM cell input from the FRAMER unit 121 is input and temporarily recorded in the input buffer unit 11 (or 12) of the IGBT unit 10 shown in FIG. When the input to the input buffer unit 11 (or 12) is completed, the IGBUF unit 10 notifies the read control unit 21 of the IGCELL unit 20 of an input completion signal (step Sa11).

The read control unit 21 returns a read start notification to the IGBT unit 10. The IGBUF unit 10 switches the switch 13 to read from the input buffer unit 11 (or 12), and inputs the ATM header 156 to the header buffer unit 22 of the IGCELL unit 20.
The header buffer unit 22 records the input ATM header 156 in a temporary storage area, reads the ATM header 156, and inputs it to the extension header generation unit 24.
The extension header generation unit 24 extracts GFC152 information from the input ATM header 156, and records the extracted GFC152 in the GFC252 which is the first octet of the output buffer unit 25 (or 26) having the fixed-length packet 251 as an element. (Step Sa12).

  The extension header generation unit 24 extracts the VPI 153 information from the input ATM header 156 and records the extracted VPI 153 in the VPI 253 which is the second octet of the output buffer unit 25 (or 26) having the fixed-length packet 251 as an element. (Step Sa13).

  The extension header generation unit 24 extracts the VCI 154 information from the input ATM header 156 and extracts the VCI 154 extracted to the VCI 254 that is the third and fourth octets of the output buffer unit 25 (or 26) having the fixed-length packet 251 as an element. Is recorded (step Sa14).

  The extension header generation unit 24 extracts PT / CLP155 information from the input ATM header 156, and extracts it into the PT / CLP255 which is the sixth octet of the output buffer unit 25 (or 26) having the fixed-length packet 251 as an element. The PT / CLP 155 thus recorded is recorded (step Sa15).

  The extension header generation unit 24 records the specified value at the seventh and eighth octets of the output buffer unit 25 (or 26) having the fixed-length packet 251 as an element (step Sa16).

  The header buffer unit 22 reads the temporarily recorded ATM header 156 and records it in the ATM header 256 which is the 9th to 12th octets of the output buffer unit 25 (or 26) having the fixed-length packet 251 as an element. (Step Sa17).

Further, the IGBUF unit 10 subsequently performs reading from the input buffer unit 11 (or 12) and inputs the payload 157 to the payload buffer unit 23 of the IGCELL unit 20.
The payload buffer unit 23 reads the temporarily recorded payload 157 and records it in the payload 257, which is the 13th to 60th octet of the output buffer unit 25 (or 26) having the fixed-length packet 251 as an element (step Sa18). ).

  The IGCELL unit 20 records a specified value at the 61st to 64th octets of the output buffer unit 25 (or 26) having the fixed-length packet 251 as an element (step Sa19).

  When the information input to the output buffer unit 25 (or 26) is completed, the IGCELL unit 20 switches the switch 27, reads out from the output buffer unit 25 (or 26), and inputs it to the protocol processing unit 201 (step Sa20). ).

  As described above, by adding the processing of the ATM header conversion unit 141, it is possible to reduce the load on the protocol processing unit 201 related to the extraction of information elements from the header information performed for each ATM cell.

(Second Embodiment)
In the first embodiment, the embodiment when applied to a UNI format ATM cell has been described. In the second embodiment, an embodiment when applied to an NNI format ATM cell will be described.
Since the schematic block diagram shown in FIG. 1 is also referred to, description of the configuration and reference numerals is omitted.

With reference to FIG. 5 and FIG. 6, a description will be given of a process of allocating a fixed-length packet of ATM cells 64 octets defined by the NNI format.
The difference from the above-mentioned UNI format is that the NNI format has no GFC assignment, and the reduced GEC is further assigned as VPI information.

  FIG. 5 shows an ATM cell 171 defined by NNI and a fixed-length packet 271 to which ATM cell information is assigned.

In FIG. 5, the first octet of the fixed-length packet 271 is used as the preliminary information 281. Also, the VPI 173 of the NNI ATM cell 171 is allocated as the VPI 273 of the second and third octets of the fixed-length packet 271.
Except for the above, it is the same as the UNI ATM cell allocation method in FIG.

  In FIG. 6, as described in the process of allocating the UNI format ATM cell of FIG. 5 to the fixed-length packet 271, the ATM header conversion unit 141 uses the ATM BUF unit shown in FIG. 2 as the ATM cell input from the FRAMER unit 121. The data is input to ten input buffer units 11 (or 12) and temporarily recorded. When the input to the input buffer unit 11 (or 12) is completed, the IGBUF unit 10 notifies the read control unit 21 of the IGCELL unit 20 of an input completion signal (step Sa21).

The read control unit 21 returns a read start notification to the IGBT unit 10. The IGBUF unit 10 switches the switch 13 to read from the input buffer unit 11 (or 12), and inputs the ATM header 176 to the header buffer unit 22 of the IGCELL unit 20.
The header buffer unit 22 records the input ATM header 176 in a temporary storage area, reads the ATM header 156, and inputs it to the extension header generation unit 24.

  The extension header generation unit 24 records the specified value in the first octet of the output buffer unit 25 (or 26) having the fixed-length packet 271 as an element (step Sa22).

  The extension header generation unit 24 extracts the VPI 173 information from the input ATM header 176 and extracts the VPI 173 extracted into the VPI 273 that is the second and second octets of the output buffer unit 25 (or 26) having the fixed-length packet 271 as an element. Is recorded (step Sa23).

  Thereafter, the extension header generation unit 24 extracts VCI 174 information from the input ATM header 176 by the same processing as the UNI format, and the output buffer unit 25 (or 26) 3 including the fixed-length packet 271 as an element, The extracted VCI 174 is recorded in the VCI 274, which is the fourth octet (step Sa24).

  The extension header generation unit 24 extracts PT / CLP175 information from the input ATM header 176, and extracts it into PT / CLP275, which is the sixth octet of the output buffer unit 25 (or 26) having the fixed-length packet 271 as an element. The PT / CLP 175 thus recorded is recorded (step Sa25).

  The extension header generation unit 24 records the specified value at the seventh and eighth octets of the output buffer unit 25 (or 26) having the fixed-length packet 271 as an element (step Sa26).

  The header buffer unit 22 reads the temporarily recorded ATM header 176 and records it in the ATM header 276 that is the 9th to 12th octets of the output buffer unit 25 (or 26) having the fixed-length packet 271 as an element. (Step Sa27).

Further, the IGBUF unit 10 subsequently reads from the input buffer unit 11 (or 12) and inputs the payload 177 to the payload buffer unit 23 of the IGCELL unit 20.
The payload buffer unit 23 reads the temporarily stored payload 177 and records it in the payload 277, which is the 13th to 60th octet of the output buffer unit 25 (or 26) having the fixed-length packet 271 as an element (step Sa28). ).

  The IGCELL unit 20 records the specified value at the 61st to 64th octets of the output buffer unit 25 (or 26) having the fixed-length packet 271 as an element (step Sa29).

  When the information input to the output buffer unit 25 (or 26) is completed, the IGCELL unit 20 switches the switch 27 to read from the output buffer unit 25 (or 26) and input it to the protocol processing unit 201 (step Sa30). ).

(Third embodiment)
In the first embodiment and the second embodiment, the reception processing from the ATM line side toward the packet communication line has been described.
Next, transmission processing from the packet communication line side to the ATM line will be described as a third embodiment.
Since the schematic block diagram shown in FIG. 1 is also referred to, description of the configuration and reference numerals is omitted.

In the case of the above-described reception process from the ATM line, it is necessary to change the process depending on the type of the ATM line to be connected.
Regarding the transmission process to the ATM line described here, a method is described in which the ATM header conversion unit 141 does not refer to the ATM header information unlike the above-described reception process.

The ATM cell information (52 octets) in the fixed-length packet (64 octets) input from the PROC unit 221 is matched with the structure of the ATM cells (52 octets) input to the FRAMER unit 121 at the subsequent stage by the ATM header converter 141. In other words, the fixed length packets are continuously allocated.
The allocation to fixed-length packets is the allocation from the 1st octet to the 52nd octet.

As a result, the ATM header conversion unit 141 may not perform the process of referring to the ATM cell information (particularly ATM header information) input from the PROC unit 221.
Further, since the ATM header conversion unit 141 does not use the extended ATM header, the extended ATM header information is not allocated to the fixed-length packet, and the ATM cell is generated without increasing the process of generating the extended ATM header as the process of the PROC unit 221. Can be generated.

  By taking the above method, the ATM header converting unit 141 according to the present embodiment records the fixed-length packet to which the ATM cell information input from the PROC unit 222 is allocated in the temporary storage area, and is allocated. An ATM cell is extracted, and the information is read as it is and input to the FRAMER unit 121.

The process flow will be described again as follows.
When a data packet is input from the line module 12 to the protocol processing unit 201, the FAP unit 231 inputs the data packet input from the line module 12 to the designated protocol processing unit 201.

Based on the address information given to the packet information input from the FAP unit 231, the SAR processing unit 222 of the PROC unit 221 performs ATM cell conversion.
The SAR processing unit 222 assigns ATM cell information to the fixed-length packet, and inputs the fixed-length packet to the ATM header conversion unit 141 of the physical line accommodating unit 101.

  The ATM header conversion unit 141 that has received the fixed-length packet extracts the allocated ATM cell information and inputs it to the FRAMER unit 121.

  The FRAMER unit 121 to which the ATM cell is input inserts the ATM cell input from the ATM header conversion unit 141 into the SONET / SDH frame and inputs it to the TRCV unit 131.

  The TRCV unit 131 sends the information input from the FRAMER unit 121 to the physical line 401 for the ATM cell inserted in the SONET / SDH frame.

  By taking the above processing, it is not necessary to change the processing for the transmission to the ATM line in the ATM header conversion unit 141 depending on the type of ATM line (UNI and NNI).

In addition, although allocation of ATM cell information and extended ATM header information to a fixed frame is shown in FIG. 3, the allocation order and position of each information element are not limited to the above description, and another allocation may be performed. Is possible. The method of assigning information elements to the extended ATM header described is characterized in that assignment is performed in units of octets.
By assigning information elements of the ATM header in units of octets, the bit shift processing by the PROC unit 221 can be realized by the ATM header conversion unit 141.

  Although the input / output of the SAR processing unit 222 has been described as a method using a fixed-length packet of 64 octets, the fixed-length packet of 64 octets input / output to / from the physical line accommodating unit 101 using the SAR function in the prior art. An embodiment in which a conversion processing unit between the SAR function and the conventional technology is mounted on the PROC unit 221 is also an example of the SAR processing unit 222 of this embodiment.

  It is also possible to implement a method in which the fixed length packets 251 and 271 in the reception processing from the ATM line are configured as spare areas without allocating the ATM headers 256 and 276.

  Even when an OAM (Operation, Administration, and Maintenance) function for managing the communication quality of an ATM line by the ATM communication method is used, an ATM processing unit is provided on the physical line accommodation unit 101 side of the PROC unit 221 in FIG. The OAM function can be processed by referring to the extended ATM header assigned to the fixed-length packet.

If the FAP unit 231 exists in the physical line accommodating unit 101 accommodated by itself as the destination port number, the FAP unit 231 transmits data to the PROC unit 221 without passing through the transmission path between the FAP unit 231 and the FAP unit 232. It is also possible to adopt a configuration for performing transmission.
Further, when a configuration is adopted in which a plurality of ATM lines are accommodated in the physical line accommodating unit 101 and communication is performed without going through the FAP unit 231, transmission and reception of the ATM header and payload position to a fixed-length packet are performed. By combining these, it is possible to reduce the load of the relay processing of the PROC unit 221 when relaying between ATM lines.

  Note that the switching between the input buffer units 11 and 12 and the output buffer units 25 and 26 in the ATM header converting unit 141 is used as a temporary storage area, so that it is selected depending on the respective usage conditions. Control is in progress.

1 is a schematic block diagram according to a first embodiment of the present invention. It is a block diagram in the ATM cell conversion part of FIG. It is the allocation figure of the ATM cell information to the fixed length packet in 1st Embodiment (the 1). It is a flowchart (the 1) regarding the conversion process which performs the allocation process of the ATM cell information to the fixed length packet in 1st Embodiment. It is the allocation figure (the 2) of the ATM cell information to the fixed length packet in 1st Embodiment. It is a flowchart (the 2) regarding the conversion process which performs the allocation process of the ATM cell information to the fixed length packet in 1st Embodiment. It is a schematic block diagram in a prior art. It is a structure of an ATM cell format. It is a flowchart regarding the ATM header process performed by the prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ATM communication apparatus 11, 12 Line module 101,102 Physical line accommodating part 121 FRAMER part 131 TRCV part 141 ATM header conversion part 201,202 Protocol processing part 221,241 PROC part 222 SAR processing part 223 Packet processing part 231,232 FAP Unit 401, 402 Physical line

Claims (4)

An ATM line connection unit for connecting to an ATM line connected to the ATM network;
The information contained in the ATM cell received by the ATM line connection unit received from the ATM line and the ATM header information extracted from the header part of the ATM cell are assigned to fixed length packets in units of octets for each information element and output. An ATM header converter to
A relay processing unit that relays the packet of the fixed-length packet output from the ATM header conversion unit;
An ATM communication device comprising:   2. The ATM communication apparatus according to claim 1, wherein the length of the fixed-length packet is 64 octets.   2. The ATM communication apparatus according to claim 1, wherein the ATM header conversion unit assigns an information element common to UNI ATM header information and NNI ATM header information to a common position in the fixed-length packet. .   2. The ATM header conversion unit extracts information of an ATM cell allocated to a fixed length packet input from the relay processing unit as an ATM cell and outputs the ATM cell information to the ATM line connection unit. The ATM communication device described.

Images