JP4907663B2 - Strobe technique for recovering clocks in digital signals - Google Patents

Description

The present invention relates generally to semiconductor chip testing, and more specifically to digital device clocking.
REFERENCES TO RELATED APPLICATIONS This application is a priority of US patent application Nos. 11 / 234,599, 11 / 234,814, and 11 / 234,542, all filed September 23, 2005. And the contents of those patent applications are hereby incorporated by reference in their entirety.

  Automatic test equipment (ATE) is widely used to test semiconductor chips and integrated circuits being manufactured. A functional test is typically performed by configuring an ATE to apply electrical signals to multiple connection points on a DUT while measuring the output response of the device under test (DUT) at a particular connection point. The

  ATE typically measures the relative timing between an applied input signal and a measured output signal when evaluating the performance of the DUT. Especially when evaluating the response of a DUT to high-speed signals, it is often necessary to make the timing of the test system clock very accurate to ensure that appropriate data is collected.

  In many cases, it is desirable to test DUT performance against the DUT system clock. Thus, the ATE can typically be configured to measure the output at multiple points in time relative to the internal clock of the DUT. However, signal slewing and jitter can have a significant effect on measurement results, and as data and clock speeds increase, measurements for the DUT system clock may not be accurate.

  Currently, many integrated circuits (ICs) include a bus having a synchronous clock associated with the data. It is impractical to access the DUT's synchronous internal clock without being associated with a valuable test system hardware channel. Also, data on the bus can have very high jitter compared to the test system clock, so far it has been a problem to test data on a bus with a synchronous clock using the test system clock. was there.

  Method and apparatus for emulating a DUT clock for comparison with a DUT data signal using a test system clock without suffering from the excessive slew and jitter typically associated with using a system clock No. 11 / 234,542 (Attorney Docket No. 1954-US) filed by the present applicant on September 23, 2005 and entitled “STROBE TECHNIQUE FOR TEST OF DIGITAL SIGNAL TIMING”. (4057/81) 077311-0104), the patent application of which is hereby incorporated by reference.

  In systems where clock information is embedded in a digital signal, it is often desirable to regenerate the clock information for testing purposes. For example, in the ATE field, it is often desirable to recover the clock information embedded in the digital signal received from the DUT. Until now, clock information has usually been recovered from digital signals by using a clock recovery circuit based on a phase-locked loop PLL. The clock recovery circuit based on the PLL has the disadvantage that it is limited to use in a specific preset bandwidth.

  Embodiments of the present invention recover clock information embedded in a digital signal such as a data signal. In one exemplary embodiment, a set of strobe pulses is generated by routing the edge generator to a series of delay sections with progressively increasing delay values. A digital signal is applied to each input of a set of parallel latches clocked by strobe pulses. Thereby, a set of parallel latches captures a series of samples of a single shot of the data signal at multiple time points where the delay gradually increases.

  In the exemplary embodiment, an encoder converts a single shot series of samples into words that represent the edge time and polarity of the sampled signal. Words representing edge times can be stored in memory. An accumulator collects the average edge time over many (N) samples. The value N used in the accumulator sets the number of samples that average the data, thereby setting the effective bandwidth of the exemplary embodiment of the present invention. The average edge time is adjusted by a constant deskew value, which can be stored, for example, in a register. The resulting adjusted time represents the recovered clock time and is then used as a pointer to the memory. The difference between the recovered clock time and the data edge time stored at the address pointed to by the recovered clock can be determined and compared to the expected value.

  In one exemplary embodiment, the present invention applies a strobe to a digital signal, stores the state of the digital signal at the time of each strobe pulse of the strobe, and stores the stored data in the state of the digital signal. A method is provided for extracting a clock signal from a digital signal by encoding it as a digital word that identifies the edge time of change, and determining an average edge time over a predetermined number of samples of the digital word. As the digital signal, for example, a data signal of a device under test can be used. In one particular embodiment, the digital word can be stored in one memory location and the average edge time can be used as a pointer to that memory location.

  In certain embodiments, a fixed deskew value can be added to the average edge time to form an adjusted average edge time. The adjusted average edge time represents an extracted clock that can be used as a pointer to memory. The average edge time or adjusted average edge time can be provided to multiple channels via the bus and can be used as a pointer to memory on the receiving channels of the multiple channels. The data edge time stored in the memory addressed by the average edge time or the adjusted average edge time can be compared with the expected data to provide a pass / fail indication for the device under test.

  Applying each edge of the strobe as a latch clock signal to the corresponding latch of the plurality of latches, applying a digital signal to each input of the latch, and receiving the state of the digital signal as each output of the latch By doing so, the strobe can be applied to the digital signal. In a particular embodiment, as a result of the encoding step, a multi-bit word is generated, the first part specifying the time of state change and the second part specifying the polarity of state change. Multi-bit word transmission can be demultiplexed (demultiplexed) to reduce its transmission rate.

  In an exemplary embodiment of the invention, an edge generator output signal is applied to a delay circuit including a series of delay elements, and a series of delayed delays of the edge generator output signal are generated by the series of delay elements. Strobes can be generated by connecting each delay element to receive. Each successively delayed pulse forms one of the strobe pulses. The delay circuit can be controlled by a delay locked loop, which includes a controllable summing element that can be adjusted to correct the delay line error.

  Another exemplary embodiment of the present invention provides an apparatus for extracting a clock signal from a digital signal. The exemplary apparatus communicates with an edge generator (connected signalably) and gradually delays the strobe and a clock connected to a corresponding one of the delay elements. A plurality of latches having a supply input and having a data input for receiving a data signal, and an encoder connected to the plurality of latches for signal transmission. The encoder converts the information stored in the plurality of latches into a digital word representing the edge time of the digital signal. The exemplary embodiment also includes an averaging circuit that is adapted to receive a plurality of digital words from the encoder and determine an average thereof. A memory connected in signal communication with the encoder can be provided for receiving and storing the digital word. In order to reduce the data transfer rate to the memory, a demultiplexing circuit connected to the encoder and the memory so as to transmit signals can be provided.

  In one particular embodiment, the averaging circuit may comprise an accumulator that is communicatively connected to an encoder and that receives a digital word. A clock delay data register stores the deskew value. An adder circuit that is communicably connected to the accumulator and clock delay register adds the average edge time to the deskew value to provide an adjusted average edge time representative of the extracted clock value.

  In order to address the memory using the extracted clock value as a pointer to the memory, an averaging circuit and a routing circuit connected in signal communication with the memory can be provided. The routing circuit can be configured to communicate signals to and from multiple channels, and can include, for example, a clock bus. Providing a comparator circuit communicatively connected to the memory for comparing the expected value of the data at a particular clock time with the value of the data in the memory addressed by the extracted clock value Can do.

  The above features and advantages and other features and advantages of the present invention will be more fully understood from the following detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

  One exemplary method for testing and evaluating data generated by a synchronized clock without directly comparing the synchronized clock signal and the data signal under test is comprehensively described with reference to FIG. The

  In the sampling step 10, the data signal and the clock signal of the device under test (DUT) are sampled using the strobe, and the binary value of the state is obtained at a high speed. Thus, the sampled data is obtained as a series of single shot samples of the signal under test at intervals where the delay amount gradually increases. Although the term “single shot” is used herein, various embodiments of the present invention can capture multiple “single shot” series of samples, eg, on multiple channels, Alternatively, it will be appreciated that the sampling step 10 can be performed over and over again by repeating the clock recovery method of the present invention over and over time.

  Within a single shot series, the edge time and edge polarity of the signal under test are detected. In the encoding step 12, the detected edge time and polarity are encoded into a binary word. In one implementation, the encoded edge time is represented as the lower 5 bits of a 6-bit word and the polarity is represented as the most significant bit.

  In one example of a high-speed test apparatus using the method of the present invention, an encoded 6-bit word is generated at approximately 2 gigabytes / second. To provide a more suitable data rate for downstream storage and comparison steps, the encoded words are demultiplexed to give 48-bit words at only 250 megabytes / second. A 48-bit word represents eight 5-bit edge times and corresponding eight 1-bit edge polarities.

  In selector step 14, it is determined whether the encoded data represents the edge time and polarity of the sampled data signal or the edge time and polarity of the sampled clock signal. If the encoded data represents the edge time and polarity of the sampled data signal, storage step 16 is performed and the encoded data is stored in the random access memory. In the exemplary embodiment, the encoded data is stored using 96 × 40 random access memory.

  If the encoded data represents the edge time and polarity of the sampled synchronous clock signal, only the encoded data having one polarity is selected and used as the clock edge time. In clock selection step 18, the encoded clock edge time is routed to the clock bus. Thus, clock edge data can be routed to multiple channels and used in one or more chips.

  In the memory access step 20, the clock data is used as a pointer to the random access memory address of the corresponding encoded data signal edge time. In a comparison step 22, the data edge time found in the memory at the clock address is compared with an expected value to determine whether the representative data signal edge time is within a predetermined limit of the representative clock edge time. Is done. Thereby, a pass / fail instruction can be automatically generated.

  Sampling step 10 is performed to obtain short interval readings of the state of the DUT data signal and / or clock signal. FIG. 2 is a schematic timing chart showing an example of the relative timing of the data signal 24 edge and the clock signal 26 of the device under test. Data signal 24 within the device under test is shown as a voltage / logic level that changes state at edge 28. Clock signal 26 changes state at edge 30. Strobes 32, 34 provide short-interval pulses, each triggering a sampling of the state of the data signal under test.

  As a result of the sampling, a series of bits 36, 38 indicating the state of the data signal under test or the clock signal is generated in a short time interval. The change in state 40 in the series of bits 38 representing the clock signal can be used as a timing reference for comparison with the state 42 of the data signal in the series of bits 36 representing the data signal. In the exemplary embodiment, the series of bits 36 and 38 are further encoded before a comparison between them is made, as described herein with reference to FIGS.

  Throughout this specification, the term “short interval” used to describe a series of strobe pulses or signals should be interpreted broadly, and such intervals are dependent on the requirements of a particular test configuration. Those skilled in the art will appreciate that this may be different. It is understood that such pulses or signals that are “short intervals” relative to the timing of the device under test will probably have a higher frequency than the signal under test or clock signal, or may have the same frequency. Will.

  A sampling device for obtaining a strobed sample of the data signal under test or clock signal is shown in FIG. A start signal, such as a single strobe pulse, is generated by a conventional edge generator and applied to the delay line input 44. A series of delay elements outputs a start signal 48 in which the delay gradually increases. In the illustrated apparatus, a start signal 48 with progressively increasing delay is routed into an adder circuit 50 as known in the art to perform interpolation between delay elements, thereby A further signal 52 is provided with a further shortened start signal interval.

  In the exemplary apparatus, the summing circuit 50 includes summing elements 52, each summing element including a fine vernier-based Gilbert cell having eight settings (ie, 3-bit control). The setting can be adjusted to correct the delay line error. A speed control current for delay line element 46 is provided by delay lock loop 56. Each of the delayed signals with the input strobe pulse interval shortened is applied to the clock input of the corresponding D-latch 58. A data signal under test or synchronous clock signal 60 is routed as an input to each of the D-latches. As a result, the data stored in the D-latch represents a binary snapshot of the state of the data signal under test or the clock signal. In the exemplary apparatus, a set of 31 D-latches is used to obtain a 31-bit wide strobe representation of the signal under test.

  An apparatus for testing data signals in a DUT using a strobed representation of a synchronous clock will be described with reference to FIG. A signal under test 59 and a strobe 61 are applied to the sampling circuit 62. In the exemplary apparatus, sampling circuit 62 is the sampling apparatus described in detail with reference to FIG. An encoder circuit 64 in communication with the sampling circuit 62 receives from the sampling circuit 62 a short-interval strobe representation of the signal under test, which is converted to edge time and edge polarity (ie, high to low, Or from low to high). In that exemplary apparatus, the encoder converts 31-bit binary snapshots of edge transitions into 6-bit words. The most significant bit is used to represent the edge polarity and the remaining 5 bits are used to represent the edge time. The encoding described herein uses 6-bit words and 1-bit polarity representations for illustrative purposes, but many other word lengths can be used, and such data can be used using other schemes. Those skilled in the art will appreciate that data can be encoded long.

  In the exemplary apparatus of the present invention, a 6-bit word is output from the encoder at approximately 2 gigabytes / second. Using a demultiplexer 66 in communication with the encoder 64, the data is converted into 48 bit words with a data rate of 250 megabytes / second. The 48-bit word includes eight 5-bit data words representing edge time and its corresponding eight single polarity bits. Those skilled in the art will appreciate that demultiplexing may not be necessary in all cases and various other bit rates and / or demultiplexing details can be chosen.

  Using the router circuit 70, a signal representing the DUT synchronous clock is routed on the tester clock bus 72. Further, the routing circuit 70 selects only a clock edge time having one polarity in order to represent the system clock, that is, selects an edge time representing a clock set (rising polarity), and resets the clock (falling polarity). Is ignored. Thereby, clock edge times routed to the tester bus 72 can be used on multiple channels.

  The word output from the demultiplexer 66 representing the data signal of the DUT is not selected as a clock signal and is stored in the random access memory 68 as it is. In the exemplary device, data is stored in 96 × 40 random access memory. Those skilled in the art will appreciate that many other random access memory configurations can be used.

  The clock edge time on the tester bus 72 is used as a pointer for addressing data stored in the random access memory 68. The routing circuit 74 selects a clock on the bus used as a pointer, and routes the clock edge time to the comparison circuit 76. The comparison circuit 76 gives the clock edge time as an address to the random access memory 68, and reads the data edge time stored at the address. The data read from the random access memory is compared with the clock edge time, and the difference therebetween is determined.

  Comparison circuit 78 compares the expected value 77 of the difference between the data edge and the synchronous clock edge with the difference found by comparison circuit 76. The comparison circuit 78 outputs a pass / fail signal for each comparison depending on whether or not the difference from the prediction is within a specified limit.

  Accordingly, various embodiments of the multi-strobe test method and apparatus described herein provide a means for representing a signal under test in terms of its exact edge time and the polarity of the transition at the corresponding edge time. Can be provided. The edge time and polarity thus represented are stored for comparison with a timing signal, such as a synchronous clock of the device under test. The timing signal is also expressed in terms of its exact edge time. This representation of the timing signal edge time can be provided on a clock bus used throughout the test system, for example, to compare with a corresponding data signal edge time in a random access memory. The result of such comparison can be matched with expected values to determine whether the device under test is compliant with the test specification.

  One exemplary method of recovering clock information from a data signal is accomplished by adding steps to the method of testing and evaluating data generated by a synchronized clock described above with reference to FIG. Can do. An exemplary method for recovering clock information from a data signal is described generically with reference to FIG.

  A sampling step 82 is performed and the edge generator starts the input strobe. Using the strobe, a digital signal, such as the data signal of the device under test (DUT), is sampled to obtain a binary value of the state at a high rate. The resulting binary values provide a single shot series of samples of the digital signal at intervals of increasing delay.

  Edge time and edge polarity are detected in a single shot series. In an encoding step 84, the detected edge time and polarity are encoded into a binary word. In one implementation, the edge time to be encoded is represented as the lower 5 bits of a 6-bit word and the polarity is represented as the most significant bit.

  In one example of a high-speed test device using the exemplary method of the present invention, an encoded 6-bit word is generated at about 2 gigabytes per second. In order to provide a more suitable data rate for downstream storage and comparison steps, the encoded words can be demultiplexed to give a 48-bit word of only 250 megabytes per second. A 48-bit word represents eight 5-bit edge times and corresponding eight 1-bit edge polarities.

  A storage step 86 is performed and the encoded edge time is stored in memory. In the exemplary method, 96 × 40 random access memory is used to store the encoded edge time.

  An average accumulator step 88 is performed where the encoded edge time is accumulated over a number (N) of samples to determine an average edge time over N samples. Thereafter, an average adjustment step 90 is executed, and the average edge time is adjusted by the deskew value. In one exemplary embodiment, the deskew value is a constant value. In an optional write to bus step 92, the adjusted average can be written to the clock bus. The adjusted average represents the extracted clock.

  In memory access step 94, the adjusted average is used as a pointer to the memory address of the corresponding encoded data signal edge time. In a comparison step 96, the data edge time found in the memory at the address pointed to by the extracted clock is compared to the expected value, and the representative data signal edge time is a predetermined limit of the extracted clock time. It is determined whether it is within. In the last step 98, a pass / fail indication can thereby be generated automatically.

  One exemplary apparatus for extracting clock information from a digital signal adds components to an apparatus for testing a data signal in a DUT using a strobed representation of a synchronous clock described above with reference to FIG. I will explain. An exemplary apparatus for extracting clock information is described generically with reference to FIG.

  In the exemplary device, a digital signal 59 from the DUT is applied to the sampling circuit 62. A signal from the edge generator 61 is applied to the sampling circuit 62 as a second input. In the exemplary apparatus, sampling circuit 62 is the sampling apparatus described in detail with respect to FIG. The encoder circuit 64, demultiplexer 66, random access memory 68, comparator circuit 76, and comparator circuit 78, which operates to process the expected value 77 and output a pass / fail signal 80, are shown in FIG. It is configured and operates as described above with reference.

  Router circuit 100 can be used to derive the encoded edge time from demultiplexer 66 to accumulator 102. The accumulator 102 collects N samples of the encoded edge time and determines an average edge time over the N samples. An initial value register 104 in communication with the accumulator 102 stores the accumulator initial value and provides the initial value to the accumulator for calculating the average edge time. The clock delay data register 106 may be used to store the deskew value for synthesis with the average edge time provided by the accumulator 102 and adjust the average time as needed to provide an accurate pointer value. Using the adder circuit 108 in communication with the clock delay data register 106 and the accumulator 102, the deskew value and the average edge time determined by the accumulator 102 can be combined to form an adjusted average edge time. . The adjusted average edge time can be transmitted to the clock bus 72. The adjusted average edge time represents the extracted clock. The clock edge time thereby routed to the tester bus 72 can be used in multiple channels. However, when the extracted clock is only used locally, it is sent directly to the routing circuit 74, rather than being sent over the clock bus 72, and the routing circuit 74 is used to store the memory 68. The signal to be used for indicating is selected. This signal becomes a pointer to the random access memory.

  The extracted clock time from adder circuit 108 can be used as a pointer to address data stored in memory 68. The routing circuit 54 must select the local clock input from the adder circuit 108 and route this clock edge time to the comparison circuit 76. Further, the clock from adder circuit 108 can be routed to clock bus 72 and used as a clock for other channels as needed. The comparison circuit 76 gives the clock edge time as an address to the memory 68 and reads the data edge time stored at the address. The value read from the memory is compared with the clock edge time to determine the difference therebetween.

  Accordingly, various embodiments of the present invention provide a means for extracting a clock signal from a digital signal of a device under test by adding components to the multi-strobe apparatus described above. The clock extraction means can be used to supplement the multi-strobe test method, or operate alone and perform only the clock extraction operation.

  Although exemplary embodiments of the present invention have been described herein generically with respect to strobe pulses, the strobe pulses can be square wave signals, sine wave signals, triangular waves, impulses, etc. to trigger the corresponding latches. Those skilled in the art will appreciate that application of the threshold voltage in various waveform cycles can be included. For example, in an exemplary embodiment of the invention, it is contemplated that the leading edge (leading edge) of a square wave pulse can be used as a strobe pulse.

  While exemplary embodiments of the present invention have been described generally herein with reference to automated test equipment, those skilled in the art will appreciate that the present invention is useful in numerous other signal comparison operations. For example, the present invention will find utility with respect to extracting clock information from digital signals in numerous high-speed processing applications.

  It will be understood that various modifications may be made to the embodiments disclosed herein. Therefore, the above description should not be construed as limiting, but merely as exemplifications of various embodiments. Those skilled in the art will envision other modifications within the scope of the claims.

FIG. 3 is a functional block diagram of a method for testing a data signal or clock signal of a device under test using individual components of an exemplary embodiment of the present invention. FIG. 6 is a schematic timing diagram illustrating applying a strobe to a digital signal, according to an exemplary embodiment of the exemplary embodiment of the present invention. 1 is a schematic diagram of a multi-strobe sampler used in some exemplary embodiments of the invention. FIG. 1 is a schematic diagram of an apparatus for testing a data signal or clock signal of a device under test using individual components of an exemplary embodiment of the present invention. FIG. 3 is a functional block diagram of a method for recovering clock information from a digital signal according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of an apparatus for recovering clock information from a digital signal according to an exemplary embodiment of the present invention.

Claims (20)

A method for extracting a clock signal from a digital signal,
Applying a strobe including a plurality of strobe pulses to the digital signal;
Storing the state of the digital signal in the time of the strobe pulse of the strobe;
Encoding the stored state as a digital word, thereby identifying an edge time of state change of the digital signal;
Determining an average edge time over a predetermined number of samples of the digital word;
A method involving that. Storing the digital word in one memory location, and using the average edge time as a pointer to the memory location;
The method of claim 1, further comprising:   The method of claim 1, further comprising adding a deskew value to the average edge time to form an adjusted average edge time. Storing the digital word in one memory location, and using the adjusted average edge time as a pointer to the memory location;
The method of claim 3, further comprising:   The method further comprises: distributing the average edge time over a bus to a plurality of channels, wherein the adjusted average edge time is used as a pointer to a memory on a receiving channel of the plurality of channels. 4. The method according to 4. Comparing the data edge time at the memory location addressed by the adjusted average edge time with expected data, and providing a pass / fail indication as a result of the comparison;
The method of claim 4, further comprising: The strobe is
Applying each of the pulses of the strobe as a latch clock signal to a corresponding latch of the plurality of latches;
Applying the digital signal to a respective input of the latch; and receiving the state of the digital signal as a respective output of the latch;
The method of claim 1, wherein the method is applied to the digital signal.   As a result of the encoding, a multi-bit word is generated, the first part of the multi-bit word specifies the time of the state change, and the second part of the multi-bit word indicates the polarity of the state change. 2. The method of claim 1, wherein the method is specified.   The method of claim 8, further comprising demultiplexing the transmission of the multi-bit word to reduce its transmission rate.   The method of claim 1, wherein the digital signal comprises a data signal of a device under test. Applying an edge generator output signal to a delay circuit including a series of delay elements;
Connect between each of the delay elements to receive a copy of the edge of the sequentially delayed edge generator output signal, each copy of the sequentially delayed edge forming one of the strobe pulses. To
The method of claim 1, further comprising:   The method of claim 11, wherein the delay circuit is controlled by a delay lock loop, the delay element including a controllable summing element, the summing element being adjustable to correct a delay line error. An apparatus for extracting a clock signal from a digital signal,
A plurality of delay elements that communicate with the edge generator and increase strobe delay;
A plurality of latches, each having a clock supply input connected to a corresponding delay element of the delay element and a data input for receiving the data signal;
An encoder in communication with the plurality of latches, the encoder adapted to convert information stored in the plurality of latches into a digital word representing an edge time of the digital signal;
An averaging circuit adapted to receive a plurality of digital words from the encoder and determine an average thereof;
A device comprising: The averaging circuit is
An accumulator that communicates with the encoder and receives the digital word;
A clock delay data register for storing the deskew value;
An adder circuit in communication with the accumulator and the clock delay register;
14. The apparatus of claim 13, wherein the summing circuit is adapted to add the average edge time to the constant deskew value to form an extracted clock value.   The apparatus of claim 14, further comprising a memory in communication with the encoder, the memory being adapted to receive and store the digital word.   The apparatus of claim 15, further comprising a demultiplexing circuit in communication with the encoder and the memory, wherein the demultiplexing circuit is adapted to reduce a data transfer rate to the memory.   The apparatus of claim 15, wherein the digital signal is a data signal of a device under test.   16. The routing circuit of claim 15, further comprising a routing circuit adapted to communicate with the averaging circuit and the memory and to address the memory using the extracted clock value as a pointer to the memory. apparatus.   The apparatus of claim 15, wherein the routing circuit comprises a clock bus in communication with the averaging circuit and the memory, the routing circuit being adapted to communicate with a plurality of channels.   A comparator circuit in communication with the memory and adapted to compare an expected value corresponding to a particular clock time with a value of the data in the memory addressed by the extracted clock value; The apparatus of claim 15, comprising:

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