JP4916092B2 - Manufacturing method of semiconductor device - Google Patents

Description

This invention relates to a method of manufacturing a semiconductor device, more particularly, to a method of manufacturing a semiconductor device having a MIM (Metal Insulator Metal) structure of the capacitor (capacitive element).

  LSIs (Large Scale Integrated Circuits), known as semiconductor device representatives, are broadly divided into memory devices and logic devices, but with the recent advances in semiconductor manufacturing technology, large capacity has been achieved with a particularly simple structure. The former, which is composed of a dynamic random access memory (DRAM) capable of being developed, is remarkable. In addition, a mixed device in which both devices are combined is also used. Most of these devices are composed of MOS (Metal Oxide Semiconductor) type transistors which are excellent in integration.

  In the above-described DRAM, a memory cell selection transistor composed of a MOS transistor and a capacitor connected to the transistor for storing information according to the presence or absence of electric charge constitute one memory cell, and a plurality of memory cells are arranged in a matrix. Is arranged. Here, since the occupied area on the semiconductor substrate of the capacitor of each memory cell of the DRAM is restricted as the required storage information increases, it is necessary to devise a technique for increasing the capacity of each capacitor within the restricted occupied area. become. If the capacitor does not have a sufficient capacity for storing information, an error such as a soft error is likely to occur because a malfunction easily occurs due to an external noise signal or the like.

In order to increase the capacity of the DRAM capacitor as described above, a high dielectric constant insulating film made of a metal oxide such as zirconium oxide (ZrO ₂ ) or hafnium oxide (HfO ₂ ) has been conventionally used as a capacitive insulating film. In addition, a so-called MIM structure capacitor is provided which is formed using a metal nitride such as titanium nitride (TiN) which can be formed at a relatively low temperature (450 ° or less) as a lower electrode and an upper electrode. According to such a capacitor, since the lower electrode and the upper electrode can be formed at a relatively low temperature on the capacitor insulating film made of the high dielectric constant insulating film, the logic portion formed in advance of the capacitor, particularly in a hybrid device. A high-capacitance capacitor can be formed without thermally affecting the capacitor. A DRAM including a capacitor having such a configuration is disclosed in Patent Document 1, for example.

Here, when the lower electrode and the upper electrode are formed in the capacitor insulating film made of a high dielectric constant insulating film such as ZrO ₂ or HfO ₂ in the capacitor having the MIM structure as described above, an organic metal containing Ti (Metal 0rganic) ) A CVD (Chemical Vapor Deposition) method using a material, that is, a so-called MOCVD method is widely used. For example, Patent Document 2 discloses a method of depositing TiN used as a barrier metal by MOCVD using tetradimethylamino titanium (TDMAT) as an organometallic material containing Ti.

However, as described in Patent Document 2, an organic component containing carbon (C) atoms tends to be taken into a TiN film formed by the MOCVD method. In order to release these components out of the film as much as possible, a plasma treatment is performed. By such plasma treatment, these components can be released as much as possible outside the TiN film, so that the film can be modified into a dense and low resistance film. Such plasma treatment is conventionally performed using a mixed gas of nitrogen (N ₂ ) gas and hydrogen (H ₂ ) gas.

Another way to increase the capacity of a DRAM capacitor is to increase the surface area of the upper and lower electrodes of the capacitor to various types of three-dimensional structures such as a cylinder type, a box type, and a fin type. To be formed. Further, by combining such a three-dimensional structure and a capacitive insulating film made of a high dielectric constant insulating film, the capacitance of the capacitor can be further increased.
JP 2002-373945 A JP 2001-326192 A

By the way, in the conventional semiconductor device and the manufacturing method thereof, when forming a capacitor having an MIM structure, if a plasma treatment is performed after forming a TiN film by MOCVD in order to form an upper electrode on the capacitor insulating film, the capacitance of the capacitor There is a problem that characteristics deteriorate.
That is, as shown in Patent Document 2, conventionally, plasma processing after forming a TiN film by MOCVD is performed using a mixed gas of N ₂ gas and H ₂ gas. Capacitance characteristics are deteriorated because the capacitor insulating film already formed at the time of processing deteriorates due to plasma damage (reduction of the capacitor insulating film) due to the H ₂ gas and thermal damage due to the wafer temperature rising due to plasma processing. Get worse.

FIG. 15 is a diagram showing a specific example in which the capacitance characteristic of the capacitor is deteriorated. N ₂ : H ₂ = 200 SCCM (Standard Cubic Centimeter per Minute): 300 SCCM (flow rate ratio 2: 3) after the TiN film is formed by the MOCVD method. It is a figure which shows the relationship between the applied voltage (horizontal axis) and the leakage current value (vertical axis) with respect to the capacitor obtained by performing plasma processing using mixed gas. The capacitor is shown as an example measured using a plurality of (57 as an example) capacitors formed on the same semiconductor substrate (wafer). In FIG. 15, the plus side shows the characteristics obtained by applying a plus voltage to the upper electrode of the capacitor and applying a 0 voltage to the lower electrode. On the other hand, the minus side shows characteristics obtained by applying a minus voltage to the upper electrode of the capacitor and applying a 0 voltage to the lower electrode. As is apparent from FIG. 15, the leakage current values of the plurality of capacitors vary greatly within the wafer, indicating that the uniformity within the wafer surface is degraded. In addition, the leakage current value of each capacitor is large on average.

The present invention has been made in view of the above-described circumstances, and is a semiconductor device capable of preventing deterioration in capacitance characteristics of a capacitor having an MIM structure even if plasma treatment is performed after forming a metal compound film by MOCVD . The object is to provide a manufacturing method .

In order to solve the above-mentioned problems, a first aspect of the present invention relates to a method for manufacturing a semiconductor device, the step of forming a lower electrode, the step of forming a capacitive insulating film on the lower electrode, and the capacitive insulation. Forming an upper electrode made of a titanium nitride film on the film, and forming a capacitor having an MIM structure. The step of forming the titanium nitride film, the titanium nitride film, and the flow rate of the titanium nitride film A film is formed by MOCVD using a process gas having a ratio of hydrogen gas / nitrogen gas ≦ 0.5 and repeating a plasma process at a plasma power of 550 W or more.

The invention according to claim 2 relates to a method of manufacturing a semiconductor device, the step of forming a lower electrode, the step of forming a capacitive insulating film on the lower electrode, and titanium nitride on the capacitive insulating film. Forming a MIM structure capacitor, and forming the titanium nitride film, the titanium nitride film, and the titanium nitride film at a flow rate ratio of hydrogen gas / nitrogen. The process of forming a film by the MOCVD method, which repeats the step of performing plasma processing with a predetermined plasma power using a processing gas having a gas ≦ 0.5, and the step of performing the plasma processing includes the first plasma processing step, And a second plasma treatment step, wherein the plasma power of the first plasma treatment is 100 W or less, the plasma power of the second plasma treatment is 550 W or more, and the second plasma treatment is performed. The processing time of the plasma treatment process is characterized in that set longer than that of the first plasma treatment step.

According to a third aspect of the invention, there is provided the method for manufacturing a semiconductor device according to the first or second aspect , wherein after the step of forming the titanium nitride film, the titanium nitride film is plasma-treated using nitrogen gas. It has the process.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first, second, or third aspect , the number of repetitions is set to 2 to 4 in the step of forming the upper electrode of the capacitor. It is characterized by that.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourth aspect, the film thickness formed per time is 2 to 15 nm in the step of forming the upper electrode of the capacitor. It is characterized by that.

A sixth aspect of the invention relates to a method of manufacturing a semiconductor device according to any one of the first to fifth aspects, wherein the titanium nitride film has a flow rate ratio of hydrogen gas / nitrogen gas ≦ 0.5. In the step of performing the plasma treatment using a treatment gas at a plasma power of 550 W or more, only nitrogen gas is used.

A seventh aspect of the invention relates to a method of manufacturing a semiconductor device according to any one of the first to sixth aspects, wherein the titanium nitride film has a flow rate ratio of hydrogen gas / nitrogen gas ≦ 0.5. The step of performing the plasma treatment using a treatment gas is characterized in that the plasma treatment is performed at a plasma power of 550 W to 950 W.

The invention according to claim 8 relates to the method of manufacturing a semiconductor device according to any one of claims 1 to 7 , wherein tetradimethylamino titanium (TDMAT) is used as a raw material gas containing titanium. It is said.

According to a ninth aspect of the present invention, there is provided the method of manufacturing a semiconductor device according to any one of the first to eighth aspects, wherein the capacitive insulating film is formed in the step of forming the capacitive insulating film on the lower electrode. And an insulating film having at least one of zirconium oxide, hafnium oxide, aluminum oxide, titanium oxide, and tantalum oxide is formed.

A tenth aspect of the present invention relates to a method for manufacturing a semiconductor device according to any one of the first to ninth aspects, wherein a tungsten film is formed on the upper electrode by a CVD method using tungsten fluoride as a source gas. The method further includes the step of:

According to the semiconductor device manufacturing method of the present invention, the capacitor insulating film is formed using the semiconductor substrate on which the lower electrode of the MIM structure capacitor is formed. Next, an upper electrode of the capacitor is formed by repeating a step of forming a TiN film on the capacitor insulating film by MOCVD and a step of plasma-treating the TiN film using a gas containing nitrogen gas. Plasma treatment after TiN film formation is performed by using only nitrogen gas or by using a gas obtained by mixing hydrogen gas with nitrogen gas with a flow rate ratio of hydrogen gas / nitrogen gas ≦ 0.5. Since the capacitance insulating film already formed is sometimes not affected by the plasma action or annealing action by hydrogen gas, the capacitance characteristics of the capacitor can be improved. The composition of the TiN film constituting the upper electrode after the plasma treatment described above is such that C is 25 to 36%, N is 60 to 72%, and O is 28 to 35% with respect to 100% Ti (atomic ratio). (In other words, the atomic ratio of titanium 43 to 45%, carbon 11 to 16%, nitrogen 27 to 31%, oxygen 12 to 15%). A semiconductor device that can be improved can be obtained.

Forming a capacitor lower electrode on the semiconductor substrate; forming a capacitor insulating film on the lower electrode; forming a metal compound film on the capacitor insulating film by MOCVD; The upper electrode of the capacitor is formed by repeating the plasma treatment process using a gas containing gas. By such a method for manufacturing a semiconductor device, the composition ratio (in other words , carbon is 25 to 36%, nitrogen is 60 to 72%, and oxygen is 28 to 35% with respect to 100% titanium (atomic ratio) . An upper electrode made of a TiN film having a composition ratio of 43 to 45% titanium, 11 to 16% carbon, 27 to 31% nitrogen, and 12 to 15% oxygen is formed.

1 to 4 are process diagrams showing a semiconductor device manufacturing method according to the first embodiment of the present invention in the order of steps. FIG. 5 shows a method for forming a lower electrode of a capacitor having an MIM structure in the semiconductor device manufacturing method. FIG. 6 is a flowchart showing a method of forming a capacitor insulating film of an MIM structure capacitor in the manufacturing method of the semiconductor device. FIG. 7 is a flowchart of forming an upper electrode of the MIM structure capacitor in the manufacturing method of the semiconductor device. FIG. 8 is a flowchart showing the relationship between the applied voltage (horizontal axis) and the leakage current value (vertical axis) applied to the MIM structure capacitor formed by the semiconductor device manufacturing method, and FIG. The relationship between the leakage current value (horizontal axis) and the cumulative probability (vertical axis) of the capacitor with the MIM structure formed by the semiconductor device manufacturing method is compared with the conventional example. Shown Figure 10 shows the case of forming a capacitor of the MIM structure by the manufacturing method of the semiconductor device, the flow rate of H ₂ gas contained in the plasma processing gas during top electrode formed (horizontal axis) and the leakage current value (vertical axis) FIG. 11 is a diagram showing the relationship between the flow rate of H ₂ gas (horizontal axis) contained in the plasma processing gas during the formation of the upper electrode and the TiN film in the case of forming a capacitor with an MIM structure by the semiconductor device manufacturing method. FIG. 12 is a diagram showing a relationship with the composition (vertical axis), and FIG. 12 shows a leakage current value for a capacitor formed by changing plasma processing conditions when a capacitor having an MIM structure is formed by the manufacturing method of the semiconductor device. It is a figure which shows the relationship between a horizontal axis) and a cumulative probability (vertical axis). In this example, an example in which a capacitor having an MIM structure is formed in a cylindrical three-dimensional structure will be described. Hereinafter, with reference to FIGS. 1 to 4, the manufacturing method of the semiconductor device of this example will be described in the order of steps.

First, as shown in FIG. 1A, after an element isolation insulating film 2 made of a silicon dioxide (SiO ₂ ) film is formed on, for example, a P-type silicon substrate 1 by a well-known STI (Shallow Trench Isolation) method or the like. Then, an SiO ₂ film and a polycrystalline silicon film are sequentially formed in an active region surrounded by the element isolation insulating film 2, and these films are patterned into a desired shape to form a gate oxide film 3 and a gate electrode (word Line) 4 is formed. Next, by self-alignment using the gate oxide film 3 and the gate electrode 4 as a mask, N-type impurities are introduced into the silicon substrate 1 by a well-known impurity introduction method such as an ion implantation method, so that a plurality of source regions or drain regions are formed. The N type diffusion region 5 is selectively formed. Next, a first interlayer insulating film 6 made of a SiO ₂ film is formed on the entire surface by plasma CVD.

  As a result, a memory cell selection transistor 10 composed of a MOS transistor is formed by the gate oxide film 3, the gate electrode 4, and the plurality of N-type diffusion regions 5. Here, even if the plurality of N-type diffusion regions 5 constituting the source region or the drain region have an LDD (Lightly Doped Drain) structure in which a high impurity concentration region and a low impurity concentration region are combined, A non-LDD structure having only a concentration region may be employed. Next, using photolithography, the first interlayer insulating film 6 is selectively plasma etched to form the contact hole 7 so as to expose the N-type diffusion region 5.

  Next, as shown in FIG. 1B, a TiN film 8 as a barrier metal is formed on the entire surface by CVD or PVD (Physical Vapor Deposition), and then a W (tungsten) film 9 is formed on the entire surface by CVD. After the film formation, the surface of the first interlayer insulating film 6 is planarized by CMP (Chemical Mechanical Polishing) method to remove unnecessary TiN film 8 and W film 9, and the N-type diffusion region 5 and the contact hole 7 are formed in the contact hole 7. A capacitor contact 11 and a bit contact 12 are formed so as to be connected to each other.

Next, as shown in FIG. 1C, a stopper insulating film 13 made of a silicon oxynitride (SiON) film and a second interlayer insulating film 14 made of a SiO ₂ film are sequentially formed on the entire surface by plasma CVD. . Next, a capacitor having an MIM structure is formed by the following method.

First, a lower electrode of a capacitor is formed by a process step according to a flowchart as shown in FIG.
First, as shown in FIG. 2D, the second interlayer insulating film 14 is selectively plasma etched by using a photolithography method to form a cylinder groove 15 so as to expose the capacitor contact 11 (see FIG. 2D). Step S1). Plasma etching was performed under the following conditions.
Etching gas: Ar
・ Plasma power: 100-1000W
・ Etching amount: 1 ~ 20nm

Next, TDMAT is deposited by MOCVD (step S2).
Deposition was performed under the following conditions.
・ Raw material gas: TDMAT
・ Raw material bubbling gas: He (100-500 SCCM)
Carrier gas: He (100 to 500 SCCM) and N ₂ (100 to 500 SCCM)
・ Chamber pressure: 0.1 to 10 Torr (Torricelli))
・ Deposition temperature (setting): 370-480 °
・ Deposition time: 5 ~ 20sec (second)
・ Film thickness: 2-15nm

Next, preliminary plasma processing is performed (step S3). The preliminary plasma treatment was performed under the following conditions.
Preliminary plasma processing gas: N ₂ (100 to 500 SCCM) and H ₂ (100 to 500 SCCM)
・ Chamber pressure: 0.1 ~ 10Torr
・ Processing time: 3sec
・ Plasma power: 0-100W

Next, this plasma processing is performed (step S4). This plasma treatment was performed under the following conditions.
・ This plasma processing gas: N ₂ (100 to 500 SCCM) and H ₂ (100 to 500 SCCM)
・ Chamber pressure: 0.1 ~ 10Torr
・ Processing time: 15 ~ 90sec
・ Plasma power: 550-950W

Next, a purge process is performed (step S5). The purge process was performed under the following conditions.
・ Purge processing gas: N ₂ (100 to 700 SCCM) and H ₂ (100 to 500 SCCM)
・ Purge time: 15 sec
Thereafter, by repeating (Step S2) to (Step S5) 4 to 8 times, the lower electrode 16 made of a TiN film having a thickness of 20 to 40 nm is formed in the cylinder groove 15 as shown in FIG. Formed.

Next, a capacitor insulating film of the capacitor is formed by a process step according to a flowchart as shown in FIG. In this example, ZrO ₂ is formed as a capacitor insulating film.
First, Zr is deposited by one atomic layer (pulse) using TEMAZ (tetraethylmethylaminozirconium) as a source gas containing Zr by an ALD (Atomic Layer Deposition) method (step S11). Deposition was performed under the following conditions.
・ Raw material gas: TEMAZ
・ Raw material bubbling gas: He
・ Chamber pressure: 0.1 ~ 10Torr
・ Deposition temperature (setting): 250-380 °
・ Deposition time: 1-10sec

Next, the source gas is purged (step S12). Purge was performed under the following conditions.
・ Purge gas: Ar
・ Purge time: 1 to 10 seconds

Next, an oxidizing agent is supplied (step S13). The oxidizing agent was supplied under the following conditions.
・ Oxidizing agent: O ₃
・ Oxidant concentration: 100-500 g / m ³
・ Chamber pressure: 0.1 ~ 10Torr
・ Supply time: 0.1-10sec

Next, purge of O ₃ gas is performed (step S14). Purge was performed under the following conditions.
・ Purge gas: Ar
・ Purge time: 1 to 10 seconds
Thereafter, by repeating (Step S11) to (Step S14) 50 to 150 times, as shown in FIG. 2 (f), the capacitive insulating film 17 made of ZrO2 having a thickness of 5 to 15 nm is formed on the lower electrode 16. Formed.

Next, the upper electrode of the capacitor is formed by a process step according to the flowchart shown in FIG.
First, TDMAT is deposited by MOCVD (step S21).
Deposition was performed under the following conditions.
・ Raw material gas: TDMAT
・ Raw material bubbling gas: He (100-500 SCCM)
Carrier gas: He (100 to 500 SCCM) and N ₂ (100 to 500 SCCM)
・ Chamber pressure: 0.1 ~ 10Torr
・ Deposition temperature (setting): 370-480 °
・ Deposition time: 5 to 20 seconds
・ Film thickness: 2-15nm

Next, preliminary plasma processing is performed (step S22). The preliminary plasma treatment was performed under the following conditions.
・ Preliminary plasma processing gas: N ₂ (100 to 500 SCCM)
・ Chamber pressure: 0.1 ~ 10Torr
・ Processing time: 3sec
・ Plasma power: 0-100W

Next, the plasma processing is performed (step S23). This plasma treatment was performed under the following conditions.
・ Plasma processing gas: N ₂ (100-500 SCCM)
・ Chamber pressure: 0.1 ~ 10Torr
・ Processing time: 10 ~ 120sec
・ Plasma power: 550-950W

Next, a purge process is performed (step S24). The purge process was performed under the following conditions.
・ Purge processing gas: N ₂ (100 to 700 SCCM) and He (100 to 500 SCCM)
・ Purge time: 15 sec
Thereafter, by repeating (Step S21) to (Step S24) 2 to 4 times, as shown in FIG. 3G, the upper electrode 18 made of a TiN film having a thickness of 20 to 40 nm is formed on the capacitive insulating film 17. Formed. Thereby, a capacitor 19 having an MIM structure is formed by the lower electrode 16, the capacitor insulating film 17 and the upper electrode 18.
Here, when the thickness of the upper electrode 18 is thinner than 20 nm, the barrier property of the TiN film is lowered. On the other hand, even if it is thicker than 40 nm, the improvement of the characteristics is not recognized, and the productivity increases as the thickness increases. In order to obtain a high barrier property, it is necessary to form a dense film, and considering the productivity, it is preferable to repeat the plasma treatment step after forming a thin film to some extent, specifically 2-15 nm. / Times is preferably 2 to 4 times. Further, the film thickness formed per time does not necessarily have to be the same value.

  Next, as shown in FIG. 3H, a capacitor wiring 20 made of a W film is formed on the entire surface by a CVD method and connected to the upper electrode 18 of the capacitor 19. Next, as shown in FIG. 3I, an opening 21 is formed so as to expose the second capacitor insulating film 14 above the bit contact 12.

Next, as shown in FIG. 4 (j), a third interlayer insulating film 22 made of a SiO ₂ film is formed on the entire surface by plasma CVD, and then the third interlayer insulating film 22 is formed using photolithography. A contact hole 23 is formed in the opening 21 so that the bit contact 12 is exposed by selective plasma etching.

Next, as shown in FIG. 4 (k), a TiN film 24 as a barrier metal is formed on the entire surface by MOCVD, and then a source gas (WF ₆ : tungsten fluoride) containing fluorine (F) is used by CVD. Then, a bit wiring 25 made of a W film is formed on the entire surface so as to be connected to the bit contact 12, thereby completing a DRAM including the capacitor 19 having the MIM structure.
Here, according to this example, by forming the upper electrode 18 made of the TiN film, the barrier property of the TiN film is improved. Therefore, when the W film is formed by the CVD method as described above, the source gas is capacitively insulated. Damage to the film 17 can be suppressed.

FIG. 8 shows a capacitor obtained by performing the preliminary plasma treatment and the main plasma treatment using only the N ₂ gas (flow rate: 100 to 500 SCCM) after forming the TiN film by the MOCVD method by the semiconductor device manufacturing method of this example. It is a figure which shows the relationship between the applied voltage (horizontal axis) and the leakage current value (vertical axis). Note that the capacitor is shown as an example measured using a plurality (57 as an example) of capacitors formed on the same semiconductor substrate. As is apparent from the comparison of the characteristics of FIG. 8 with those of the conventional example of FIG. 15, the capacitor obtained in this example has a leakage current value of a plurality of capacitors in both the positive and negative characteristics. In addition, not only the uniformity within the wafer surface is improved, but also the leakage current value is reduced.

  FIG. 9 is a diagram showing the relationship between the leakage current value of the capacitor (horizontal axis) and the cumulative probability (vertical axis) based on FIG. 8, and the voltage applied to the capacitor in an actual device minus 0.7V. The characteristic of 57 capacitors when applying is plotted. In FIG. 9, A shows the characteristics of this example, and B shows the characteristics of the conventional example. The characteristics in FIG. 9 indicate that the steep slope has a smaller variation in the leakage current value in the wafer. Further, the one located on the left side of the illustrated characteristic indicates that the leak current value is small. Therefore, as is apparent from FIGS. 8 and 9, according to this example, both the wafer in-plane uniformity and the leakage current value are superior to the conventional example, and the capacitance characteristics of the capacitor are improved. Is understood.

As described above, the capacitance characteristic of the capacitor can be improved by this example because only the N ₂ gas is used as the plasma processing gas except for the H ₂ gas during the plasma processing after the TiN film is formed by the MOCVD method. This is probably because the capacitive insulating film 17 already formed at the time of the plasma treatment is not affected by the plasma action or the annealing action by the H ₂ gas, and as a result, the damage is alleviated and no longer deteriorates.

More specifically, the TiN film formation by the MOCVD method is suppressed to a film thickness that does not impair the film quality, and immediately after this, plasma treatment using only N ₂ gas (preliminary plasma treatment + main plasma treatment) is performed. as TiN film formation step and the plasma treatment step of one cycle, since the repeated several cycles until the upper electrode obtained consisting of the desired thickness of the TiN film, the capacitor insulating film 17 affected by H ₂ gas It is considered that the capacitance characteristics of the capacitor could be improved.

Here, the plasma processing gas described above is not necessarily limited to only N ₂ gas, and if the H ₂ gas is within a certain flow ratio with respect to the N ₂ gas, it is satisfactory as a capacitor even if it is used as a mixed gas. It was confirmed that the capacity characteristics can be obtained. FIG. 10 shows the flow rate (horizontal axis) of the H ₂ gas contained in the plasma processing gas and the leakage current value when forming the TiN film serving as the upper electrode when the MIM structure capacitor is formed by the semiconductor device manufacturing method of this example. The relationship with (vertical axis) is shown. FIG. 11 shows the flow rate of H ₂ gas (horizontal axis) and TiN contained in the plasma processing gas when forming the TiN film serving as the upper electrode when the MIM structure capacitor is formed by the semiconductor device manufacturing method of this example. The relationship with the composition (vertical axis) of the film is shown.

As is clear from FIG. 10, when H ₂ gas is mixed up to 100 SCCM with respect to N ₂ gas 200 SCCM as the plasma processing gas (flow rate ratio 2: 1), the leakage current in both positive and negative characteristics. This indicates that the value can be suppressed within a preset standard value so as to be lower than that of the conventional example, and the capacitance characteristic of the capacitor can be improved. As is clear from FIG. 11, as described above, in the case of a capacitor formed by plasma processing by mixing H ₂ gas up to 100 SCCM with N ₂ gas 200 SCCM as the plasma processing gas, the upper electrode is The composition (ratio) of the constituting TiN film is such that C is 25 to 36%, N is 60 to 72%, and O is 28 to 35% with respect to 100% Ti (atomic ratio). ing. Further, the composition ratio is different between the upper surface side and the lower surface side of the upper electrode. That is, with respect to 100% Ti, C is 25 to 36%, N is 60 to 72%, and O is 28 to 35% (in other words, the atomic ratio is titanium 43 to 45%, carbon 11 to 16). It shows that the capacitance characteristics of the capacitor can be improved by forming the upper electrode 18 made of a TiN film having a composition ratio of%, nitrogen 27-31%, oxygen 12-15% .

The capacity characteristic of the capacitor is the best when N ₂ gas alone is used. Titanium is very compatible with oxygen, so it is easy to form titanium oxide. Therefore, oxygen in the capacitor insulating film can move to the portion where carbon in the upper electrode is extracted by H ₂ plasma, whereas carbon in the upper electrode is not extracted in the case of only N ₂ plasma. It is presumed that oxygen in the insulating film is not deprived and capacity characteristics are improved accordingly. Further, when a tungsten film is formed by CVD using a source gas (WF ₆ ) containing fluorine on the upper electrode, since the barrier property of the upper electrode film is high, damage to the capacitor insulating film can be suppressed. Presumed.

As described above, when the TiN film forming step and the plasma processing step are set as one cycle and a plurality of cycles are repeated until an upper electrode 18 made of a TiN film having a desired thickness is obtained, the number of cycles is not much. It was confirmed that the increase is not preferable. FIG. 12 shows this state when a gas in which N ₂ gas 200 SCCM is mixed with H ₂ gas 100 SCCM gas is used. Characteristic C is obtained when the number of cycles is repeated three times, and characteristic D is obtained when the number of cycles is six times. The repeated case is shown. The reason why the characteristics are worse in the case of repeating 6 times is presumed that the damage by H ₂ plasma is increased. As described above, a desirable capacity characteristic can be obtained by repeating the number of cycles 2 to 4 times.

Thus, according to the semiconductor device of this example, in the semiconductor device including the capacitor 19 having the MIM structure formed by forming the lower electrode 16 and the upper electrode 18 made of the TiN film on the capacitive insulating film 17 made of the ZrO ₂ film, Capacitance characteristics of the capacitor are improved by forming the upper electrode 18 made of a TiN film having a composition ratio of C 25 to 36%, N 60 to 72%, and O 28 to 35% with respect to 100% Ti. A semiconductor device that can be obtained can be obtained.
Further, according to the method of manufacturing the semiconductor device of this example, after forming the capacitive insulating film 17 made of the ZrO ₂ film using the semiconductor substrate on which the lower electrode 16 of the capacitor 19 having the MIM structure is formed, the TiN film is formed by the MOCVD method. And a step of plasma-treating the TiN film using only nitrogen gas or using a gas in which hydrogen gas / nitrogen gas ≦ 0.5 at a flow ratio is mixed with hydrogen gas. Thus, the upper electrode 18 made of the TiN film having the composition ratio as described above is formed.
Therefore, it is possible to prevent the capacitance characteristics of the capacitor having the MIM structure from being deteriorated even if plasma treatment is performed after the TiN film is formed by the MOCVD method.

The second embodiment of the present invention is characterized in that a capacitive insulating film made of HfO ₂ is formed as a capacitive insulating film. Other than this, the configuration is substantially the same as that of the above-described first embodiment, and thus the description thereof is omitted.
In the manufacturing method of the semiconductor device of this example, first, as shown in FIG. 2E of Example 1, the substrate in which the lower electrode 16 made of a TiN film having a thickness of 20 to 40 nm is formed in the cylinder groove 15. Prepare 1
Next, Hf is deposited by one atomic layer (pulse) using TEMAH (tetraethylmethylaminohafnium) as a source gas containing Hf by the ALD method (step 1). Deposition was performed under the following conditions.
・ Raw material gas: TEMAH
・ Raw material bubbling gas: Ar
・ Deposition temperature (setting): 250-380 °
・ Deposition time: 1-10sec

Next, the source gas is purged (step 2). Purge was performed under the following conditions.
・ Purge gas: Ar
・ Purge time: 1 to 10 seconds

Next, an oxidizing agent is supplied (step 3). The oxidizing agent was supplied under the following conditions.
・ Oxidizing agent: O ₃
・ Oxidant concentration: 100-500 g / m ³
・ Supply time: 0.1-10sec

Next, O ₃ gas is purged (step 4). Purge was performed under the following conditions.
・ Purge gas: Ar
・ Purge time: 1 to 10 seconds
Thereafter, by repeating (Step 1) to (Step 4) 50 to 150 times, a film thickness of 5 to 15 nm is formed on the lower electrode 16 in substantially the same manner as shown in FIG. A capacitor insulating film (corresponding to the capacitor insulating film 17) made of HfO ₂ was formed.
In the following, the DRAM having the MIM structure capacitor 19 is completed by repeating substantially the same steps as those in FIGS. 3G to 4K of the first embodiment.

  As described above, the configuration of this example is different from that of the first embodiment only in the type of the capacitive insulating film, so that substantially the same effect as that of the first embodiment can be obtained.

FIG. 13 is a flowchart showing a method of forming the upper electrode of the capacitor having the MIM structure in the method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 14 is a flowchart showing the method for forming the MIM structure formed by the method for manufacturing the semiconductor device. It is a figure which shows the relationship between the leakage current value (horizontal axis) of a capacitor, and an accumulation probability (horizontal axis) compared with a prior art example. The configuration of the semiconductor device manufacturing method according to the third embodiment is greatly different from that of the first embodiment described above. After the conventional plasma processing is repeated several times, the final plasma processing is performed using only N ₂ gas. It is a point that I tried to do.
In the manufacturing method of the semiconductor device of this example, first, as shown in FIG. 2F of Example 1, a capacitive insulating film 17 made of ZrO ₂ having a thickness of 5 to 15 nm was formed on the lower electrode 16. A substrate 1 is prepared.

Next, the upper electrode of the capacitor is formed by a process step according to the flowchart shown in FIG.
First, TDMAT is deposited by MOCVD (step S31).
Deposition was performed under the following conditions.
・ Raw material gas: TDMAT
・ Raw material bubbling gas: He (100-500 SCCM)
Carrier gas: He (100 to 500 SCCM) and N ₂ (100 to 500 SCCM)
・ Chamber pressure: 0.1 ~ 10Torr
・ Deposition temperature (setting): 370-480 °
・ Deposition time: 5 to 20 seconds
・ Film thickness: 2-15nm

Next, preliminary plasma processing is performed (step S32). The preliminary plasma treatment was performed under the following conditions.
Preliminary plasma processing gas: N ₂ (100 to 500 SCCM) and H ₂ (100 to 500 SCCM)
・ Chamber pressure: 0.1 ~ 10Torr
・ Processing time: 3sec
・ Plasma power: 0-100W

Next, the plasma processing is performed (step S33). This plasma treatment was performed under the following conditions.
・ This plasma processing gas: N ₂ (100 to 500 SCCM) and H ₂ (100 to 500 SCCM)
・ Chamber pressure: 0.1 ~ 10Torr
・ Processing time: 10 ~ 120sec
・ Plasma power: 550-950W

Next, a purge process is performed (step S34). The purge process was performed under the following conditions.
・ Purge processing gas: N ₂ (100 to 700 SCCM) and He (100 to 500 SCCM)
・ Purge time: 15 sec
Thereafter, (Step S31) to (Step S34) are repeated 1 to 3 times.

Next, TDMAT is deposited by MOCVD (step S35).
Deposition was performed under the following conditions.
・ Raw material gas: TDMAT
・ Raw material bubbling gas: He (100-500 SCCM)
Carrier gas: He (100 to 500 SCCM) and N ₂ (100 to 500 SCCM)
・ Chamber pressure: 0.1 ~ 10Torr
・ Deposition temperature (setting): 370-480 °
・ Deposition time: 5 to 20 seconds
・ Film thickness: 2-15nm

Next, preliminary plasma processing is performed (step S36). The preliminary plasma treatment was performed under the following conditions.
・ Preliminary plasma processing gas: N ₂ (100 to 500 SCCM)
・ Chamber pressure: 0.1 ~ 10Torr
・ Processing time: 3sec
・ Plasma power: 0-100W

Next, the plasma processing is performed (step S37). This plasma treatment was performed under the following conditions.
・ Plasma processing gas: N ₂ (100-500 SCCM)
・ Chamber pressure: 0.1 ~ 10Torr
・ Processing time: 10 ~ 120sec
・ Plasma power: 550-950W

Next, a purge process is performed (step S38). The purge process was performed under the following conditions.
・ Purge processing gas: N ₂ (100 to 700 SCCM) and He (100 to 500 SCCM)
・ Purge time: 15 sec

As described above, the upper electrode 18 made of a TiN film having a thickness of 20 to 40 nm was formed on the capacitor insulating film 17 in substantially the same manner as that shown in FIG. Thereby, a capacitor 19 having an MIM structure is formed by the lower electrode 16, the capacitor insulating film 17 and the upper electrode 18.
In the following, a DRAM having the MIM structure capacitor 19 is completed by repeating substantially the same steps as those of the first embodiment shown in FIGS. 3 (h) to 4 (k).

  As is apparent from FIG. 14 showing the relationship between the leakage current value (horizontal axis) and the cumulative probability (horizontal axis) of the capacitor 19 having the MIM structure formed by the semiconductor device manufacturing method of this example in comparison with the conventional example. In the characteristic E of this example, the variation of the leakage current value in the wafer is smaller than that of the characteristic F of the conventional example, the leakage current value is small, and the capacitance characteristic of the capacitor is improved. Is understood.

Thus, according to the semiconductor device manufacturing method of this example, the capacitor characteristics are improved even if the final plasma treatment is performed using only N ₂ gas after the plasma treatment under the conventional conditions is repeated several times. can do.
Therefore, substantially the same effect as that of the first embodiment can be obtained.

As shown in each example, when the plasma treatment is performed with N ₂ gas after the TiN film is formed, the plasma treatment is performed for a longer time following the preliminary plasma treatment, thereby improving the capacity characteristics. Can be improved. For example, when film formation and plasma processing are repeated, the capacity characteristics can be further improved by increasing the plasma processing time of only the final layer (for example, the processing time of 30 seconds is usually 60 seconds and 90 seconds). it can. Also, in the example in which the final layer is plasma-treated with N ₂ gas following the plasma treatment with a mixed gas of N ₂ gas and H ₂ gas, the capacity characteristics are similarly improved by extending the plasma treatment time. be able to.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and the present invention can be changed even if there is a design change or the like without departing from the gist of the present invention. include. For example, in the embodiments, a DRAM is described as an example of a semiconductor device including a capacitor having an MIM structure, but the present invention is not limited to this, and the present invention can also be applied to a semiconductor device in which a DRAM and a logic device are mixedly mounted. In addition, the memory cell selection transistor constituting the DRAM is not limited to the MOS type transistor, but is insulated with other structures such as a nitride film (Nitride Film) or a double film of an oxide film and a nitride film as a gate insulating film. A MIS (Metal Insulator Semiconductor) type transistor using a film may be used.

In addition, although an example in which TEMAZ is used as a raw material gas when forming ZrO ₂ as a capacitive insulating film by the ALD method is shown, it is not limited to this and TDAZ (tetradiethylaminozirconium), TDMAZ (tetradimethylaminozirconium), etc. Other ingredients can be used. Similarly, as an example of using TEMAH as a raw material gas when HfO ₂ is formed as a capacitive insulating film by the ALD method, the material gas is not limited to this, but is limited to TDEAH (tetradiethylaminohafnium), TDMAH (tetradimethylaminohafnium). Other raw materials can be used. Further, the method for forming the capacitor insulating film is not limited to the ALD method, and other methods such as a CVD method and a PVD method can be used.

Further, the capacitive insulating film is formed by stacking or mixing ZrO ₂ and Al ₂ O ₃ (aluminum oxide), stacking or mixing HfO ₂ and Al ₂ O ₃ , stacking or mixing ZrO ₂ and TiO ₂ (titanium oxide), HfO ₂ or TiO ₂ may be laminated or mixed. Moreover, although the example which uses TiN was shown as a metal compound film which comprises an upper electrode, it is not restricted to this, Other materials like tantalum nitride (TaN) formed using pentaethoxy tantalum (PET) as source gas Can be used. In addition, the conditions (gas type, chamber pressure, plasma power, film formation temperature, film formation time, etc.) for forming the MIM structure capacitor shown in each example are merely examples, and the use, purpose, etc. Any change is possible depending on the situation. In addition, since the drain region and the source region of the MOS transistor constituting the memory cell selection transistor operate in the same manner in principle, they can be operated interchangeably. Further, the P-type semiconductor layer and the N-type semiconductor layer of the MOS transistor may be interchanged.

It is process drawing which shows the manufacturing method of the semiconductor device which is Example 1 of this invention in order of a process. It is process drawing which shows the manufacturing method of the same semiconductor device in process order. It is process drawing which shows the manufacturing method of the same semiconductor device in process order. It is process drawing which shows the manufacturing method of the same semiconductor device in process order. 4 is a flowchart showing a method of forming a lower electrode of a capacitor having an MIM structure in the method for manufacturing a semiconductor device. 4 is a flowchart showing a method of forming a capacitive insulating film of a capacitor having an MIM structure in the method for manufacturing a semiconductor device. 4 is a flowchart showing a method for forming an upper electrode of a capacitor having an MIM structure in the manufacturing method of the semiconductor device. It is a figure which shows the relationship between the applied voltage (horizontal axis) with respect to the capacitor | condenser of the MIM structure formed with the manufacturing method of the same semiconductor device, and a leakage current value (vertical axis). It is a figure which shows the relationship between the leakage current value (horizontal axis) and the accumulation probability (vertical axis) of the capacitor of the MIM structure formed by the manufacturing method of the semiconductor device in comparison with the conventional example. Diagram showing the relationship between the case of forming a capacitor of the MIM structure by the manufacturing method of the semiconductor device, the flow rate of H ₂ gas contained in the plasma processing gas during top electrode formed (horizontal axis) and the leakage current value (vertical axis) It is. When forming an MIM structure capacitor by the semiconductor device manufacturing method, the relationship between the flow rate (horizontal axis) of the H ₂ gas contained in the plasma processing gas when forming the upper electrode and the composition (vertical axis) of the TiN film is shown. FIG. FIG. 6 shows a relationship between a leakage current value (horizontal axis) and a cumulative probability (vertical axis) for a capacitor formed by changing plasma processing conditions when a MIM structure capacitor is formed by the semiconductor device manufacturing method. FIG. 7 is a flowchart showing a method for forming an upper electrode of a capacitor having an MIM structure in a method for manufacturing a semiconductor device according to a third embodiment of the present invention. It is a figure which shows the relationship between the leakage current value (horizontal axis) and the accumulation probability (horizontal axis) of the capacitor | condenser of the MIM structure formed with the manufacturing method of the same semiconductor device compared with a prior art example. It is a figure which shows the relationship between the applied voltage (horizontal axis) with respect to the capacitor | condenser of the MIM structure manufactured with the manufacturing method of the conventional semiconductor device, and a leakage current value (vertical axis).

Explanation of symbols

1 P-type silicon substrate 2 Insulating film for element isolation 3 Gate oxide film 4 Gate electrode (word line)
5 N-type diffusion region 6 First interlayer insulating film 7, 23 Contact hole 8 TiN film 9 W film 10 Memory cell selection transistor 11 Capacitance contact 12 Bit contact 13 Stopper insulating film 14 Second interlayer insulating film 15 Cylinder groove 16 Lower electrode (TiN film)
17 Capacitive insulating film (ZrO ₂ )
18 Upper electrode (TiN film)
19 Capacitor with MIM structure 20 Capacitance wiring 21 Opening 22 Third interlayer insulating film 24 TiN film 25 Bit wiring

Claims (10)

Forming a lower electrode;
Forming a capacitive insulating film on the lower electrode;
Forming an upper electrode made of a titanium nitride film on the capacitor insulating film, and forming a capacitor having an MIM structure,
The titanium nitride film,
Forming a titanium nitride film;
Plasma-treating the titanium nitride film at a plasma power of 550 W or more using a processing gas having a flow rate ratio of hydrogen gas / nitrogen gas ≦ 0.5;
A method for manufacturing a semiconductor device, characterized in that a film is formed by MOCVD, which repeats the above. Forming a lower electrode;
Forming a capacitive insulating film on the lower electrode;
Forming an upper electrode made of a titanium nitride film on the capacitor insulating film, and forming a capacitor having an MIM structure,
The titanium nitride film,
Forming a titanium nitride film;
Plasma-treating the titanium nitride film with a predetermined plasma power using a processing gas having a flow ratio of hydrogen gas / nitrogen gas ≦ 0.5;
The film is formed by the MOCVD method that repeats
The plasma processing step comprises a first plasma processing step followed by a second plasma processing step, wherein the plasma power of the first plasma processing is 100 W or less, and the second plasma processing The method of manufacturing a semiconductor device is characterized in that the plasma power of the second plasma processing step is set to be longer than that of the first plasma processing step. After the step of forming the titanium nitride film,
3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing plasma treatment on the titanium nitride film using nitrogen gas. In the step of forming the upper electrode of the capacitor, a method of manufacturing a semiconductor device according to claim 1, 2 or 3, wherein the setting the number of repetitions in 2-4 times. 5. The method of manufacturing a semiconductor device according to claim 4 , wherein in the step of forming the upper electrode of the capacitor, a film thickness formed per time is 2 to 15 nm. The process of plasma-treating the titanium nitride film at a plasma power of 550 W or more using a process gas having a flow rate ratio of hydrogen gas / nitrogen gas ≦ 0.5 uses only nitrogen gas. Item 6. A method for manufacturing a semiconductor device according to any one of Items 1 to 5 . The plasma processing is performed on the titanium nitride film at a plasma power of 550 W or more and 950 W or less using a processing gas having a flow rate ratio of hydrogen gas / nitrogen gas ≦ 0.5. A method for manufacturing a semiconductor device according to any one of 1 to 6 . As a raw material gas containing titanium, a method of manufacturing a semiconductor device according to any one of claims 1 to 7, characterized by using tetradimethylamino titanium (TDMAT). In the step of forming the capacitive insulating film on the lower electrode, an insulating film having at least one of zirconium oxide, hafnium oxide, aluminum oxide, titanium oxide, and tantalum oxide is formed as the capacitive insulating film. A method for manufacturing a semiconductor device according to claim 1 . The method of manufacturing a semiconductor device according to tungsten hexafluoride to any one of claims 1 to 9, further comprising the step of forming a tungsten film by a CVD method as a material gas on the upper electrode.

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