JP4923583B2 - Clock synchronization system in asynchronous networks - Google Patents

Description

  The present invention relates to a clock synchronization system in an asynchronous network. The present invention relates to a transmission apparatus that enables communication in a synchronous transfer mode (STM) of a high-speed digital leased line service provided by a communication carrier via an IP (Internet Protocol) network (= asynchronous transfer network). Applies to The present invention is also applied as an STM / ETHER converter (hereinafter abbreviated as S / E converter) for converting an interface between STM transmission and ETHERNET (Ethernet: registered trademark of Fuji Xerox Co., Ltd.).

  When transmitting digital data over a network, data and a clock are usually transmitted and received between devices, and data and a clock are usually synchronized. FIG. 10 is a block diagram showing a configuration example of this type of conventional system, and shows an example of a synchronous transfer mode by STM. In the figure, 1a is a clock supply device for supplying a clock, 1b is a subscriber termination device that receives a clock from the clock supply device 1a, and 1c is a high-speed digital leased line network connected to the subscriber termination device 1b. Reference numeral 1d is a line terminating device connected to the high-speed digital leased line network 1c, and 1e is a terminal device connected to the line terminating device 1d. The operation of the system configured as described above will be described as follows.

  The system shown in the figure enables network signal synchronization from the clock supply device 1a to the terminal device 1e using the same clock or a synchronous clock, thereby enabling bidirectional signal transmission. First, the subscriber terminal device 1b is supplied with a clock in the communication station. Then, a carrier clock is generated from the input clock, and the carrier clock is superimposed on the carrier signal (data signal) and transmitted via the high-speed digital leased line network 1c. An optical fiber or a metallic cable may be used instead of the high-speed digital leased line network. In this way, data is transmitted and received between the line terminating device 1d and the subscriber terminating device 1b.

  At this time, the line terminating device 1d extracts data, a clock, and a frame synchronization signal from the received signal, operates in synchronization with the clock, and also superimposes a clock component on the carrier signal for transmission to the terminal device 1e. To do. Similarly, the terminal device 1e performs subsynchronization by extracting data, a clock, and a frame synchronization signal, establishes network synchronization as a whole, and enables synchronous transfer of data.

As a conventional technology of this type, in transmitting a PCM signal, an asynchronous PCM signal is accumulated in a temporary memory, the stored content is read out with a clock of the synchronization signal, and the phase difference between both signals is monitored by a comparison circuit. When the phase difference deviates more than a certain limit, a technique is known in which reading is temporarily stopped according to a predetermined method, phase adjustment is performed, and information indicating the phase change position is transmitted to the receiving side (for example, non-patent document) 1).
"PCM communication system" edited by IEICE. 1980. p76-77

  Here, the high-speed digital leased line network 1c shown in FIG. 10 is an asynchronous network such as an IP (Internet Protocol) network that is not network-synchronized, or packet transfer in which the interface of the subscriber termination device 1b or the line termination device 1d is asynchronous. Etc., there is a problem that the clock component cannot be conveyed. For this reason, an error or a serious communication failure may occur in the carrier signal between the subscriber terminal device 1b and the terminal device 1e.

  The present invention has been made in view of such problems, and an asynchronous network (for example, an IP network) or the like is interposed between terminal devices by STM transmission or between a terminal device and a subscriber terminal device (node device). Another object of the present invention is to provide a clock synchronization system in an asynchronous network that can establish a network synchronization and realize a synchronous transfer mode by transmitting a clock component through the asynchronous network.

(1) The invention according to claim 1 is a data transmission system in which a first transmission device and a second transmission device are connected via an asynchronous network, the first transmission device, the asynchronous network, and the asynchronous network. An interface device for transmitting and receiving data is provided between the first transmission device and the second transmission device, and a buffer pointer of a transmission buffer that temporarily holds data as a clock component on the data transmission side in the interface device The present invention is characterized in that there are provided a digitizing means for digitizing the buffer pointer value , inserting it into a packet and transmitting it, and a clock generating means for extracting and generating a clock from the received packet on the data receiving side. To do.
(2) In the invention according to claim 2, the clock generation means extracts a clock component from the received packet, converts the extracted clock component into an analog signal, receives the analog signal, and a frequency corresponding to the analog signal. characterized in that it is intended to generate.
(3) The invention according to claim 3 is characterized in that the clock generation means extracts a clock component from a received packet and inputs the extracted clock component directly to a digitally controlled oscillator to obtain a frequency. To do.

(1) According to the first aspect of the invention, the clock component is digitized and inserted into the packet and passed through the asynchronous network, and the receiver side extracts the digitized clock component to generate a synchronous clock. Thus, even if the network is an asynchronous network, network synchronization can be established and a synchronous transfer mode can be realized.
(2) According to the second aspect of the present invention , the clock component that is the received digital signal is converted into a voltage value that is an analog signal, and a frequency corresponding to the voltage value is generated using the voltage value, By generating a clock from the frequency, network synchronization can be established between asynchronous networks .
(3) According to the invention described in claim 3, it is possible to process a clock component which is a received digital signal and generate a clock by the DPLL method.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. According to the present invention, frequency control information, which is a buffer pointer value of a transmission buffer (FIFO) synchronized with a synchronous network, is used as a data transmission method by synchronizing clocks between STM transmission apparatuses via an IP network which is an asynchronous network. Information is transmitted between STM-Ethernet converters by packet transmission, and voltage control oscillator (Voltage Controlled Crystal Oscillator, hereinafter abbreviated as VCXO) is controlled by the control information to achieve clock synchronization and network synchronization. Is. Thus, the STM synchronous transfer mode is enabled by generating the STM clock frequency.

  FIG. 1 is a block diagram showing an embodiment of the present invention. The same components as those in FIG. 10 are denoted by the same reference numerals. In the figure, 1a is a clock supply device that supplies a clock, 1b is a subscriber termination device as a first transmission device that receives a clock from the clock supply device 1a, 2c is connected to the subscriber termination device 1b, An S / E converter 2d as an interface device that performs mutual conversion between the Ethernet and the Ethernet is an asynchronous network connected to the S / E converter 2c. As the asynchronous network 2d, an IP network is used here, but other asynchronous networks may be used. The S / E converter 2c includes an STM block connected to the subscriber terminating device 1b and an Ethernet block connected to the IP network 2d, and performs STM / Ethernet conversion. At the same time, the synchronous clock component is digitized and transmitted as a packet to the IP network 2d side.

  An S / E converter 2e is connected to the IP network 2d and serves as an interface device that performs mutual conversion between STM and Ethernet. Reference numeral 1d denotes a line termination device as a second transmission device connected to the S / E converter 2e, and 1e denotes a terminal device connected to the line termination device 1d. The S / E converter 2e is composed of an Ethernet block connected to the IP network 2d and an STM block connected to the line terminating device 1d, and performs STM / Ethernet conversion. At the same time, a packet obtained by digitizing the synchronous clock component transferred from the S / E converter 2c side is received, the numerical value is processed to extract the clock component, and a synchronous clock to the line terminating device 1d side is generated. . The operation of the system configured as described above will be described as follows.

  FIG. 2 is a diagram for explaining the operation of the transmission buffer in the transmission control unit to the subscriber terminal device 1b side in the S / E converter 2c. This transmission buffer is provided in both the subscriber terminating device 1b and the line terminating device 1d. The subscriber terminal device 1b and the line terminal device 1d exchange data with each other. Here, a FIFO (First In First Out) is used as a transmission buffer. Asynchronous data of the Ethernet interface is written to the transmission buffer 3b in a burst manner from the transmission buffer 3a side. That is, the packet data is written in the transmission buffer 3b at the timing of the write clock. On the other hand, the 3c side is periodically read by the interface of the STM synchronous network. That is, reading is performed from the transmission buffer 3b in synchronization with the read clock generated by the clock.

  The buffer pointer value indicating the amount of data accumulated in the buffer 3b changes according to such writing and reading to the buffer 3b. The buffer pointer value indicates the amount of data accumulated in the buffer 3b, but is also an index indicating the address of the buffer to be written or read. When there is a lot of data from 3a, the buffer pointer value increases, and when there are many reads of 3c, the buffer pointer value decreases.

  Therefore, this information is transmitted to the S / E converter 2e by packet transmission which is a communication means via the IP network 2d, and the clock frequency is controlled on the S / E converter 2e side, so that the subscriber It is possible to synchronize with the STM synchronization network on the terminal device 1b side. When a serious line failure such as input disconnection, link disconnection or loss of STM synchronization occurs, the buffer 3b can be reset and the operation can be started from the default (initial value) pointer at the time of recovery.

  FIG. 3 is an explanatory diagram of the clock component (buffer pointer value) transfer method obtained by the transmission control unit of the S / E converter. The same components as those in FIG. 1 are denoted by the same reference numerals. The buffer pointer value 3d (see FIG. 2) is composed of 18-bit data (details will be described later). The 18-bit data is transferred as a pointer packet by embedding 3 bytes into 64 bytes, which is the minimum packet length in packet transfer. At this time, identification data is also given so that it can be identified as a pointer packet.

  The S / E converter 2e receives the pointer packet by the identification data and extracts the buffer pointer value. FIG. 4 is a block diagram showing an example of the internal configuration of the S / E converter 2e. The S / E converter 2c side has the same configuration. The received 8-bit pointer packet data 5a is input to the D / A converter 5b. Here, since identification data that can be identified as a pointer packet is added to the packet data, the packet data can be recognized. The D / A converter 5b converts the input data into an analog signal and inputs the analog signal to the gain amplifier 5c having a gain n.

  In this case, when the transmission interval of the pointer packet data is large, the relative difference between the data is large, and when the transmission interval is small, the relative difference is small, so that the frequency generated by the S / E converter 2e is stabilized. The degree changes. Therefore, the gain of the gain amplifier 5c having the gain n is adjusted so that the transmission interval of the packet data value is optimized.

  The output of the gain amplifier 5c is input to the VCXO 5d. The voltage controlled oscillator 5d generates and outputs a frequency corresponding to the input voltage. The subsequent clock generation unit 5e generates and outputs a timing clock for determining data from the output frequency of the voltage controlled oscillator 5d. As described above, the frequency control is executed using the buffer pointer value 3d and the input data 5a of the D / A converter. Note that a DPLL system that obtains a frequency by directly inputting digital data 5a to a digitally controlled oscillator (DCO) may be used.

  FIG. 5 is a diagram showing the relative relationship of frequency control. An increase in the buffer pointer value 3d indicates that the amount of data from the S / E converter 2e is large and the frequency of the S / E converter 2e is high. In such a state, the input of the D / A converter 5b is reduced. As a result, the voltage of the VCXO 5d decreases and the output frequency decreases. Conversely, when the buffer pointer value 3d is small, the amount of data from the S / E converter 2e is small and the frequency of the S / E converter 2e is low. In such a state, the input of the D / A converter 5b is increased. As a result, the voltage of the VCXO 5d increases and the output frequency thereof increases.

  FIG. 6 is a diagram showing input data to the D / A converter 5b, and shows a method of generating the input data 5a of the D / A converter 5b from the buffer pointer value 3d and a control method related thereto. Since data is written in burst from the 3a side in the transmission buffer 3b in FIG. 2, the data length in the packet transferred from the S / E converter 2e is fixed to 1023 bytes for 10 bits and transferred. As a result, the buffer pointer value 3d is increased by 10 bits of (a) in a burst manner.

  Further, the 14-bit point data of (b) is determined by setting the default pointer and buffer depth at the time of reset to 16 packets. According to the present invention, the pointer data changes from 10 bits to 18 bits, with 14 bits as a default value. That is, if the default value is K and the variation value is ± Δ, the pointer data value is expressed as K ± Δ.

  As described above, every time a packet is written to the 18-bit buffer pointer value 3d, fluctuations in the input data (8-bit data) of the D / A converter 5b can be minimized, and the default pointer value is the center. The 8-bit data of the input data 5a is determined. As shown in FIG. 5, since the relationship between the buffer pointer value 3d and the input data 5a and the input voltage of the VCXO 5d is inversely proportional, the gain of the gain amplifier 5c determines n = 1 / m. The upper 8 bits of the default pointer value are taken as input data for the D / A converter 5b (see FIG. 4).

  As described above in detail, according to the present invention, the clock component is digitized and inserted into the packet and passed through the asynchronous network, and the receiver side extracts the digitized clock component to generate the synchronous clock. Thus, even if the network is an asynchronous network, network synchronization can be established and the synchronous transfer mode can be realized.

  Further, according to the present invention, network synchronization between asynchronous networks can be established by using the pointer value of the transmission buffer as a clock component. Furthermore, the received clock component is converted into an analog signal, a frequency corresponding to the voltage value is generated using the voltage value, and a clock is generated from the frequency to establish network synchronization between the asynchronous networks. Can do.

  According to the present invention, it is possible to vary the characteristics by using parameters as shown in FIG. 7 as other parameters, and it is possible to flexibly cope with the use. FIG. 7 is an explanatory diagram of parameter adjustment. When the frame data size in the 2c direction from the S / E converter 2e in FIG. 3 is used as a parameter, 1023 bytes can be considered as an example of the setting value. If the frame data size is reduced, the frequency stability increases, but there is a problem that traffic from the S / E converter 2e to 2c increases.

  When a correction interval (pointer packet transmission interval) is used as a parameter, 1 second is considered as an example of a set value. If the correction interval is small, the frequency tracking becomes fine, but there is a problem that traffic from the S / E converter 2c to 2e increases. When the VCXO input gain adjustment is used as a parameter, for example, xn is used as a gain setting value. When the gain is large, the followability is improved, but there is a problem that the frequency stability is deteriorated. When the buffer depth is used as a parameter, for example, 16 packets are used as the set value. If the depth is small, the delay becomes small, but there is a problem that it cannot cope with a rapid change.

  Next, specific effects of the present invention will be described. In a communication network in which a STM network and an IP network are duplicated, the capital investment and the maintenance management cost are twice as high as those in the case of a single. However, although the STM network equipment is being replaced by the IP network equipment, it is necessary to continue operation until the last user of the service is removed.

  Therefore, by consolidating STM equipment via the IP network, the equipment can be greatly depreciated, and by unifying the IP network, personnel costs can be reduced and maintenance can be centralized, troubleshooting, etc. Time can be reduced, and total service quality can be improved.

  FIG. 8 shows an example of a conventional network configuration. In the figure, 1c is an STM network (synchronous network), 2d is an IP network (asynchronous network), and 10 is a station. In the station building 10, an STM facility 11 and an IP facility 12 are provided. Reference numeral 20 denotes an STM subscriber connected to the STM facility 11. In the case of such a conventional system, the STM equipment 11 and the IP equipment 12 are overlapped for each station 10, and further, the STM network 1c and the IP network 2d are built to be complicated.

  FIG. 9 is a diagram showing a network configuration example of the present invention. The same components as those in FIG. 8 are denoted by the same reference numerals. In the present invention, the STM subscriber 20 can be accommodated in the IP facility 12 so that the facility can be unified. Also, the equipment cost can be greatly reduced by consolidating the STM equipment 11 that has been vacated into one place. In addition, since the network is also integrated into the IP network (asynchronous network), maintenance and operation costs can be reduced, the system can be simplified, and this can lead to a reduction in time for troubleshooting and the like, thereby improving the total service quality. .

It is a block diagram which shows one embodiment of this invention. It is operation | movement explanatory drawing of a transmission buffer. It is explanatory drawing of the clock component transmission system via IP network. It is a block diagram which shows the example of an internal structure of a S / E converter. It is a figure which shows the relative relationship of frequency control. It is a figure which shows the input data to a D / A converter. It is explanatory drawing of adjustment of a parameter. It is a figure which shows the example of a conventional network structure. It is a figure which shows the network structural example of this invention. It is a block diagram which shows the structural example of a conventional system.

Explanation of symbols

1a Clock supply device 1b Subscriber termination device 1d Line termination device 1e Terminal device 2c S / E converter 2d IP network (asynchronous network)
2e S / E converter

Claims (3)

In a data transmission system in which a first transmission device and a second transmission device are connected via an asynchronous network,
An interface device for transmitting and receiving data between the first transmission device and the asynchronous network, and between the asynchronous network and the second transmission device;
The interface device uses a buffer pointer value of a transmission buffer that temporarily holds data as a clock component on the data transmission side, digitizes the buffer pointer value , inserts it into a packet, and transmits the packet. And a clock synchronization system in an asynchronous network, comprising a clock generation means for extracting and generating a clock from a received packet on a data reception side. The clock generation means extracts a clock component from the received packet, converts the extracted clock component into an analog signal, and receives the analog signal to generate a frequency corresponding to the analog signal. The clock synchronization system in the asynchronous network according to claim 1. 2. The clock synchronization in an asynchronous network according to claim 1 , wherein said clock generation means extracts a clock component from the received packet and inputs the extracted clock component directly to a digitally controlled oscillator to obtain a frequency. system.

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