JP4923596B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state imaging device.

A solid-state imaging device called a so-called CMOS image sensor using a MOS amplification type imaging device is known. This solid-state imaging device generally has an imaging unit in which a large number of pixels have regularity in a two-dimensional matrix, for example, a regular arrangement as columns and rows in the vertical and horizontal directions, a vertical drive unit, , A horizontal transfer unit and an output unit.
As an example of this solid-state imaging device, FIG. 8 shows a schematic configuration of a MOS amplification type solid-state imaging device having an analog / digital converter for each column. The solid-state imaging device 1 includes a plurality of pixels 1 a arranged in a two-dimensional matrix in an imaging region 2, an output circuit 6 connected to a vertical signal line 3, a column unit 4, and a horizontal signal line 5, a vertical drive circuit 7, A horizontal drive circuit 8 and a control circuit 9 are included.

The control circuit 9 receives data for instructing an input clock, an operation mode, and the like from the outside of the MOS image sensor, and supplies clocks and pulses necessary for the operation of the following units in accordance with the data.
The vertical drive circuit 7 selects a row in the pixel portion, and a necessary pulse is supplied to the pixel in that row through a horizontal control wiring (not shown).
In the column unit 4, column signal processing circuits 10 are arranged corresponding to the columns. The column signal processing circuit 10 receives the signals of pixels for one row, and performs processing such as CDS (Correlated Double Sampling), signal amplification, and AD conversion on the signal.
The horizontal drive circuit 8 sequentially selects the column signal processing circuit 10 and guides the signal to the horizontal signal line 5. The output circuit 6 processes and outputs the signal of the horizontal signal line 5. For example, only buffering may be performed, and black level adjustment, column variation correction, signal amplification, and color-related processing may be performed before that.
The pixel 1a includes a photodiode (PD) that is one photoelectric conversion element and a plurality of MOS transistors.

As a circuit configuration that can be used for the pixel 1a, for example, a so-called three-transistor configuration shown in FIG.
In this circuit configuration, the cathode (n region) of the photodiode (PD) is connected to the gate of the amplification transistor Tr3 via the transfer transistor Tr1. A node electrically connected to the gate of the amplification transistor Tr3 is referred to as a floating diffusion (FD). The transfer transistor Tr1 is connected between the photodiode (PD) and the floating diffusion (FD). When the transfer pulse φTRG is applied to the gate via the transfer line 11, the transfer transistor Tr1 is turned on. The converted signal charge is transferred to a floating diffusion (FD).

  The reset transistor Tr2 has a drain connected to the pixel power supply Vdd1, and a source connected to the floating diffusion (FD). The reset transistor Tr2 is turned on when a reset pulse φRST is applied to the gate via the reset line 12, and before the signal charge is transferred from the photodiode (PD) to the floating diffusion (FD), the floating transistor The floating diffusion (FD) is reset by discarding the charge of the diffusion (FD) to the pixel power supply Vdd1.

The amplification transistor Tr3 has a gate connected to the floating diffusion (FD), a drain connected to the pixel power supply Vdd2, and a source connected to the vertical signal line 13. The amplification transistor Tr3 outputs the potential of the floating diffusion (FD) after being reset by the reset transistor Tr2 to the vertical signal line as the reset level, and further, the floating diffusion (after transfer of the signal charge by the transfer transistor Tr1) The potential of FD) is output to the vertical signal line 13 as a signal level.
Note that the drain of the amplifying transistor Tr3 fluctuates due to the influence of the pixel power supply Vdd1 being switched between a high level and a low level as the pixel is driven.

On the other hand, as another circuit configuration that can be used for the pixel 1a, for example, a so-called four-transistor configuration shown in FIG.
In this circuit configuration, four transistors Tr1 to Tr4 are provided in addition to a photoelectric conversion element, for example, a photodiode (PD). Here, the transistors Tr1 to Tr4 are configured as, for example, N-channel MOS transistors.
The photodiode (PD) photoelectrically converts received light into photoelectric charges (here, electrons) having a charge amount corresponding to the amount of light. The cathode (n-type region) of the photodiode (PD) is connected to the gate of the amplification transistor Tr3 through the transfer transistor Tr1. A node electrically connected to the gate of the amplification transistor Tr3 becomes a floating diffusion (FD).
The horizontal wirings, that is, the transfer line 14, the reset line 15, and the selection line 16 are common to the pixels in the same row and are controlled by the vertical drive circuit 7. However, the p-well wiring 17 for fixing the p-well potential of the pixel 1a is fixed to the ground potential.

Further, in this configuration, the transfer transistor Tr1 is connected between the cathode of the photodiode (PD) and the floating diffusion (FD), and is turned on when the transfer pulse φTRG is applied to the gate via the transfer line 14. Thus, the photoelectric charge photoelectrically converted by the photodiode (PD) is transferred to the floating diffusion (FD).
The reset transistor Tr2 is turned on when the drain is connected to the pixel power supply Vdd, the source is connected to the floating diffusion (FD), and the gate is supplied with a reset pulse φRST via the reset line 15, and the photodiode (PD) Prior to the transfer of the signal charge from the floating diffusion (FD) to the floating diffusion (FD), the floating diffusion (FD) is reset by discarding the charge of the floating diffusion (FD) to the pixel power supply Vdd.
In the amplification transistor Tr3, the gate is connected to the floating diffusion (FD), the drain is connected to the pixel power supply Vdd, the potential of the floating diffusion (FD) after being reset by the reset transistor Tr2 is output as a reset level, and further transferred The potential of the floating diffusion (FD) after the signal charge is transferred by the transistor Tr1 is output as a signal level.
In the selection transistor Tr4, for example, the drain is connected to the source of the amplification transistor Tr3, the source is connected to the vertical signal line 18, and the selection pulse φSEL is applied to the gate via the selection line 16, so that the pixel 1a is turned on. As a selected state, the signal output from the amplification transistor Tr3 is relayed to the vertical signal line 18.

By the way, in the CMOS image sensor having these circuit configurations, when very strong light is incident on the photodiode PD that performs photoelectric conversion and accumulation, or when the accumulation time is long, electrons are saturated in the PD and adjacent pixels are detected. There is a possibility that a phenomenon called blooming that leaks to pixels farther away may occur.
Since blooming causes deterioration of the image quality in the solid-state imaging device, a structure for controlling (suppressing) is required. On the other hand, as a proposed structure, a so-called vertical overflow structure in which a path (electron flow path) is provided from the photodiode to the substrate side, or a so-called horizontal overflow in which a path is provided from the transfer transistor in the floating diffusion (FD) direction. Examples include the structure.
Here, in a solid-state imaging device having a CMOS image sensor structure, it is required to reduce the dark current by applying a negative potential to the gate of the transfer transistor at the time of driving. In order to suppress the above-mentioned blooming, it is necessary to use a vertical overflow (see, for example, Patent Document 1).

On the other hand, in a CMOS image sensor having a transfer transistor in each pixel, the overflow barrier / drain impurity region and substrate bias application provided on the substrate in the depth direction as in the CCD type image sensor are applied on the same substrate as the imaging region. Because it was thought that it would affect the operation of the transistors in the drive circuit section and signal processing circuit section provided in the circuit, and because it was not easy to form a potential distribution that forms a vertical overflow structure in the process, the horizontal type Overflow structure was common.
JP 2005-217397

  The present invention has been made in view of such problems, and an object of the present invention is to provide a solid-state imaging device having a potential distribution suitable for a vertical overflow structure while being a CMOS image sensor type in which each pixel includes a transfer transistor. Is to provide.

A solid-state imaging device according to the present invention is formed below an imaging region including a plurality of pixels, a first P-type well region formed in a semiconductor substrate of the imaging region, and the first P-type well region. And the second P-type well region has an ion impurity concentration of 1 × 10 ¹⁶ / cm ³ or less, and the first well region has one or more pixels. The first well region includes a plurality of first conductivity type regions in the substrate depth direction, and the deepest first conductivity type region of the plurality of first conductivity type regions, or The ion impurity concentration of the first conductivity type region located within a distance of 1.5 μm or less from the two well region is 1 × 10 ¹⁶ / cm ³ or more and 2 × 10 ¹⁶ / cm ³ or less, and the ion impurity in the second well region The first conductivity having the deepest concentration in the first well region Region, or is less than half of the ion concentration of the impurity of the first conductivity type region located from the second well region within a distance of 1.5 [mu] m.

Further, the solid-state imaging device is a solid-state imaging equipment having an imaging region including a plurality of pixels, in the semiconductor substrate, forming a second well region of the first conductivity type from the one principal surface of the semiconductor substrate And a first well region of the first conductivity type including a portion having a higher impurity concentration than the second well region is formed in a lattice shape from the main surface side of the semiconductor substrate, leaving intermittent portions. And a step of performing.

According to the solid-state imaging device according to the present invention, the imaging region including a plurality of pixels, the first P-type well region formed in the semiconductor substrate of the imaging region, and the lower side of the first P-type well region And the second P-type well region has an ion impurity concentration of 1 × 10 ¹⁶ / cm ³ or less. It is possible to configure the solid-state imaging device with suppression.

According to the solid-state imaging device described above, the step of forming the first conductivity type second well region in the semiconductor substrate and the first conductivity type first well including a portion having a higher impurity concentration than the second well region. A step of forming the 1-well region in a lattice pattern with the intermittent portions remaining, so that it is possible to simply manufacture a solid-state imaging device in which the blooming rate is suppressed.

In the solid-state imaging device according to the present embodiment, first, a negative potential is applied to the gate of the transfer transistor at the time of charge accumulation in the photodiode, thereby suppressing the occurrence of blooming paths other than going to a deeper position on the substrate. . Furthermore, by selecting the impurity concentration in the first conductivity type second well region (deep well region; deep p-well) formed at a particularly deep position (for example, the deepest part) in the substrate of the imaging region, Among those that can be a flow path (path) of the charge accumulated in the diode, the one that goes to a deeper position on the substrate is the only or main flow path.
In addition, in order to flow more electrons deeper on the substrate through this flow path, the concentration of the first well region (p-well) existing mainly between the element isolation means and the second well region is selected. Then, if necessary, by forming a predetermined impurity concentration distribution in the depth direction in the first well region, the potential tightening is reduced, for example, the blooming rate is reduced to 10% or less as will be described later. It is intended to suppress this.
In the present embodiment, the blooming rate is defined as the ratio at which a signal leaks from a specific pixel to an adjacent pixel.

Embodiments of the present invention will be described with reference to the drawings.
A solid-state imaging device according to the present embodiment described below, that is, a MOS amplification type solid-state imaging device, has the same overall configuration as the solid-state imaging device 1 of FIG. 8 described above. As the pixel, a plurality of transistor types such as the three-transistor type and the four-transistor type shown in FIG. 9 or 10 can be used. That is, in the following description, it is assumed that the solid-state imaging device has three or four transistors in one pixel.
In a CMOS image sensor type solid-state imaging device, not only an imaging region including pixels but also a peripheral circuit can be integrated on the same chip. In the following description, the p-well of the peripheral circuit unit and the pixel unit The p-well is assumed to be electrically separated.

<First Embodiment of Solid-State Imaging Device>
First, a first embodiment of a solid-state imaging device according to the present invention will be described.
1A and 1B show a schematic cross-sectional view of a pixel 21a, which is a main part of the solid-state imaging device 21 according to the present embodiment, and a cross-sectional view on the AA ′ line of the schematic cross-sectional view.
The solid-state imaging device 21 according to the present embodiment is a first conductivity type (p-type) semiconductor substrate having a low impurity concentration or a second conductivity type (n-type) semiconductor substrate having a low impurity concentration in each pixel 21a constituting the imaging unit. For example, a photoelectric conversion element 25 including a high-concentration p-type impurity region 23 and an n-type impurity region 24 is provided on one main surface side (upper surface side in this example) of the silicon substrate 22. The photoelectric conversion element 25 is a buried photodiode, and the dark current is reduced by the high-concentration p-type impurity layer 23 on the surface.
On the other hand, a high-concentration n-type impurity region 27 serving as a drain of the transfer transistor is provided at a position opposed to the transfer transistor having the photoelectric conversion element 25 as a source across the gate 26.

Outside the transfer transistor, the element isolating means is in contact with the photoelectric conversion element 25 and the n-type impurity region 27 and is exposed on the main surface side and deeper than the p-type impurity region 23 and the n-type impurity region 27. 28a and 28b are formed. These element isolation means 28a and 28b may be in any form as long as they have an element isolation function, such as STI (Shallow Trench Isolation) and LOCOS (Local Oxidation of Silicon).
Further, p-type first well regions 29a and 29b are provided below the element isolation means 28a and 28b. A common second well region 30 is formed in contact with the first well regions 29a and 29b on the side opposite to the main surface described above, in the present example, on the lower side, and the first well regions 29a and 29b The 2-well region 30 is separated from the photoelectric conversion element 25 by a low-concentration n-type impurity region 31.

The second well region 30 has an ion impurity concentration suppressed at least as compared with the first well regions 29a and 29b, and is, for example, 1 × 10 ¹⁶ / cm ³ or less.
Although not shown, it is preferable that the first well regions 29a and 29b include a plurality of first conductivity type regions distributed in the substrate depth direction.
Further, a positive fixed charge is applied to the semiconductor substrate 22, and a ground (GND) potential is applied to the second well region 30.

In the solid-state imaging device 21 according to the present embodiment, it is assumed that corresponding well contacts are provided, one per pixel or one per several pixels. This well contact stabilizes the potentials of the first well regions 29a and 29b, and suppresses so-called shading that causes bias in the output between the central portion and the peripheral portion of each pixel at the time of saturation or darkness due to well fluctuation. be able to.
If the pixel array portion is small or shading is not a problem, it is not always necessary to provide a well contact. On the other hand, if there is a margin in area, resistance, etc., a plurality of contacts are provided per pixel and a well potential is provided. Even when the well resistance increases, the shading can be suppressed.
By providing well contacts in this way, an increase in well resistance k (well resistance) that can occur when the impurity concentration of the first well regions 29a and 29b and the second well region 30 is simply reduced is avoided. It is possible to avoid shading (output distribution and non-uniformity in the pixel area) due to a difference in time constant in the pixel array area.

FIG. 2 shows the potential structure of the AA ′ cross section of FIG. 1A. In the photodiode, where n-type impurities such as As (arsenic) and P (phosphorus) are implanted, the potential deepens and electrons accumulate.
In the charge accumulation period, when a large number of electrons are accumulated in the photodiode, the potential becomes shallower, and flows to the substrate side beyond the overflow barrier (OFB), that is, the second well region 30 immediately below the photodiode. A vertical overflow structure is formed. When the OFB is lowered, the electrons easily flow to a deeper position (depth direction) of the substrate, thereby suppressing blooming.
Note that OFB decreases as the impurity concentration in the second well region decreases, that is, as the potential is brought in the positive direction. In the present embodiment, an appropriate OFB level can be obtained by controlling the impurity concentration of the second well region 30. On the other hand, in the charge accumulation period, a positive voltage is applied to the gate electrode of the transfer transistor, whereby the channel portion is turned into p and the dark current is suppressed.

Thus, in the solid-state imaging device 21 according to the present embodiment, the ion impurity concentration in the second well region 30 is suppressed, for example, 1 × 10 ¹⁶ / cm ³ or less. An electron overflow path (flow path) is formed so as to go deeper in the substrate, and blooming can be suppressed.

<Second Embodiment of Solid-State Imaging Device>
First, a second embodiment of the solid-state imaging device according to the present invention will be described.
FIG. 3 is a schematic cross-sectional view of a pixel 41a that is a main part of the solid-state imaging device 41 according to the present embodiment.
The solid-state imaging device 41 according to the present embodiment is a first conductivity type (p-type) semiconductor substrate having a low impurity concentration or a second conductivity type (n-type) semiconductor substrate having a low impurity concentration in each pixel 41a constituting the imaging unit. For example, a photoelectric conversion element 45 including a high-concentration p-type impurity region 43 and an n-type impurity region 44 is provided on one main surface side (upper surface side in this example) of the silicon substrate 42. The photoelectric conversion element 45 is a buried photodiode, and the dark current is reduced by the high-concentration p-type impurity layer 43 on the surface.
On the other hand, a high-concentration n-type impurity region 47 serving as a drain of the transfer transistor is provided at a position opposed to the transfer transistor having the photoelectric conversion element 45 as a source across the gate 46.

Outside the transfer transistor, the element isolation means is in contact with the photoelectric conversion element 45 and the n-type impurity region 47 and is exposed to the main surface side and deeper than the p-type impurity region 43 and the n-type impurity region 47. 48a and 48b are formed. These element isolation means 48a and 48b may be in any form as long as they have an element isolation function, such as STI and LOCOS.
Further, p-type first well regions 49a and 49b are provided below the respective element isolation means 48a and 48b. A common second well region 50 is formed in contact with the first well regions 49a and 49b on the side opposite to the main surface described above, in this example, on the lower side, and the first well regions 49a and 49b The two-well region 50 is separated from the photoelectric conversion element 45 by a low concentration n-type impurity region 51.

In the present embodiment, as shown in FIG. 4, the second well region 50 is provided in a lattice shape corresponding to the formation portions of the first well regions 49a and 49b, and includes a central portion of the pixel. In the part, an intermittent part without the second well region 50 is provided.
In the case of this configuration, the first well regions 49a and 49b directly from at least one of the deepest (close to the second well region) first conductivity type region and the second well region 50 by impurity diffusion or the like. In this case, the potential is tightened toward the center of the pixel in which the second well region 50 is not formed, and an overflow barrier is indirectly formed in the depth direction from the photoelectric conversion element 45 to a deeper position of the substrate. .
Therefore, according to this configuration, blooming can be suppressed similarly to the configuration in the first embodiment described above, and the manufacturing cost can be reduced. In manufacturing, the mask used to form the first well regions 49a and 49b can also be used to form the second well region 50. Further, the photoresist in the ion implantation is also used for the first well regions 49a and 49b and the second well. Since it can be used at the time of each formation with a region, the steps relating to the formation and removal of the resist can be reduced.

The second well region 50 has an ion impurity concentration suppressed at least as compared with the first well regions 49a and 49b, and is, for example, 1 × 10 ¹⁶ / cm ³ or less.
Although not shown, it is preferable that the first well regions 49a and 49b include a plurality of first conductivity type regions distributed in the substrate depth direction.
Further, a positive fixed charge is applied to the semiconductor substrate 42, and a ground (GND) potential is applied to the second well region 50.

Also in the solid-state imaging device 41 according to the present embodiment, it is assumed that corresponding well contacts are provided for each pixel or for several pixels in common. This well contact stabilizes the potentials of the first well regions 49a and 49b, and suppresses so-called shading in which the output is biased between the central portion and the peripheral portion of each pixel during saturation or darkness due to well fluctuation. Can do.
If the pixel array portion is small or shading is not a problem, it is not always necessary to provide a well contact. On the other hand, if there is a margin in terms of area, resistance, etc., a plurality of contacts are provided per pixel and the well potential is reduced. Even when the stabilization capability is increased and the well resistance is increased, shading can be suppressed.

Also in the present embodiment, during the charge accumulation period, when a large number of electrons are accumulated in the photodiode, the potential becomes shallower and exceeds the overflow barrier (OFB), that is, the second well region 50 immediately below the photodiode, on the substrate side. As a result, the vertical overflow structure is formed. When the OFB is lowered, the electrons easily flow to a deeper position (depth direction) of the substrate, thereby suppressing blooming.
Note that OFB decreases as the impurity concentration in the second well region decreases. In the present embodiment, an appropriate OFB level can be obtained by controlling the impurity concentration of the second well region 50. On the other hand, in the charge accumulation period, a positive voltage is applied to the gate electrode of the transfer transistor, whereby the channel portion is turned into p and the dark current is suppressed.

As described above, also in the solid-state imaging device according to the present embodiment, the ion impurity concentration in the second well region 50 is suppressed, for example, 1 × 10 ¹⁶ / cm ³ or less, so that the photoelectric conversion element 45 and the substrate An electron overflow path (flow path) is formed so as to go to a deeper position, and blooming can be suppressed.

< Method for Manufacturing Solid-State Imaging Device >
Next, a method for manufacturing the solid-state imaging device will be described.
Na us, for the first exemplary method for manufacturing a solid-state imaging device 21 described in the embodiment of the solid-state imaging device, describes the formation of the main part.

In the method for manufacturing a solid-state image sensor, First, a n-type semiconductor substrate 22, an element isolation means 28a and 28b in a position to be the isolation between the pixel and the pixels for the substrate 22.
Subsequently, a p-type second well region 30 is formed by ion implantation at a predetermined depth position from the upper surface of the substrate, and a p-type finally obtained first well region is formed at a position corresponding to the inside of the pixel. First well regions 29a and 29b are formed using a lattice-shaped mask corresponding to the planar shape.
In the case where the second well region is formed in the shape having the intermittent portion as described in the second embodiment of the solid-state imaging device described above, a mask used for the first well region is set in advance and common. The first well region and the second well region can be simply formed using this mask.

Here, in the case where the first well region is constituted by a plurality of impurity regions, in order to lower the impurity concentration particularly in the impurity region closer to the second well region, the dose is gradually reduced while the impurity implantation energy is gradually reduced. It is preferable to increase the amount and make it gradually shallow.
In addition, the first well region and the second well region can be formed independently of the wells constituting the peripheral circuit by selective impurity implantation into the imaging region.

Subsequently, the n-type region 24 and the high-concentration p-type region 23 constituting the photoelectric conversion element are formed by ion implantation in the vicinity of the upper surface apart from the second well region 30 and the first well regions 29a and 29b, Further, a high-concentration n-type region 27 serving as the drain of the transfer transistor having the n-type region 24 as a source is formed by ion implantation so as to be in contact with the first well region 29b.
Subsequently, a gate electrode 26 is formed on the corresponding channel region between the n-type region 24 and the n-type region 27 via the gate insulating film.
In this way, the solid-state imaging device 21 is obtained.

<Example>
Examples of the solid-state imaging device according to the present invention will be described.
First, as a first example, in the solid-state imaging device according to the first embodiment described above, deep p− obtained by (impurity concentration of second well region 30 / impurity concentration of first well regions 29a and 29b). The well concentration ratio and the blooming rate were examined. The results are shown in FIG. 5 (solid line a).
From this result, it is preferable that the impurity concentration of the second well region 30 is not more than half of the impurity concentration of the first well regions 29a and 29b. Specifically, the ionic impurity having the impurity concentration of the first well regions 29a and 29b is preferred. It was confirmed that the concentration is preferably 1 × 10 ¹⁶ / cm ³ or more and 2 × 10 ¹⁶ / cm ³ or less.

Note that the blooming rate can be controlled to an arbitrary value by controlling the impurity concentration. That is, by reducing OFB, the amount of charge accumulated in the PD is naturally reduced and the saturation signal amount is reduced, but the saturation signal amount and the blooming rate can be controlled to arbitrary values. When the blooming rate is controlled by deep p-well, of course, the suppression effect is greater when the blooming rate is zero, and the results in FIG. 5 also show that there is the least blooming when there is no deep p-well (density ratio 0). .
However, since the variation of the saturation signal amount becomes large and there is a concern that the controllability is lowered, it is considered that the impurity concentration is preferably not 0 in consideration of mass production.

Next, as a second example, in the solid-state imaging device according to the first embodiment described above, the first well region includes a plurality of first conductivity type regions distributed in the substrate depth direction. The relationship between the deep p-well concentration ratio and the blooming rate was performed.
FIG. 6 shows a configuration in which a second well region having a lower impurity concentration than that of the first well region is provided (common to the first embodiment; solid line a ′), and in addition to this, in the first well region. 3 shows a result relating to a configuration (broken line b) in which the concentration of the first conductivity type impurity region deepest (that is, closest to the second well region) is lowered in two steps.
In the present embodiment, the blooming rate is reduced because the deepest part of the impurity concentration in the first well region, which is at a position that indirectly contributes to the formation of the OFB potential, is half that in the first embodiment. Was greatly reduced, and the suppression of blooming was confirmed.
It has also been confirmed that it is effective to reduce the concentration of the impurity region located within a distance of 1.5 μm or less from the second well region among the plurality of impurity regions constituting the first well region. . Here, the position of the impurity region means the position of the concentration center.

Next, as a third example, the solid-state imaging device according to the first embodiment described above and the solid-state imaging device according to the second embodiment were compared.
FIG. 7 shows a configuration in which a second well region having a lower impurity concentration than the first well region is provided (common to the first embodiment; solid line a ″), and the second well region is intermittently formed. The result regarding the structure (broken line c) provided in the grid | lattice form which has an opening including the center of a pixel is shown.
From this result, it was confirmed that blooming was particularly reduced when the lattice shape was used.

As described in the above embodiments and examples, according to the solid-state imaging device according to the present embodiment, the first conductive surface is formed on one main surface side of the semiconductor substrate on which many pixels including photoelectric conversion elements are formed. A first well region of the type is formed, a second well region of the first conductivity type is formed on the opposite side of the main surface of the first well region, and the ionic impurity concentration of the second well region is 1 Since it is set to x 10 ¹⁶ / cm ³ or less, as will be described later, it is possible to configure a solid-state imaging device while suppressing the blooming rate.

  Note that the numerical conditions such as the materials used, the amount thereof, the processing time, and the dimensions mentioned in the description of the above embodiments are only suitable examples, and the dimensions, shapes, and arrangement relationships in the drawings used for the description are also schematic. Is. That is, the present invention is not limited to this embodiment.

For example, in the foregoing description, the first conductivity type is p-type, will be described an example of a solid-state imaging equipment according to the present invention the second conductivity type is n-type, it is also possible to reverse the two conductivity types.
For example, in the above-described embodiment, the case where electrons are stored has been described as an example. However, in the case of holes, all the polarities are reversed, and the same structure can be used.

Further, for example, the semiconductor substrate is not limited to the n-type, and may be a p-type with an extremely low concentration.
Further, for example, the solid-state imaging device according to the present invention can have any of the circuit configurations of the so-called 4-transistor and 3-transistor described above. Various modifications and changes can be made to the present invention, such as a circuit configuration connected between the two.

1A and 1B are a schematic cross-sectional view showing a configuration of a main part in an example of a solid-state imaging device according to the present invention, and a schematic cross-sectional view relating to a cross section different from this by 90 °. It is a schematic diagram which shows distribution of the potential of the principal part in an example of the solid-state imaging device which concerns on this invention. It is a schematic sectional drawing which shows the structure of the principal part in the other example of the solid-state imaging device concerning this invention. It is a schematic diagram which shows the planar shape of an example of a 2nd well area | region in the other example of the solid-state imaging device which concerns on this invention. It is a schematic diagram showing the relationship between the impurity concentration ratio and the blooming rate for explaining an example of the solid-state imaging device according to the present invention. It is a schematic diagram showing the relationship between the impurity concentration ratio and the blooming rate for explaining an example of the solid-state imaging device according to the present invention. It is a schematic diagram showing the relationship between the impurity concentration ratio and the blooming rate for explaining an example of the solid-state imaging device according to the present invention. It is a schematic block diagram with which it uses for description of a solid-state imaging device. It is a circuit diagram with which it uses for description of a solid-state imaging device. It is a circuit diagram with which it uses for description of a solid-state imaging device.

Explanation of symbols

  1, 21, 41 ... solid-state imaging device, 1 a, 21 a, 41 a... Pixel, 2... Imaging region, 3. Line 6 6 Output circuit 7 Vertical drive circuit 8 Horizontal drive circuit 9 Control circuit 10 Column signal processing circuit 11 Transfer line 12 .. Reset line, 13... Vertical signal line, 14... Transfer line, 15... Reset line, 16... Selection line, 17. , 42 ... Semiconductor substrate, 23, 43 ... p-type impurity region, 24, 44 ... n-type impurity region, 25, 45 ... Photoelectric conversion element, 26, 46 ... Gate, 27, 47, n-type impurity regions, 28a, 28b, 48a, 48b, element isolation means, 29a, 29b, 49a 49b ··· first well region, 30, 50 ... the second well region

Claims (3)

An imaging region including a plurality of pixels;
A first well region of a first conductivity type formed in the semiconductor substrate of the imaging region;
A second well region of a first conductivity type formed below the first well region,
The second well region has an ion impurity concentration of 1 × 10 ¹⁶ / cm ³ or less,
The first well region is connected to a well contact for each of the pixels or for each of the plurality of pixels;
The first well region includes a plurality of first conductivity type regions in the substrate depth direction, and the ion impurity concentration of the deepest first conductivity type region of the plurality of first conductivity type regions is 1 × 10 ¹⁶ / cm. ³ or more and 2 × 10 ¹⁶ / cm ³ or less,
A solid-state imaging device , wherein an ion impurity concentration of the second well region is ½ or less of an ion impurity concentration of the deepest first conductivity type region of the first well region . An imaging region including a plurality of pixels;
A first well region of a first conductivity type formed in the semiconductor substrate of the imaging region;
A second well region of a first conductivity type formed below the first well region,
The second well region has an ion impurity concentration of 1 × 10 ¹⁶ / cm ³ or less,
The first well region is connected to a well contact for each of the pixels or for each of the plurality of pixels;
The first well region includes a plurality of first conductivity type regions in the substrate depth direction, and is located at a distance of 1.5 μm or less from the second well region included in the plurality of first conductivity type regions. The ion impurity concentration in the conductivity type region is 1 × 10 ¹⁶ / cm ³ or more and 2 × 10 ¹⁶ / cm ³ or less,
Solid-state imaging in which the ion impurity concentration of the second well region is ½ or less of the ion impurity concentration of the first conductivity type region located within a distance of 1.5 μm from the second well region of the first well region apparatus.   3. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is formed to include an ion impurity of a first conductivity type or a second conductivity type, the first conductivity type is a p-type, and the second conductivity type is an n-type. The solid-state imaging device described.

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