JP4936337B2 - Status response detection system and method - Google Patents

Description

  The present invention relates generally to a system for detecting states at multiple locations, and more particularly to a system for adjusting multiple detector elements with a common electronic circuit.

  Many applications require detection of conditions such as pressure, acceleration, torque, and force at multiple locations. As an example in an automotive environment, an electrohydraulic brake system or EHB system generally requires detection of oil pressure at six locations. Pressure detection is required at each wheel for closed-loop braking force control, at a location for detecting driver input, and at the accumulator to detect system pre-pressure. Since all the hydraulic detection points are on a path through a hydraulic control unit or HCU having a system controller, i.e. a microprocessor, there can be one member that detects all the different hydraulic system pressures. Proper operation is obtained with six discrete pressure sensors with fully regulated electronics, but the total cost of the pressure sensor is higher than desired, compared to the cost of the remaining system components.

  Accordingly, it is an object of the present invention to provide a state response detection system that is more reliable and less costly than the prior art systems described above. Yet another object is a relatively low cost, accurate and reliable detection system that responds to pressure, acceleration, torque, force, etc., and an improved low cost tuning condition response detection element Is to provide a simple method.

  Briefly, in a state response detection system manufactured according to the present invention, a plurality of detection elements are connected to an ASIC, and the output of any selected detection element is connected to a common signal conditioning circuit by analog multiplexing. . The signal of the detection element is adjusted by a signal adjustment circuit of an ASIC that includes basic calibration data and performs partial adjustment. The complete feature data for all detector elements is stored in the ASIC's non-volatile memory, which may provide additional compensation necessary for the host controller to perform the appropriate mathematical operations and complete the signal conditioning. Is transferred to a host controller, for example, a microprocessor. According to a feature of the present invention, a diagnostic circuit path for diagnosing detection element and detection element connection failures is included in the ASIC. According to another feature, first and second fixed test sensing elements are formed in the ASIC for diagnosing ASIC failures.

  In accordance with an embodiment of the present invention, the sensing element is an individual known in the art, such as a silicon resistance bridge that is fired at high temperature and bonded to the diaphragm via a glass material suitable for placement in the fluid pressure port. Formed from a strain bridge. When pressurized, fluid is present in the pressure port and the diaphragm and bridge are subjected to elastic strain. Since the resistors in the bridge are made from silicon, they exhibit a piezoresistive effect that causes a change in resistance when subjected to strain. Applying a voltage to the bridge causes a small voltage change in the bridge output. In the described embodiment, a circuit for six detector elements is shown, but it should be understood that the circuit can be modified to accommodate more or fewer detector elements as desired.

  According to the described embodiment, the bridge bias is supplied via an electronically programmable resistance in series with the strain bridge. The resistance can be set to a specific value to obtain a temperature signal from the bridge, or set to zero to bias the bridge with the full supply voltage. Selection of the bias resistance value is performed by selecting a register value. The generation of the temperature signal takes place by using a temperature coefficient (TCR) of the resistance of the bridge and forming a voltage divider with a low / zero TCR programmable resistance. The generation of the temperature signal by this means has been conventionally performed.

  In accordance with the present invention, since the bridge adjustment circuit functions using one bridge at a time, means are provided for switching the bridge bias and the respective bridge output to the input of the adjustment circuit. This is done by an analog multiplexer. The input to the adjustment circuit is controlled by three register values. All bridges are always connected to the ASIC terminals. In addition to the six pressure sensor inputs, two reference bridges are also included in the circuit and are selected by an analog multiplexer register for the purpose of diagnostic testing of the circuit. The function of the reference bridge is further described below.

  Correction of the electronically programmable offset and gain of the signal proportional to the pressure is performed by control of the respective registers. This minimum amount of calibration is necessary to maximize the output range of the pressure signal output signal in order to use the maximum possible input range of the analog-to-digital converter (ADC). By using this approach, the bit resolution of the ADC block can be reduced to a minimum acceptable level, thereby reducing the size and cost of circuit elements. An optional input low-pass filter is provided to attenuate high-frequency noise sources (eg, EMI), and an electronically programmable gain stage output provides an optional low-pass filter that allows the system to respond to customer frequency response. Provided to adapt to.

  The diagnostic function is realized by two parts of the circuit. The first part is the detector element diagnostic circuit, which provides an offset corrected amplified signal that is proportional to the addition of the selected bridge output signal. Ideally, the output of the sensing element diagnostic circuit is independent of pressure and temperature, so changes in this parameter are used to indicate a sensing element failure (eg, bridge parameter drift or hard failure). sell. A system comparison of the compensated output with the value stored at the time of manufacture is performed to determine if the performance of the sensing element is degraded. Manufacturing tolerances cause pressure and temperature dependence, which reduces the accuracy of the sensing element diagnostic signal and reduces the ability to detect errors at the system level. The system's use of pressure and temperature signals from selected bridges provides a means to correct pressure and temperature related sensing element diagnostic signal errors, allowing more accurate analysis and more precise error detection capabilities. .

  The second part of the circuit that provides the diagnostic function is the first and second reference bridges. The function of these reference bridges is to input a fixed bridge signal that is proportional to the zero and full scale bridge outputs, respectively. The pressure signal, temperature signal, and detection element diagnostic signal are calibrated at the time of manufacture and stored in the non-volatile memory of the ASIC. When test mode is activated, the system analyzes the pressure, temperature, and detector diagnostic output signals and compares these outputs to the values stored at the time of manufacture to determine if the circuit performance is degraded or malfunctioning. It can be decided. The use of zero and full scale reference bridges fully operates the full operating range of all circuit paths and provides extensive diagnostic capabilities.

  The digital port function is provided to send data to and receive data from the host controller or system controller. The system controller inputs commands to the adjustment electronics, where the adjustment electronics perform the functions requested by the controller. For example, the controller requests pressure information from the detection element 2. The digital port receives the command, and the logic controller block confirms (eg, partially checks) and decodes the command. The logic controller block then sets the correct multiplexer switch position, loads the corresponding register value, waits for the analog signal path to stabilize, triggers the analog-to-digital conversion, and outputs the analog-to-digital converter output. Instructs the digital port to load and send the requested information to the digital port. Combined instructions are executed and more than one piece of information is supplied at a time (eg, pressure, temperature, and sensing element diagnostics are captured and transferred in a single transmission), or the system The sequence can be instructed to be transmitted continuously (eg, P1, SDC1, P2, SDC2, P3, SDC3, P4, SDC4, P5, SDC5, P6, SDC6, T1, repeat ...). The format of the digital data transmission can be customized to meet customer requirements.

  In order to minimize system complexity and cost, a minimum amount of electronic calibration of the pressure, temperature and diagnostic signals is performed. The remaining signal correction is performed by the existing system controller (eg, a microprocessor) using additional coefficients stored in the ASIC. In calibration, the circuit is electronically calibrated by controlling binary register values, and all digital settings are stored in non-volatile memory (eg, EEPROM) in the ASIC. In that case, the sensing element and circuit outputs (pressure, temperature, and sensing element diagnostics) have features as a collection of pressure and temperature to determine operation in the full operating parameter range. From this test data, errors in the remaining temperature signal, pressure signal, and diagnostic signal are determined and stored in the non-volatile memory of the ASIC. Since the conditioning electronics has the ability to communicate the compensation factor to the system controller, it can take advantage of its existing ability to perform highly accurate mathematical corrections of pressure signals, temperature signals, and diagnostic signals. Objects, advantages, and novel features of the present invention will become more fully apparent when the following description is read with reference to the accompanying drawings.

  With particular reference to FIG. 2, the number 1 indicates a state response detection element in the form of a bridge as described above. Although it is described as responsive to pressure, it can also be used to detect other conditions such as acceleration, torque, and force suitable for such bridge structures.

An ASIC (Application Specific Integrated Circuit) MSC is formed with first, second, and third 8-to-1 analog multiplexers 10a, 10b, 10c, respectively, at its front end. Multiplexer 10a has eight address locations IP0 to IP7, multiplexer 10b has eight address locations IM0 to IM7, and multiplexer 10c has address locations GD0 to GD7. Each detection element bridge has a bridge node BRG, a ground node GND, a positive output node INP, and a negative output node INM. The positive output node of the detection element 1 is connected to IP1 of the multiplexer 10a, the negative output node is connected to IM1 of the multiplexer 10b, and the ground node GND is connected to GD1 of the multiplexer 10c. The other detection elements are similarly connected to the ASIC 10 as shown in FIG. The bridge voltage node of each detection element is connected to a voltage source V _pwr via a node BRG and an electronically programmable low temperature coefficient bias resistor 10d1. The electronically programmable bias resistor 10d1 is digitally used to adjust a resistor R REG, ie, a bias resistor connected to a selected sensing element bridge having a relatively high temperature coefficient to obtain a temperature signal. Controlled by the variable to be controlled. In some applications, the bridge may be biased by a zero value resistor, but in this application, it should be understood that a signal proportional to the temperature signal is used for circuit compensation for temperature error. The specific resistance level to properly bias each bridge is selected during calibration along with the offset and gain described below. Bridge voltage V _brg is also supplied to the analog-digital converter 10g which will be described later via an amplifier 10d2.

  Multiplexers 10a, 10b, and 10c are controlled by respective registers MIPREG, MIM REG, and MGD REG. The sensing elements are controlled by setting each multiplexer to the same address location and coupling the ground node of the selected sensing element bridge to signal ground to complete the sensing element bridge bias. The plus output and minus output are multiplexed to the common signal adjustment circuit path 10f. Commands are issued from the logic controller section 10e that synchronizes control of various ASIC components. The command makes a call from the non-volatile memory section 10h and routes the register value corresponding to the selected sensing element bridge to all locations.

The signal conditioning circuit path 10f is used to adjust the detected parameter, in this particular embodiment the pressure. The positive and negative outputs of the sensing element bridge are first supplied to a differential gain amplifier 10f1, the output of which is proportional to the voltage V _brg added to the signal to correct the initial sensing element offset error. Connected to an offset correction stage including an adder network 10f2 controlled by a register B REG for supplying offset correction. The offset corrected signal proportional to pressure is then fed to a gain stage including a variable gain amplifier 10f3 controlled by resistor G REG, and the resulting adjusted signal is then analog to digital converter 10g. Connected to. The low pass filter LPF is optionally shown to attenuate input noise at the input of the differential amplifier 10f1, as shown, and to customize the pressure at the output of the variable gain amplifier 10f3 according to system requirements. Provided.

  The analog-to-digital converter 10g then converts all information associated with the selected sensing element into a digital word and sends that information via the digital port 10k to the system controller 12 shown in FIG. This information is offset and gain corrected, but not temperature corrected to simplify the ASIC and reduce cost. As will be described later, the data necessary to perform the temperature compensation is stored in the non-volatile memory section 10h, which means that when the system controller 12 is able to perform mathematical correction of the signal upon command, the controller 12 To be downloaded.

The logic controller 10e selects a sensing element that captures the pressure response signal, and the positive and negative outputs of this sensing element are also multiplexed into the sensing element diagnostic circuit path 10m and added and summed at the summing node 10m1 signal is connected to the offset correction stage including a summing network 10m2 which is controlled by and register CB REG proportional to the bridge drive V _brg. The offset corrected signal is then supplied to the variable gain stage 10m3 controlled by the register CG REG. The low pass filter LPF is preferably used to tune the circuit response and the signal is input to the analog to digital converter 10g. This gives an average of the positive and negative outputs of the sensing element and provides information independent of temperature and pressure input parameters, and the system controller 12 analyzes this information and crosses the boundary where the diagnostic signal is. It makes it possible to determine whether there is a fluctuating sensing element or sensing element connection failure.

  The second diagnostic tool is provided by fixed test bridges RB1 and RB2 formed in the ASIC itself, each of which has one state, eg, zero pressure, and a second state, eg, full scale pressure. It has been simulated. At the time of manufacture, the register value of the register R REG is selected for the bridges RB1 and RB2, so when the address 0 for the test bridge RB1 is selected or when the address 7 for the test bridge RB2 is selected, respectively. Are multiplexed via signal conditioning circuit path 10f, temperature circuit path, and path element diagnostic circuit path with appropriate register values. The feature data, also stored at the time of manufacture, allows the system controller 12 to analyze this information and determine if there is a failure in the ASIC. The test bridge provides a fixed input that does not vary with time, temperature, or other parameters, and whether the temperature, pressure, and detector diagnostic circuits are functioning properly at the extremes of the state range, for example, the pressure range Decide if.

  During the manufacture of the ASIC and the detector element, an automatic calibrating device is conventionally used by the issuing ASIC via the (by issuing ASIC) digital port 10k, and various registers in the circuit are automatically set and individually set. These calibration coefficients are stored in the non-volatile memory section 10h of the ASIC. In this way, each sensing element stores a set of register values that enable custom offset, gain, bridge drive, and common mode signals, so that such changes in information can be It is applied to the selected detection element. Once all the information is stored in non-volatile memory, the sensing element and ASIC are given pressure and temperature characteristics, i.e. the ASIC and sensing element are placed in a heating chamber and pressure is applied to the different sensing elements. The output signals at the respective temperature and pressure test points are input. Because of the non-linear temperature error, three temperature states are taken up in the sensing element, but since the pressure response is linear, two pressure points are sufficient. This characteristic data of the temperature and pressure matrix is stored in the non-volatile memory section 10h. This information enables the system controller to respond to the specific performance of each detector element, for example, to perform appropriate mathematical compensation by means of a lookup table or correction of polynomial coefficients to achieve high precision compensation. . In this way, the register is initially set with two pressures and one temperature to calibrate the sensing element, which in turn allows characterization at additional temperature and pressure points. The term characterization here refers to obtaining the output at these additional temperature and pressure points, and then changing this data in a table format or indirectly as a polynomial coefficient without changing or adjusting the original calibration data. , To remember. This gives a complete matrix of data necessary to mathematically adequately correct the output signal in the system controller.

  The digital port 10k is used to transfer digital information to or from the system controller 12. The digital port receives a command from the system controller 12, which is properly checked by the logic controller 10e, such as by a conventional parity check, and decoded by the logic controller section to provide the necessary functions, eg, Select the address of the multiplexer, recall the appropriate register settings from the non-volatile memory section 10h, start analog-to-digital conversion, and then send the data from the digital port 10k to the system controller 12. The command is issued individually to obtain and transmit a single piece of information, such as a pressure condition at a designated sensing element, a diagnostic signal, or other selected information, or it is selected A command is continuously issued by the sequence, and data is obtained as desired from each of the detection element and the diagnosis.

  The circuit on the ASIC is preferably formed so that data can be obtained within a sufficiently short period of time so that when a piece of information is requested according to the prior art, the signal is already well conditioned, i.e. Whether the system controller is compensated for temperature and pressure, is multiplexed by the system controller, or is partially adjusted by compensation performed in the system controller according to the present invention, for example, a fraction of milliseconds Within the same.

  According to the present invention, the analog adjustment is performed in the sensor system, i.e., the ASIC that supplies the digitized signal, and then the signal compensation is performed in the host controller, and the information is obtained from the ASIC non-volatile memory. Supplied to the volatile memory of the host controller. In accordance with the present invention, multiple sensors are multiplexed into a common electrically calibratable temperature signal, pressure signal, and diagnostic signal compensation adjustment path, which provides partial compensation for sensing element errors. The compensation is sent to the host controller along with the data coefficients to digitally compensate each sensing element. The test bridge and detector element diagnostic circuit paths have the ability to continue to ensure reliable operation.

  The initialization sequence for the transfer of feature data from the ASIC MSC to the system controller is shown in FIGS. 3a and 3b. The application of power in step 100 and the feature data stored in the factory in step 102 It includes transmission of a command for transferring a specific one, transmission confirmation in step 104, and determination step 106 for ascertaining whether an error has been detected. A negative decision is a decision step that decodes the command and controls other circuit blocks to lead to step 108 where the command is executed, then to step 110 for parity check to see if an error has been detected. Proceed to 112. The negative response here leads to step 114 where the requested information is loaded into the digital port, then proceeds to step 116 where transmission confirmation data is added, and further to step 118 where data is transmitted. An affirmative response in decision blocks 104 and 112 leads to step 120 where an error bit is loaded into the digital port.

  Following the transmission of data (step 118), the routine proceeds to step 122 where the system controller digital port confirms the transmission and then proceeds to decision step 124 to investigate whether an error has been detected. If no error has been detected, the routine proceeds to step 126 where the data is stored in the memory of the system controller and then proceeds to step 130 and from there to step 102 where all feature data is stored. The entire routine is repeated until it is transferred from the ASIC MSC to the system controller. A positive determination of the decision block also returns to step 102.

  FIGS. 4a and 4b show data acquisition in a typical detection element (SE1). In step 150, the system controller sends a command to transmit the detection element data in element SE1, and in step 152, the digital port receives and confirms the transmission. Decision step 154 determines whether an error has been detected; if a negative decision is made, the routine proceeds to step 156 where the logic block decodes the command and controls other circuit blocks to execute the command. Process step 158 performs a parity check and reaches another error detection decision block 160. A negative response there leads to step 162, which transfers circuit calibration data associated with the sensing element from the non-volatile memory to the various registers, and then step 164 sets the address of the analog multiplexer. In step 166, a time delay is provided to allow the circuit to stabilize, and then in step 168, an analog-to-digital conversion of the pressure signal, temperature signal, and sensing element SE1 diagnostic signal is performed. This ADC value is loaded into the digital port at step 170, and at step 172, the logic block adds a transmit bit to the data at the digital port. Returning to decision steps 154 and 160, in the case of a positive decision, proceed to step 174 where the detected error bit is loaded into the digital port. Process steps 172 and 174 lead to step 176 where the digital port transfers data and proceeds to step 178 where the system controller's digital port receives and confirms the transmission. Next, decision step 180 checks whether an error has been detected, and if a positive response, returns the routine to start step 150, and if a negative response, proceeds to step 182 to determine the pressure, temperature of SE1. And diagnostic data is stored in the memory of the system controller. In step 184, the system controller uses the stored feature data to mathematically correct the pressure, temperature, and diagnostic data of the sensing element SE1, and then in step 186, the system controller Compare the corrected diagnostic data of SE1 with the failure threshold. Decision block 190 checks whether a fault has been detected and, if negative, leads to step 192 where the system controller uses the pressure and temperature data of sensing element SE1 corrected in the control algorithm, In the case of a positive response, the data is not used in the control algorithm and the system controller reports an error.

  5a and 5b show the diagnostic data acquisition sequence in one test, ie reference bridge RB1. This sequence begins at step 200, where the system controller sends a command to the ASIC MSC to transmit data for bridge RB1, and then proceeds to step 202 where the ASIC digital port receives the transmission. The process proceeds to error detection step 204. The negative response there leads to step 206, where the logic block decodes the command and controls the other circuit blocks to execute the command, then proceeds to step 208 to perform a parity check and the contents Inspect. The negative response of error detection step 210 leads to step 212 where the circuit calibration data associated with bridge RB1 is transferred from the non-volatile memory to the appropriate register and then proceeds to step 214 where the analog multiplexer address. Is set. Step 216 provides a time delay to stabilize the circuit, and then in step 218 the pressure signal, temperature signal, and sensing element diagnostic signal are converted from analog to digital form. In step 220, the converted value is loaded into the digital port, and in step 222, the logic block adds a transmission confirmation to the digital port data. Returning to steps 204 and 210, if an error is detected, proceed to step 224 where the error bit is loaded into the digital port and then proceed to step 222 where the confirmation bit is added. Step 222 then proceeds to step 226 where the digital port transmits data and then proceeds to step 228 where the system controller digital port receives and confirms the transmission. If an error is detected, the routine returns to start step 200, and if no error is detected, the routine proceeds to step 232, where the pressure, temperature, and diagnostic data for bridge RB1 is stored in the system controller. Stored in the memory. Next, in step 234, the system controller calculates the difference between the data measured by the bridge RB1 and the characteristic data of the corresponding bridge RB1. In process step 236, the system controller compares the difference to an acceptable error limit and in step 238 checks whether an error has been detected. The negative decision here leads to step 240, where the system controller determines that the ASIC has passed the diagnostic check, while the positive decision leads to step 242, where the system controller determines that an error has occurred. And report the error.

  Although embodiments of the present invention have been disclosed in detail, various modifications, such as using sensing elements responsive to the aforementioned acceleration, torque, force, etc., depart from the spirit of the present invention or the appended claims. It should be understood that it will be adopted without any problems. Furthermore, it should be understood that the bridge bias can be multiplexed if desired, without multiplexing the ground connection, or in addition to multiplexing the ground connection.

  (Related Application) 35 U.S. of US Provisional Application No. 60 / 264,473, filed Jan. 26, 2001. S. C. 119 (e) claims the rights under (1).

FIG. 2 is a schematic diagram illustrating a plurality of state response detection elements, a multiple detection element adjustment circuit in the form of an ASIC, and a system controller in the form of a microprocessor. FIG. 2 is a schematic block circuit diagram showing the multiple detection element adjustment ASIC shown in FIG. 1 with one detection element shown as. 6 shows an initialization sequence for transferring feature data from the ASIC to the system controller. 6 shows an initialization sequence for transferring feature data from the ASIC to the system controller. An example data sequence for one sensing element (SE1) is shown. An example data sequence for one sensing element (SE1) is shown. Fig. 4 shows a diagnostic data acquisition sequence for one reference bridge (RB1) as an example. Fig. 4 shows a diagnostic data acquisition sequence for one reference bridge (RB1) as an example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bridge type detection element 2 Bridge type detection element 3 Bridge type detection element 4 Bridge type detection element 5 Bridge type detection element 6 Bridge type detection element 10 ASIC
10a Analog multiplexer 10b Analog multiplexer 10c Analog multiplexer 10d1 Bias resistor 10f Common signal adjustment circuit path 10f2 Addition network 10f3 Variable gain amplifier 10h Non-volatile memory section 10k Digital port 10m Detection element diagnosis circuit path 12 System controller BR1 Diagnostic test bridge BR2 Diagnostic test Bridge INM Minus output node INP Plus output node

Claims (20)

A state response detection system,
A plurality of state response detecting elements having outputs and detecting one state of pressure, acceleration, load and torque;
An electronic circuit including at least one multiplexer having an addressable input connected to outputs of the plurality of state response detection elements, the at least one multiplexer receiving an output signal of the state response detection element based on calibration data Having an output connected to a signal conditioning circuit path including an adjustment component to be adjusted;
The electronic circuit further includes a non-volatile memory that stores characteristic data used by an external controller to correct an output signal adjusted by the adjustment component, and a data port operable based on a command from the external controller ; Including
The data port transfers data from a non-volatile memory to the multiplexer for addressing the multiplexer, and the data port is addressed by the multiplexer to adjust the output signal of each state response detection element Transfer the calibration data of the non-volatile memory to the adjustment component for the state response detection element connected to the input, and the data port corrects the output signal adjusted by the adjustment component by an external controller. A status response detection system that transfers the feature data to an external controller to enable Each of the plurality of state response detection elements includes a bridge network, each bridge network having a bridge voltage node, a ground node, a positive output node, and a negative output node;
The state response detection system is further connected in series between a voltage source and a respective bridge voltage node, and a biased resistance value selected based on calibration data stored in the nonvolatile memory is supplied to the bridge voltage node. The status response detection system of claim 1, comprising a resistor to be supplied. The electronic circuit further includes first and second test bridge networks having fixed resistance values , wherein the first and second test bridge networks are respectively a bridge voltage node, a ground node, and a positive output. A node and a negative output node,
The positive and negative output nodes of the first and second test bridge networks are connected to the signal conditioning circuit path through the multiplexer,
The positive and negative output nodes of the first test bridge network provide a first value signal, and the positive and negative output nodes of the second test bridge network provide a second value signal. The condition response detection system of claim 1, wherein the first and second test bridge circuitry provides data for diagnosing a fault in the electronic circuit. The state response detection system according to claim 1, wherein the electronic circuit is an ASIC. State response detection system further detecting element diagnostics to provide diagnostic signal adjustment part only contains and selected state response detection element for adjusting the output signal of the status response detection element based on the adder circuit and the calibration data has a circuit path, the plus output node and a minus output node status response detection element connected to the input addressed by the multiplexer are added being connected to said adder circuit, the added value, the adjustment component Supplied to
2. The diagnostic signal and feature data stored in the non-volatile memory are transmitted by the data port to an external controller to enable an external controller to correct the diagnostic signal. Condition response detection system. The electronic circuit further includes first and second test bridge networks having fixed resistance values , wherein the first and second test bridge networks are respectively a bridge voltage node, a ground node, and a positive output. A node and a negative output node,
The positive output node and the negative output node of the first and second test bridge networks are connected to the detection element diagnostic circuit path through the multiplexer,
The positive and negative output nodes of the first test bridge network provide a first value signal, and the positive and negative output nodes of the second test bridge network provide a second value signal. The state response detection system according to claim 5, wherein the first and second test bridge networks supply data for diagnosing a failure in the detection element diagnosis circuit path. The electronic circuit further includes first and second test bridge networks , wherein the first and second test bridge networks are respectively a bridge voltage node, a ground node, a positive output node, and a negative output node. Have
The positive and negative output nodes of the first and second test bridge networks are connected to the signal conditioning circuit path through the multiplexer,
The positive and negative output nodes of the first test bridge network provide a first value signal, and the positive and negative output nodes of the second test bridge network provide a second value signal. and, first and second test bridge network allows the diagnosis of the fault state response detection element is operating, the state response detection system according to claim 2. The state response detection system according to claim 1, wherein the detected state is pressure. A state response detection system,
A plurality of state response detection elements that generate a state dependent voltage output, wherein the detected state is one of pressure, acceleration, load, and torque, each of the state response detection elements including a bridge voltage node and The plurality of state response detection elements having a bridge network having a ground node, a positive output node, and a negative output node;
A voltage source;
Each bridge voltage node connected to the voltage source;
An electronic circuit having first, second, and third multiplexers, each multiplexer having an output and a plurality of addressable inputs, wherein the positive output node of each state response detection element is a first And the negative output node of each state response detection element is connected to each input of the second multiplexer, and the ground node of each state response detection element is connected to each input of the third multiplexer. The electronic circuit, wherein each register is connected to a first, second, and third multiplexer;
Signal ground to which the output of the third multiplexer is connected;
A signal conditioning circuit path having a differential amplifier having a positive input, a negative input, and an output, wherein the output of the first multiplexer is connected to the positive input of the differential amplifier, and the output of the second multiplexer is The signal conditioning circuit path further includes an offset correction network having an adder circuit having an output and an input, the input of the offset correction network is connected to the output of the differential amplifier, and the signal conditioning circuit is connected to the negative input. The path further includes an offset circuit controlled by a register to provide a correction proportional to the bridge voltage, and the signal conditioning circuit path further has an input connected to the output of the offset correction network and gain correction Said signal conditioning circuit path comprising a gain correction network having a variable gain amplifier controlled by a register; and
A digital port;
An analog-to-digital converter having an input and an output, the analog-to-digital converter receiving the output of the gain correction network and supplying a digital signal corresponding to the detected state to the digital port;
A logic controller and a non-volatile memory, wherein the non-volatile memory is connected to a number of registers under the control of the logic controller, and the digital port transmits data to an external controller and from the external controller Forms an interface for receiving data, and the non-volatile memory provides data to the external controller to allow the external controller to correct for errors in the detection signal adjusted by the signal conditioning circuit path The logic control device provides an instruction to obtain a detection signal of the selected state response detection element, the logic control device and the nonvolatile memory;
Including state response detection system. The state response detection system is further connected in series between the voltage source and the respective bridge voltage node, and a selected bias resistance value is transferred to each state response detection element when the state response detection element is selected. The state response detection system according to claim 9 , comprising a resistor to be supplied and a register connected to the resistor and receiving data from a nonvolatile memory and controlling a value of the resistor. The state response detection system according to claim 9, wherein the state is pressure. The electronic circuit further includes first and second test bridge networks having fixed resistance values , wherein the first and second test bridge networks are respectively a bridge voltage node, a ground node, and a positive output. A node and a negative output node,
The positive output node, the negative output node, and the ground node of the first and second test bridge networks are connected to the signal conditioning circuit path and the signal ground through the first, second, and third multiplexers,
The positive and negative output nodes of the first test bridge network provide a first value signal, and the positive and negative output nodes of the second test bridge network provide a second value signal. The status response detection system according to claim 9, wherein the first and second test bridge circuitry provides data for diagnosing an electronic circuit failure. The electronic circuit further includes first and second test bridge networks having fixed resistance values , wherein the first and second test bridge networks are respectively a bridge voltage node, a ground node, and a positive output. A node and a negative output node,
The positive and negative output nodes of the first and second test bridge networks are connected to the signal conditioning circuit path through the multiplexer,
The positive and negative output nodes of the first test bridge network provide a first value signal, and the positive and negative output nodes of the second test bridge network provide a second value signal. and, first and second test bridge network allows the diagnosis of the fault state response detection element is operating, the state response detection system of claim 10. The state response detection system according to claim 10, wherein the electronic circuit is an ASIC. State response detection system further adder circuit and the output signal of the status response detection element based on the calibration data to adjust the viewing including the adjustment component, and the detection element diagnostic circuit for providing a diagnostic signal in the selected state response detection element A positive output node and a negative output node of a state response detection element having a path and connected to inputs addressed by the first and second multiplexers are connected to the adder circuit for addition, and the added value is is supplied to the adjusting part,
The diagnostic signal and the data for correction stored in said nonvolatile memory is transmitted to the external controller in order to allow the external controller to correct the said diagnostic signal, status response according to claim 9 Detection system. The electronic circuit further includes first and second test bridge networks having fixed resistance values , wherein the first and second test bridge networks are respectively a bridge voltage node, a ground node, and a positive output. A node and a negative output node,
The positive output node, the negative output node, and the ground node of the first and second test bridge networks are connected to the detection element diagnostic circuit path and the signal ground through first, second, and third multiplexers,
The positive and negative output nodes of the first test bridge network provide a first value signal, and the positive and negative output nodes of the second test bridge network provide a second value signal. The state response detection system according to claim 15, wherein the first and second test bridge networks supply data for diagnosing a failure in the detection element diagnosis circuit path. A method in a state response detection system having a plurality of state response detection bridge elements, comprising:
Providing a bias resistance value for each state detection bridge element;
Multiplexer, signal conditioning circuit path having signal conditioning components for regulating output signal of state response detection bridge element based on calibration data , analog-digital converter, logic control device, non-volatile memory, and electronic having digital port for transmitting / receiving data Providing a circuit;
Forming the electronic circuit as an ASIC;
A step of obtaining electronic calibration data, and stores the calibration data in non-volatile memory for each state detection bridge element during manufacture of the state response detection system,
Connecting the electronic circuit to an external controller;
Transferring data from the non-volatile memory to allow an external controller to perform corrections on the digital signal adjusted by the signal conditioning component ;
Selecting an address of a multiplexer to connect the output of the selected state detection bridge element to the signal conditioning circuit path, and transmitting the calibration data to the signal conditioning component in the signal conditioning circuit path;
Using said calibration data sent from the non-volatile memory, and adjusts the output signal of the state detection bridge elements selected, and providing the regulated output signal,
Converting the adjusted output signal from an analog format to a digital format in an analog-to-digital converter and providing a digital signal;
Transmitting the digital signal to an external controller;
Completing the adjustment of the adjusted output signal by correcting the digital signal in an external controller using the correction data transferred from the nonvolatile memory;
Including methods. The method to further comprise the step of forming the electronic circuit and the second test bridge providing a first test bridge and the second reference value to supply a first reference value,
18. The method of claim 17, wherein a fault in the electronic circuit is diagnosed using first and second reference values provided from the first and second test bridges. A method of a state response detection system having a plurality of state detection bridge elements, comprising:
Providing a bias resistance value for each state detection bridge element;
Forming a detection element diagnostic circuit path in the electronic circuit , the electronic circuit adding a plus output and a minus output of the selected state detection bridge element; and offset and gain correction of the signal adjustment circuit path Providing said reference data including offset and gain components corresponding to the network and used for diagnosing faults in connection between the state detection bridge element and the state detection bridge element;
Provided is an electronic circuit having a multiplexer, a signal conditioning circuit path having a signal conditioning component for regulating an output signal of a state detection bridge element , an analog-digital converter, a logic control device, a nonvolatile memory, and a digital port for transmitting and receiving data. Steps,
A step of obtaining electronic calibration data, and stores the calibration data in non-volatile memory for each state detection bridge element during manufacture of the state response detection system,
Connecting the electronic circuit to an external controller;
Transferring data from non-volatile memory to allow an external controller to make corrections to the digital signal adjusted by the offset and gain components ;
A step of selecting an address multiplexer outputs the selected state detection bridge element for connection to the signal conditioning circuit path, and transmits the calibration data to the offset and gain components of the signal conditioning circuit path,
Using said calibration data sent from the non-volatile memory, and adjusts the output signal of the state detection bridge elements selected, and providing the regulated output signal,
Converting the adjusted output signal from an analog format to a digital format in an analog-to-digital converter and providing a digital signal;
Transmitting the converted digital signal to an external controller;
Using the data transferred from the non-volatile memory to complete the adjustment of the adjusted output signal by correcting the digital signal in an external controller;
Including methods. The method of claim 18, wherein the electronic circuit includes the ability to diagnose a failure of an activated state response detection element .

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