JP4938346B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
- Publication number
- JP4938346B2 JP4938346B2 JP2006121575A JP2006121575A JP4938346B2 JP 4938346 B2 JP4938346 B2 JP 4938346B2 JP 2006121575 A JP2006121575 A JP 2006121575A JP 2006121575 A JP2006121575 A JP 2006121575A JP 4938346 B2 JP4938346 B2 JP 4938346B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- solder
- conductive member
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
- H10W72/01251—Changing the shapes of bumps
- H10W72/01255—Changing the shapes of bumps by using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07234—Using a reflow oven
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/853—On the same surface
- H10W72/856—Bump connectors and die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/923—Bond pads having multiple stacked layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
(a)導電部材40を形成する工程よりも前に、支持基板上に樹脂膜50を形成する工程(図4(a)〜図4(c))
(b)樹脂膜50中に、導電部材40を形成する工程(図5(a))
(c)樹脂膜50および導電部材40上に、当該樹脂膜50および導電部材40に接するようにTi膜62を形成する工程(図5(b)〜図5(c))
(d)Ti膜62上にNi膜66を形成する工程(図6(a)〜図6(c))
(e)導電部材40と電気的に接続されるように、Ni膜66上に半田14を介して半導体チップ10を載置する工程(図7(a)〜図7(c))
(f)半導体チップ10を載置する工程よりも後で且つ半導体チップ20を載置する工程よりも前に、上記支持基板を除去する工程(図8(a)〜図8(b))
(g)導電部材40と電気的に接続されるように、樹脂膜50の半導体チップ10と反対側に半田24を介して半導体チップ20を載置する工程(図9(a)〜図9(b))
10 半導体チップ
12 電極
14 半田
20 半導体チップ
22 電極
24 半田
30 接続部
40 導電部材
42 Cu膜
43 Au膜
44 Ni膜
50 樹脂膜
50a 孔
60 配線膜
62 Ti膜
64 Cu膜
66 Ni膜
70 配線
72 Ti膜
74 Cu膜
76 Ni膜
82 封止樹脂
84 アンダーフィル樹脂
86 アンダーフィル樹脂
90 外部電極端子
92 支持基板
94 メッキシード層
P30 接続部が形成される部分
P70 配線が形成される部分
R1 フォトレジスト
S1 第1面
S2 第2面
Claims (11)
- 絶縁膜と、
前記絶縁膜中に設けられ、上面が前記絶縁膜の第1面よりも下に位置した導電部材と、
前記絶縁膜の前記第1面側に設けられ、第1の半田を介して前記導電部材と電気的に接続された第1の電子回路部品と、
前記絶縁膜の前記第1面と反対の面である第2面側に設けられ、第2の半田を介して前記導電部材と電気的に接続された第2の電子回路部品と、
前記導電部材と前記第1の半田との間に設けられ、前記第1の半田の拡散を防ぐ第1の拡散防止金属膜と、
前記導電部材の少なくとも一部を構成し、前記第2の半田の拡散を防ぐ第2の拡散防止金属膜と、
前記絶縁膜の前記第1面上および前記絶縁膜中に当該絶縁膜および導電部材の前記上面に接して設けられ、前記第1の半田および前記第1の拡散防止金属膜の何れよりも、前記絶縁膜に対する密着性が高い密着金属膜と、
を備えることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第2の拡散防止金属膜は、前記密着金属膜に接している半導体装置。 - 請求項1または2に記載の半導体装置において、
前記第2の半田は、前記絶縁膜の前記第2面において前記導電部材に接している半導体装置。 - 請求項1乃至3いずれかに記載の半導体装置において、
前記密着金属膜は、Ti膜、TiN膜、W膜、TiW膜、Cr膜、Ta膜またはTaN膜である半導体装置。 - 請求項1乃至4いずれかに記載の半導体装置において、
前記第1および第2の拡散防止金属膜は、Ni膜またはNiV膜である半導体装置。 - 請求項1乃至5いずれかに記載の半導体装置において、
前記第1の拡散防止金属膜上に、前記第1の半田に接して設けられた第1のAu膜を備える半導体装置。 - 請求項1乃至6いずれかに記載の半導体装置において、
前記導電部材上に、前記第2の半田に接して設けられた第2のAu膜を備える半導体装置。 - 請求項1乃至7いずれかに記載の半導体装置において、
前記絶縁膜の前記第1面上に設けられ、前記密着金属膜を構成する材料を含む配線を備える半導体装置。 - 請求項1乃至8いずれかに記載の半導体装置において、
前記絶縁膜の厚みは、20μm以下である半導体装置。 - 絶縁膜中に、上面が前記絶縁膜の第1面よりも下に位置するように少なくとも一部が第2の拡散防止金属膜により構成された導電部材を形成する工程と、
前記絶縁膜の前記第1面上および前記絶縁膜中に、当該絶縁膜および導電部材の前記上面に接するように密着金属膜を形成する工程と、
前記密着金属膜上に、第1の拡散防止金属膜を形成する工程と、
前記導電部材と電気的に接続されるように、前記第1の拡散防止金属膜上に第1の半田を介して第1の電子回路部品を載置する工程と、
前記導電部材と電気的に接続されるように、前記絶縁膜の前記第1の電子回路部品と反対側に第2の半田を介して第2の電子回路部品を載置する工程と、を含み、
前記密着金属膜は、前記第1の半田および前記第1の拡散防止金属膜の何れよりも、前記絶縁膜に対する密着性が高く、
前記第1および第2の拡散防止金属膜は、それぞれ前記第1および第2の半田の拡散を防ぐものであることを特徴とする半導体装置の製造方法。 - 請求項10に記載の半導体装置の製造方法において、
前記導電部材を形成する工程よりも前に、支持基板上に前記絶縁膜を形成する工程と、
前記第1の電子回路部品を載置する工程よりも後で且つ前記第2の電子回路部品を載置する工程よりも前に、前記支持基板を除去する工程と、
を含む半導体装置の製造方法。
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006121575A JP4938346B2 (ja) | 2006-04-26 | 2006-04-26 | 半導体装置およびその製造方法 |
| US11/790,155 US7652375B2 (en) | 2006-04-26 | 2007-04-24 | Semiconductor device and method of manufacturing the same |
| CNB200710101059XA CN100541791C (zh) | 2006-04-26 | 2007-04-26 | 半导体器件及其制造方法 |
| US12/635,160 US8030201B2 (en) | 2006-04-26 | 2009-12-10 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006121575A JP4938346B2 (ja) | 2006-04-26 | 2006-04-26 | 半導体装置およびその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007294706A JP2007294706A (ja) | 2007-11-08 |
| JP4938346B2 true JP4938346B2 (ja) | 2012-05-23 |
Family
ID=38765021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006121575A Expired - Lifetime JP4938346B2 (ja) | 2006-04-26 | 2006-04-26 | 半導体装置およびその製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US7652375B2 (ja) |
| JP (1) | JP4938346B2 (ja) |
| CN (1) | CN100541791C (ja) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013135085A (ja) * | 2011-12-26 | 2013-07-08 | Ibiden Co Ltd | 半導体装置、配線板、及び配線板の製造方法 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61244035A (ja) * | 1985-04-22 | 1986-10-30 | Fujitsu Ltd | バンプ電極の接続方法 |
| JPH0656861B2 (ja) * | 1986-06-13 | 1994-07-27 | 日本電信電話株式会社 | 基板間接続子の製造法 |
| JP2930763B2 (ja) | 1991-02-26 | 1999-08-03 | 日本メクトロン株式会社 | 回路部品搭載用中間基板及びその製造法 |
| JP3169254B2 (ja) * | 1992-03-18 | 2001-05-21 | 株式会社日立製作所 | 多層配線基板 |
| JP2680232B2 (ja) | 1992-10-22 | 1997-11-19 | ローム株式会社 | 半田ワイヤによるワイヤーボンディング方法 |
| US6730541B2 (en) * | 1997-11-20 | 2004-05-04 | Texas Instruments Incorporated | Wafer-scale assembly of chip-size packages |
| JP3397689B2 (ja) * | 1998-06-01 | 2003-04-21 | 株式会社東芝 | マルチチップ半導体装置およびその製造方法 |
| JP2001217388A (ja) | 2000-02-01 | 2001-08-10 | Sony Corp | 電子装置およびその製造方法 |
| US20020074637A1 (en) * | 2000-12-19 | 2002-06-20 | Intel Corporation | Stacked flip chip assemblies |
| JP4092890B2 (ja) * | 2001-05-31 | 2008-05-28 | 株式会社日立製作所 | マルチチップモジュール |
| JP2003264260A (ja) * | 2002-03-08 | 2003-09-19 | Toshiba Corp | 半導体チップ搭載基板、半導体装置、半導体モジュール及び半導体装置実装基板 |
| TWI322448B (en) * | 2002-10-08 | 2010-03-21 | Chippac Inc | Semiconductor stacked multi-package module having inverted second package |
| US20040140571A1 (en) * | 2003-01-17 | 2004-07-22 | Matsushita Electric Industrial Co., Ltd. | Mounting structure of electronic device |
| JP2006012890A (ja) * | 2004-06-22 | 2006-01-12 | Canon Inc | 半導体装置およびその製造方法 |
| JP3905100B2 (ja) * | 2004-08-13 | 2007-04-18 | 株式会社東芝 | 半導体装置とその製造方法 |
| JP2006216758A (ja) * | 2005-02-03 | 2006-08-17 | Three M Innovative Properties Co | プリント回路基板の接続方法 |
| JP4344707B2 (ja) * | 2005-02-24 | 2009-10-14 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
| US7868457B2 (en) * | 2007-09-14 | 2011-01-11 | International Business Machines Corporation | Thermo-compression bonded electrical interconnect structure and method |
-
2006
- 2006-04-26 JP JP2006121575A patent/JP4938346B2/ja not_active Expired - Lifetime
-
2007
- 2007-04-24 US US11/790,155 patent/US7652375B2/en active Active
- 2007-04-26 CN CNB200710101059XA patent/CN100541791C/zh not_active Expired - Fee Related
-
2009
- 2009-12-10 US US12/635,160 patent/US8030201B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101127347A (zh) | 2008-02-20 |
| US7652375B2 (en) | 2010-01-26 |
| JP2007294706A (ja) | 2007-11-08 |
| US20100087058A1 (en) | 2010-04-08 |
| US8030201B2 (en) | 2011-10-04 |
| US20080136020A1 (en) | 2008-06-12 |
| CN100541791C (zh) | 2009-09-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101211798B (zh) | 焊料凸块结构及其制作方法 | |
| TWI413225B (zh) | 半導體結構以及半導體元件的形成方法 | |
| US6441500B1 (en) | Semiconductor device having resin members provided separately corresponding to externally connecting electrodes | |
| JP2005175019A (ja) | 半導体装置及び積層型半導体装置 | |
| KR20010070217A (ko) | 반도체 장치 및 그 제조 방법 | |
| JP2001135663A (ja) | 半導体装置及びその製造方法 | |
| CN102386147A (zh) | 半导体装置及半导体装置的制造方法 | |
| CN100524725C (zh) | 半导体装置及其制造方法 | |
| JP2001168231A5 (ja) | ||
| CN111613586B (zh) | 电子装置及电子装置的制造方法 | |
| CN108364924A (zh) | 半导体装置以及半导体装置的制造方法 | |
| JP2009016882A (ja) | 半導体装置およびその製造方法 | |
| JP4215571B2 (ja) | 半導体装置の製造方法 | |
| JP7582775B2 (ja) | 半導体装置 | |
| JPH11204560A (ja) | 半導体装置及びその製造方法 | |
| CN101017804A (zh) | 半导体器件及其制造方法 | |
| JP4465891B2 (ja) | 半導体装置 | |
| JP4938346B2 (ja) | 半導体装置およびその製造方法 | |
| JP4631223B2 (ja) | 半導体実装体およびそれを用いた半導体装置 | |
| US7358177B2 (en) | Fabrication method of under bump metallurgy structure | |
| JP5061010B2 (ja) | 半導体モジュール | |
| JP2007005357A (ja) | 半導体装置の製造方法 | |
| JP2004072043A (ja) | 半導体ウェハ及び半導体チップ並びに半導体装置とその製造方法 | |
| JP2004172163A (ja) | 半導体装置及びその製造方法 | |
| JP4286264B2 (ja) | 半導体装置及びその製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20090216 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090714 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110719 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110920 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120221 |
|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120223 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150302 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 4938346 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |