JP4939802B2 - Semiconductor circuit, display device, and electronic apparatus including the display device - Google Patents

Description

  The present invention relates to a semiconductor circuit. In particular, the present invention relates to a semiconductor circuit configured using transistors. In addition, the present invention relates to a display device including a semiconductor circuit and an electronic device including the display device.

  Note that the semiconductor circuit here refers to all circuits that can function by utilizing semiconductor characteristics.

  In a driver circuit of a display device, a semiconductor circuit that inputs a signal for controlling operation timing of a transistor is used in various semiconductor devices.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices and electronic devices are all semiconductor devices.

  FIG. 23 shows a configuration example of a conventional semiconductor circuit that constitutes a shift register circuit and a latch circuit (see, for example, Patent Document 1). The semiconductor circuit shown in FIG. 23 includes a first clocked inverter CKINV1, a second clocked inverter CKINV2, and an inverter circuit INV.

  An input signal IN is input from the outside to the input terminal of the first clocked inverter CKINV1, and the output terminal of CKINV1 is connected to the input terminal of the inverter INV and the output terminal of the second clocked inverter CKINV2. ing. The input terminal of the second clocked inverter CKINV2 is connected to the output terminal of the inverter INV.

  When the input signal IN is input to the input terminal, it is synchronized with the timing control signal TP and the inverted timing control signal TPB whose polarity is inverted, which are input to the first clocked inverter CKINV1 and the second clocked inverter CKINV2, respectively. Then, the output signal OUT1 is output from the output terminal.

  FIG. 24 is a circuit diagram in which the first clocked inverter CKINV1, the second clocked inverter CKINV2, and the inverter circuit INV that constitute the semiconductor circuit having the configuration shown in FIG. The number of transistors constituting the semiconductor circuit shown in FIG. 24 is four in the first clocked inverter CKINV1, four in the second clocked inverter CKINV2, and two in the inverter INV.

In the shift register circuit and the latch circuit of the driver circuit, a plurality of semiconductor circuits shown in FIG. 24 are provided to output a signal shifted by a half cycle of the input signal, and to hold and capture the input signal.
JP-A-8-161896

  The configuration of the semiconductor circuit of FIG. 23 and FIG. 24 constituting the conventional shift register circuit and latch circuit is formed by using two clocked inverters and one inverter, and the total number of transistors is calculated as shown in FIG. There will be ten.

  Since the above-described semiconductor circuit forms a shift register circuit and a latch circuit using a plurality of stages, the number of transistors for manufacturing the shift register circuit and the latch circuit increases in proportion to the number of transistors in the semiconductor circuit. Therefore, in the active matrix display device, the layout area of the driver circuit is increased due to an increase in the number of transistors as the number of columns and rows in the pixel portion is increased. In addition, there is a problem that the yield due to the variation of the transistors becomes worse as the number of transistors to be configured increases.

  As described above, the semiconductor circuits constituting the current shift register circuit and latch circuit have problems such as an increase in layout area and deterioration in yield due to the configuration. The present invention has been devised in view of the above-described problems, and provides a semiconductor circuit, a display device, and an electronic apparatus including the display device that can solve the above problems.

  In order to solve the above problems, in the present invention, instead of two clocked inverters having eight transistors in the semiconductor circuit of FIGS. 23 and 24, an n-channel transistor and a p-channel transistor are used. A semiconductor circuit capable of reducing the number of transistors by using a transistor is provided.

  More specifically, the semiconductor circuit of the present invention includes a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, and an inverter. And a timing control signal is input to the gate terminal of the first n-channel transistor and the gate terminal of the first p-channel transistor to which the first input signal is input. A first terminal of the first n-channel transistor, a first terminal of the first p-channel transistor to which an inversion timing control signal is input, and the first n electrically connected to each other. A second terminal of the channel transistor and a second terminal of the first p-channel transistor, the first n-channel transistor The second terminal and the second terminal of the first p-channel transistor are electrically connected to the input terminal of the inverter circuit, and the second signal output from the output terminal of the inverter circuit is input. A gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor, and a first terminal of the second p-channel transistor to which the timing control signal is input, A first terminal of the second n-channel transistor to which the inversion timing control signal is input, a second terminal of the second n-channel transistor electrically connected to each other, and the second p A second terminal of the channel transistor, and a second terminal of the second n-channel transistor and the second p-channel transistor. The second terminal of the capacitor has a configuration that is electrically connected to an input terminal of the inverter circuit.

  Still another semiconductor circuit of the present invention includes a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, an inverter circuit, And a gate terminal of the first n-channel transistor to which a first input signal is input and a gate terminal of the first p-channel transistor, and the first to which a timing control signal is input. A first terminal of the p-channel transistor, a first terminal of the first n-channel transistor to which an inversion timing control signal is input, and the first n-channel transistor electrically connected to each other And a second terminal of the first p-channel transistor, and a second terminal of the first n-channel transistor. The terminal and the second terminal of the first p-channel transistor are electrically connected to the input terminal of the inverter circuit, and the second signal output from the output terminal of the inverter circuit is input thereto. A gate terminal of a second n-channel transistor, a gate terminal of the second p-channel transistor, a first terminal of the second n-channel transistor to which the timing control signal is input, and the inversion timing A first terminal of the second p-channel transistor to which a control signal is input, a second terminal of the second n-channel transistor and the second p-channel transistor that are electrically connected to each other The second terminal of the second n-channel transistor and the second p-channel transistor. Second terminal is a structure that is electrically connected to an input terminal of the inverter circuit.

  The timing control signal of the present invention may be a latch signal, and the inverted timing control signal may be an inverted latch signal.

  The timing control signal of the present invention may be a clock signal, and the inverted timing control signal may be an inverted clock signal.

  Still another semiconductor circuit according to the present invention includes a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, and a first inverter. A circuit, a third n-channel transistor, a third p-channel transistor, a fourth n-channel transistor, a fourth p-channel transistor, and a second inverter circuit. And a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is input, and the first n-channel transistor to which a clock signal is input And the first terminal of the first p-channel transistor to which the inverted clock signal is input are electrically connected to each other. A second terminal of the first n-channel transistor and a second terminal of the first p-channel transistor, and a second terminal of the first n-channel transistor, The second terminal of the first p-channel transistor is electrically connected to the input terminal of the first inverter circuit, and the second terminal output from the output terminal of the first inverter circuit. A gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a signal is input, and a first terminal of the second p-channel transistor to which the clock signal is input And a first terminal of the second n-channel transistor to which the inverted clock signal is input, and the second n-channel transistor electrically connected to each other A second terminal and a second terminal of the second p-channel transistor, and a second terminal of the second n-channel transistor and a second terminal of the second p-channel transistor. The terminal is electrically connected to the input terminal of the first inverter circuit, and the gate terminal of the third n-channel transistor and the gate of the third p-channel transistor to which the second input signal is input. A terminal, a first terminal of the third p-channel transistor to which a clock signal is input, and a first terminal of the third n-channel transistor to which an inverted clock signal is input. A second terminal of the third n-channel transistor and a second terminal of the third p-channel transistor connected to each other, and the third n-channel transistor. The second terminal of the register and the second terminal of the third p-channel transistor are electrically connected to the input terminal of the second inverter circuit, and output from the output terminal of the second inverter circuit. A gate terminal of the fourth n-channel transistor and a gate terminal of the fourth p-channel transistor to which the third signal is input, and the fourth n-channel transistor to which the clock signal is input A first terminal of the fourth p-channel transistor to which the inverted clock signal is input, and a second terminal of the fourth n-channel transistor electrically connected to each other And a second terminal of the fourth p-channel transistor, and a second terminal of the fourth n-channel transistor and the fourth p-channel transistor. The second terminal of Njisuta was configured to be electrically connected to an input terminal of the second inverter circuit.

  Still another semiconductor circuit according to the present invention includes a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, and a first inverter. A circuit, a third n-channel transistor, a third p-channel transistor, a fourth n-channel transistor, a fourth p-channel transistor, and a second inverter circuit. The first n-channel transistor to which the first input signal is input, the gate terminal of the first p-channel transistor and the first p-channel transistor to which the clock signal is input. And the first terminal of the first n-channel transistor to which the inverted clock signal is input are electrically connected to each other. A second terminal of the first n-channel transistor and a second terminal of the first p-channel transistor, and a second terminal of the first n-channel transistor, The second terminal of the first p-channel transistor is electrically connected to the input terminal of the first inverter circuit, and the second terminal output from the output terminal of the first inverter circuit. A gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which a signal is input, and a first terminal of the second n-channel transistor to which the clock signal is input And the second n-channel transistor electrically connected to the first terminal of the second p-channel transistor to which the inverted clock signal is input A second terminal and a second terminal of the second p-channel transistor, and a second terminal of the second n-channel transistor and a second terminal of the second p-channel transistor. The terminal is electrically connected to the input terminal of the first inverter circuit, and the gate terminal of the third n-channel transistor and the gate of the third p-channel transistor to which the second input signal is input. A terminal, a first terminal of the third n-channel transistor to which a clock signal is input, and a first terminal of the third p-channel transistor to which an inverted clock signal is input. A second terminal of the third n-channel transistor and a second terminal of the third p-channel transistor connected to each other, and the third n-channel transistor. The second terminal of the register and the second terminal of the third p-channel transistor are electrically connected to the input terminal of the second inverter circuit, and output from the output terminal of the second inverter circuit. A gate terminal of the fourth n-channel transistor and a gate terminal of the fourth p-channel transistor to which the third signal is input, and the fourth p-channel transistor to which the clock signal is input A first terminal of the fourth n-channel transistor to which the inverted clock signal is input, and a second terminal of the fourth n-channel transistor that is electrically connected to each other. And a second terminal of the fourth p-channel transistor, and a second terminal of the fourth n-channel transistor and the fourth p-channel transistor. The second terminal of Njisuta was configured to be electrically connected to an input terminal of the second inverter circuit.

  Further, the n-channel transistor and the p-channel transistor of the present invention may be constituted by a thin film transistor formed over a glass substrate.

  Further, the n-channel transistor and the p-channel transistor of the present invention may be formed over a single crystal substrate.

  Further, according to the present invention, an n-channel transistor and a p-channel transistor are used instead of the two clocked inverters in the semiconductor circuit of FIGS. A display device that can be reduced can be provided.

  More specifically, the display device of the present invention includes a gate driver, a source driver, the gate driver, and a pixel portion connected to the source driver. The source driver includes a shift register circuit and a latch circuit. The gate driver includes a shift register circuit, the shift register circuit and the latch circuit of the source driver, and the shift register circuit of the gate driver are each a first n-channel transistor and a first p-channel transistor. A semiconductor circuit including a transistor, a second n-channel transistor, a second p-channel transistor, and an inverter circuit, wherein the semiconductor circuit receives a first input signal; A gate terminal of a first n-channel transistor and the first p-channel transistor A first terminal of the first n-channel transistor to which a timing control signal is input, and a first terminal of the first p-channel transistor to which an inverted timing control signal is input. A second terminal of the first n-channel transistor and a second terminal of the first p-channel transistor electrically connected to each other, and the first n-channel transistor The second terminal and the second terminal of the first p-channel transistor are electrically connected to the input terminal of the inverter circuit, and the second signal output from the output terminal of the inverter circuit is input. The timing control signal is input to the gate terminal of the second n-channel transistor and the gate terminal of the second p-channel transistor. The first terminal of the second p-channel transistor and the first terminal of the second n-channel transistor to which the inversion timing control signal is input are electrically connected to the second terminal. a second terminal of the n-channel transistor and a second terminal of the second p-channel transistor, and a second terminal of the second n-channel transistor and the second p-channel transistor. The second terminal of the transistor is electrically connected to the input terminal of the inverter circuit.

  Still another display device of the present invention includes a gate driver, a source driver, and the gate driver, a pixel portion connected to the source driver, and the source driver includes a shift register circuit and a latch circuit, The gate driver includes a shift register circuit, and each of the source driver shift register circuit and the gate driver shift register circuit includes a first n-channel transistor, a first p-channel transistor, and a second a semiconductor circuit including an n-channel transistor, a second p-channel transistor, and an inverter circuit, wherein the semiconductor circuit receives the first input signal; A gate terminal of the transistor and a gate terminal of the first p-channel transistor; The first terminal of the first p-channel transistor to which the timing control signal is input and the first terminal of the first n-channel transistor to which the inversion timing control signal is input are electrically connected to each other. A second terminal of the first n-channel transistor, and a second terminal of the first p-channel transistor, and a second terminal of the first n-channel transistor, The second terminal of the first p-channel transistor is electrically connected to the input terminal of the inverter circuit, and the second signal output from the output terminal of the inverter circuit is input to the second terminal. A gate terminal of an n-channel transistor and a gate terminal of the second p-channel transistor, and the second n-channel transistor to which the timing control signal is input A first terminal of a transistor, a first terminal of the second p-channel transistor to which the inversion timing control signal is input, and a second of the second n-channel transistor electrically connected to each other. And a second terminal of the second p-channel transistor, and a second terminal of the second p-channel transistor and a second terminal of the second p-channel transistor, The inverter circuit is electrically connected to the input terminal.

  Still another display device of the present invention includes a gate driver, a source driver, and the gate driver, a pixel portion connected to the source driver, and the source driver includes a shift register circuit and a latch circuit, The gate driver includes a shift register circuit, and each of the source driver shift register circuit and the gate driver shift register circuit includes a first n-channel transistor, a first p-channel transistor, and a second an n-channel transistor, a second p-channel transistor, a first inverter circuit, a third n-channel transistor, a third p-channel transistor, a fourth n-channel transistor, 4 p-channel transistors and a second inverter circuit. The semiconductor circuit has a plurality of stages, and the semiconductor circuit includes a gate terminal of the second n-channel transistor to which the second signal output from the output terminal of the first inverter circuit is input, and the second A gate terminal of the p-channel transistor, a first terminal of the second p-channel transistor to which the clock signal is input, and a second terminal of the second n-channel transistor to which the inverted clock signal is input. A second terminal of the second n-channel transistor and a second terminal of the second p-channel transistor, which are electrically connected to each other, and the second n A second terminal of the channel transistor and a second terminal of the second p-channel transistor are electrically connected to an input terminal of the first inverter circuit, and The third n-channel transistor gate terminal and the third p-channel transistor gate terminal to which the input signal is input and the first p-channel transistor first terminal to which the clock signal is input are input. A terminal, a first terminal of the third n-channel transistor to which an inverted clock signal is input, a second terminal of the third n-channel transistor electrically connected to each other, and the third terminal and a second terminal of the third n-channel transistor and a second terminal of the third p-channel transistor are connected to the second inverter circuit. The fourth n-channel transistor that is electrically connected to the input terminal and receives the third signal output from the output terminal of the second inverter circuit. And the fourth terminal of the fourth p-channel transistor, the first terminal of the fourth n-channel transistor to which the clock signal is input, and the first terminal to which the inverted clock signal is input. A first terminal of the four p-channel transistors, a second terminal of the fourth n-channel transistor and a second terminal of the fourth p-channel transistor electrically connected to each other. And a second terminal of the fourth n-channel transistor and a second terminal of the fourth p-channel transistor are electrically connected to an input terminal of the second inverter circuit; did.

Still another display device of the present invention includes a gate driver, a source driver, and the gate driver, a pixel portion connected to the source driver, and the source driver includes a shift register circuit and a latch circuit, The gate driver includes a shift register circuit, and each of the source driver shift register circuit and the gate driver shift register circuit includes a first n-channel transistor, a first p-channel transistor, and a second an n-channel transistor, a second p-channel transistor, a first inverter circuit, a third n-channel transistor, a third p-channel transistor, a fourth n-channel transistor, 4 p-channel transistors and a second inverter circuit. The semiconductor circuit has a plurality of stages, and the semiconductor circuit includes a gate terminal of the first n-channel transistor and a gate terminal of the first p-channel transistor to which a first input signal is input, and a clock signal. A first terminal of the first p-channel transistor to which is input, a first terminal of the first n-channel transistor to which an inverted clock signal is input,
A second terminal of the first n-channel transistor and a second terminal of the first p-channel transistor that are electrically connected to each other; And the second terminal of the first p-channel transistor are electrically connected to the input terminal of the first inverter circuit, and output from the output terminal of the first inverter circuit. A gate terminal of the second n-channel transistor and a gate terminal of the second p-channel transistor to which the second signal is input, and the second n-channel transistor to which the clock signal is input A first terminal of the second p-channel transistor to which the inverted clock signal is input, and the second n-channel electrically connected to each other. A second terminal of the second n-channel transistor, and a second terminal of the second p-channel transistor, and a second terminal of the second p-channel transistor. The second terminal is electrically connected to the input terminal of the first inverter circuit, and the gate terminal of the third n-channel transistor and the third p-channel to which the second input signal is input. A gate terminal of the n-type transistor, a first terminal of the third n-channel transistor to which a clock signal is input, a first terminal of the third p-channel transistor to which an inverted clock signal is input, A second terminal of the third n-channel transistor and a second terminal of the third p-channel transistor which are electrically connected to each other; The second terminal of the n-channel transistor and the second terminal of the third p-channel transistor are electrically connected to the input terminal of the second inverter circuit, and the output of the second inverter circuit A gate terminal of the fourth n-channel transistor and a gate terminal of the fourth p-channel transistor to which the third signal output from the terminal is input; and the fourth p to which the clock signal is input. A first terminal of the channel type transistor, a first terminal of the fourth n-channel type transistor to which the inverted clock signal is input, and a fourth terminal of the fourth n-channel type transistor electrically connected to each other. 2 terminal and the second terminal of the fourth p-channel transistor, and the second terminal of the fourth n-channel transistor and the second terminal The second terminal of the four p-channel transistors is electrically connected to the input terminal of the second inverter circuit.

  Further, the n-channel transistor and the p-channel transistor of the present invention may be constituted by a thin film transistor formed over a glass substrate.

  Further, the n-channel transistor and the p-channel transistor of the present invention may be formed over a single crystal substrate.

  Further, the display device of the present invention may use a liquid crystal or an EL element.

  Further, according to the present invention, an n-channel transistor and a p-channel transistor are used instead of the two clocked inverters in the semiconductor circuit of FIGS. An electronic device that can be reduced can be provided.

More specifically, the electronic device of the present invention includes a display panel including a gate driver, a source driver, and the pixel driver connected to the gate driver and the source driver. A shift register circuit, and a latch circuit, wherein the gate driver includes a shift register circuit, and the shift register circuit and latch circuit of the source driver and the shift register circuit of the gate driver are each a first n-channel transistor. And a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, and an inverter circuit, the semiconductor circuit comprising: And the first n-channel transistor to which the input signal is input and the first n-channel transistor and the first And the gate terminal of the p-channel type transistor, a first terminal of the first n-channel transistor timing control signal is input,
A first terminal of the first p-channel transistor to which an inversion timing control signal is input, a second terminal of the first n-channel transistor and the first p-channel that are electrically connected to each other A second terminal of the first n-channel transistor and a second terminal of the first p-channel transistor are electrically connected to an input terminal of the inverter circuit. And the gate terminal of the second n-channel transistor and the gate terminal of the second p-channel transistor to which the second signal output from the output terminal of the inverter circuit is input, A first terminal of the second p-channel transistor to which a timing control signal is input, and the second n to which the inversion timing control signal is input A first terminal of a channel transistor, a second terminal of the second n-channel transistor and a second terminal of the second p-channel transistor electrically connected to each other; The second terminal of the second n-channel transistor and the second terminal of the second p-channel transistor are electrically connected to the input terminal of the inverter circuit.

Still another electronic device according to another aspect of the invention includes a display panel including a gate driver, a source driver, and the pixel driver connected to the gate driver and the source driver. The source driver includes a shift register circuit. , And a latch circuit, the gate driver includes a shift register circuit, the shift register circuit of the source driver, and the shift register circuit of the gate driver are respectively a first n-channel transistor and a first p-channel transistor. A semiconductor circuit includes a channel transistor, a second n-channel transistor, a second p-channel transistor, and an inverter circuit, and the semiconductor circuit receives a first input signal. And a gate terminal of the first n-channel transistor and the first p-channel transistor. A first terminal of the first p-channel transistor to which a timing control signal is input, and a first terminal of the first n-channel transistor to which an inversion timing control signal is input. A second terminal of the first n-channel transistor and a second terminal of the first p-channel transistor electrically connected to each other, and the first n-channel transistor The second terminal and the second terminal of the first p-channel transistor are electrically connected to the input terminal of the inverter circuit, and the second signal output from the output terminal of the inverter circuit is input. The timing control signal is input to the gate terminal of the second n-channel transistor and the gate terminal of the second p-channel transistor. A first terminal of the second n-channel transistor,
The first terminal of the second p-channel transistor to which the inversion timing control signal is input, the second terminal of the second n-channel transistor electrically connected to each other, and the second p-channel transistor And a second terminal of the second n-channel transistor and a second terminal of the second p-channel transistor are electrically connected to an input terminal of the inverter circuit. Connected to each other.

  Still another electronic device according to another aspect of the invention includes a display panel including a gate driver, a source driver, and the pixel driver connected to the gate driver and the source driver. The source driver includes a shift register circuit. , And a latch circuit, the gate driver includes a shift register circuit, the shift register circuit of the source driver, and the shift register circuit of the gate driver are respectively a first n-channel transistor and a first p-channel transistor. A channel transistor, a second n-channel transistor, a second p-channel transistor, a first inverter circuit, a third n-channel transistor, a third p-channel transistor, and a fourth transistor N-channel transistor, fourth p-channel transistor, and second in-channel transistor And a plurality of stages of semiconductor circuits, wherein the semiconductor circuit includes a gate terminal of the first n-channel transistor to which a first input signal is input and the first p-channel. A gate terminal of a type transistor, a first terminal of the first n-channel type transistor to which a clock signal is input, a first terminal of the first p-channel type transistor to which an inverted clock signal is input, A second terminal of the first n-channel transistor and a second terminal of the first p-channel transistor that are electrically connected to each other; 2 terminal and the second terminal of the first p-channel transistor are electrically connected to the input terminal of the first inverter circuit, and the first inverter circuit. The second n-channel transistor to which the second signal output from the output terminal is input, the gate terminal of the second p-channel transistor and the second terminal to which the clock signal is input. A first terminal of the p-channel transistor, a first terminal of the second n-channel transistor to which the inverted clock signal is input, and the second n-channel transistor electrically connected to each other A second terminal of the second n-channel transistor and a second terminal of the second p-channel transistor. Is electrically connected to the input terminal of the first inverter circuit, and the gate terminal of the third n-channel transistor to which the second input signal is input. And a gate terminal of the third p-channel transistor, a first terminal of the third p-channel transistor to which a clock signal is input, and the third n-channel transistor to which an inverted clock signal is input A first terminal of the third n-channel transistor and a second terminal of the third p-channel transistor electrically connected to each other, and the third terminal A second terminal of the n-channel transistor and a second terminal of the third p-channel transistor are electrically connected to an input terminal of the second inverter circuit, and A gate terminal of the fourth n-channel transistor to which a third signal output from the output terminal is input, and a gate terminal of the fourth p-channel transistor; The first terminal of the fourth n-channel transistor to which the clock signal is input and the first terminal of the fourth p-channel transistor to which the inverted clock signal is input are electrically connected to each other. A second terminal of the fourth n-channel transistor and a second terminal of the fourth p-channel transistor, and a second terminal of the fourth n-channel transistor, The second terminal of the fourth p-channel transistor is electrically connected to the input terminal of the second inverter circuit.

  Still another electronic device according to another aspect of the invention includes a display panel including a gate driver, a source driver, and the pixel driver connected to the gate driver and the source driver. The source driver includes a shift register circuit. , And a latch circuit, the gate driver includes a shift register circuit, the shift register circuit of the source driver, and the shift register circuit of the gate driver are respectively a first n-channel transistor and a first p-channel transistor. A channel transistor, a second n-channel transistor, a second p-channel transistor, a first inverter circuit, a third n-channel transistor, a third p-channel transistor, and a fourth transistor N-channel transistor, fourth p-channel transistor, and second in-channel transistor And a plurality of stages of semiconductor circuits, wherein the semiconductor circuit includes a gate terminal of the first n-channel transistor to which a first input signal is input and the first p-channel. A gate terminal of the n-type transistor, a first terminal of the first p-channel transistor to which a clock signal is input, a first terminal of the first n-channel transistor to which an inverted clock signal is input, A second terminal of the first n-channel transistor and a second terminal of the first p-channel transistor that are electrically connected to each other; 2 terminal and the second terminal of the first p-channel transistor are electrically connected to the input terminal of the first inverter circuit, and the first inverter circuit. The second n-channel transistor to which the second signal output from the output terminal is input, the gate terminal of the second p-channel transistor and the second terminal to which the clock signal is input. A first terminal of the n-channel transistor, a first terminal of the second p-channel transistor to which the inverted clock signal is input, and the second n-channel transistor electrically connected to each other A second terminal of the second n-channel transistor and a second terminal of the second p-channel transistor. Is electrically connected to the input terminal of the first inverter circuit, and the gate terminal of the third n-channel transistor to which the second input signal is input. And a gate terminal of the third p-channel transistor, a first terminal of the third n-channel transistor to which a clock signal is input, and the third p-channel transistor to which an inverted clock signal is input A first terminal of the third n-channel transistor and a second terminal of the third p-channel transistor electrically connected to each other, and the third terminal A second terminal of the n-channel transistor and a second terminal of the third p-channel transistor are electrically connected to an input terminal of the second inverter circuit, and A gate terminal of the fourth n-channel transistor to which a third signal output from the output terminal is input, and a gate terminal of the fourth p-channel transistor; The first terminal of the fourth p-channel transistor to which the clock signal is input is electrically connected to the first terminal of the fourth n-channel transistor to which the inverted clock signal is input. A second terminal of the fourth n-channel transistor and a second terminal of the fourth p-channel transistor, and a second terminal of the fourth n-channel transistor, The second terminal of the fourth p-channel transistor is electrically connected to the input terminal of the second inverter circuit.

  The present invention also provides an electronic device in which the above-described display panel uses a liquid crystal or an EL element.

  The electronic device of the present invention includes a television receiver, a video camera, a digital camera, a goggle type display, a navigation system, a sound reproduction device, a computer, a game device, a mobile computer, a mobile phone, a portable game machine, an electronic book, and an image reproduction. Device.

  According to the present invention, the number of transistors constituting a semiconductor circuit can be reduced from 10 to 6, and the layout area can be reduced. In addition, when a plurality of semiconductor circuits such as a shift register circuit and a latch circuit are used, it is particularly effective to apply the semiconductor circuit of the present invention, which can suppress variation in performance when a transistor is manufactured, and can improve yield. Improvement can be expected.

  Further, in the display device using the semiconductor circuit of the present invention, the layout area of the peripheral circuit can be reduced as the area of the pixel portion is increased by reducing the number of transistors constituting the semiconductor circuit from 10 to 6. In addition, when the transistor of the pixel portion and the substrate are formed integrally, when the semiconductor circuit of the present invention is applied to the peripheral circuit, the number of transistors constituting the semiconductor circuit is reduced from 10 to 6, thereby improving the performance of the transistor. Since the variation can be suppressed, the yield can be improved.

  Further, in the electronic device using the semiconductor circuit of the present invention, the layout area of the display portion can be reduced, so that the electronic device can be reduced in size and weight. Moreover, a product with a high yield can be manufactured, and a cheaper product can be provided to the customer.

(Embodiment 1)

  FIG. 1A shows an embodiment of a semiconductor circuit according to the present invention. As shown in FIG. 1A, the first clocked inverter CKINV1 and the second clocked inverter CKINV2 of the conventional semiconductor circuit are replaced with a circuit composed of an n-channel transistor and a p-channel transistor. Here, an n-channel transistor and a p-channel transistor are respectively referred to as a first n-channel transistor 201a, a first p-channel transistor 201b, a second n-channel transistor 202a, and a second p-channel transistor 202b. And In this specification, the source electrode or drain electrode of the first n-channel transistor 201a to which the timing control signal TP is input and the source electrode or drain electrode of the second p-channel transistor 202b are used. Let the terminal be the first terminal. In addition, a terminal serving as a source electrode or a drain electrode of the first p-channel transistor 201b to which the inversion timing control signal TPB is input and a terminal serving as a source electrode or a drain electrode of the second n-channel transistor 202a are used as the first electrode. Terminal. In each transistor, the other terminal that is not input with the timing control signal or the inverted timing control signal is a second terminal.

  In addition, the second terminal of the first n-channel transistor and the second terminal of the first p-channel transistor are electrically connected to each other. In addition, the second terminal of the second p-channel transistor 202b and the second terminal of the second n-channel transistor 202a are electrically connected to each other.

  When the timing control signal TP is input to the first terminal of the first n-channel transistor 201a, the inverted timing control signal TPB is input to the first terminal of the first p-channel transistor 201b. On the other hand, when the inversion timing control signal TPB is input to the first terminal of the n-channel transistor 201a, the timing control signal TP is input to the first terminal of the first p-channel transistor 201b.

  The second terminal of the first n-channel transistor 201a is connected to the second terminal of the first p-channel transistor 201b. The gate electrodes of the first n-channel transistor 201a and the first p-channel transistor 201b serve as input terminals, and the second terminal of the first n-channel transistor 201a and the second of the first p-channel transistor 201b. Are connected to the input terminal of the inverter INV.

  Here, when the timing control signal TP is input to the first terminal of the first n-channel transistor 201a, the inverted timing control signal TPB is input to the first terminal of the first n-channel transistor 202a. The timing control signal TP is input to the first terminal of the second p-channel transistor 202b. On the other hand, when the inverted timing control signal TPB is input to the first terminal of the first n-channel transistor 201a, the timing control signal TP is input to the first terminal of the second n-channel transistor 202a. The inversion timing control signal TPB is input to the first terminal of the second p-channel transistor 202b.

  The second terminal of the second n-channel transistor 202a, which serves as the second clocked inverter CKINV2, is connected to the second terminal of the second p-channel transistor 202b. The gate electrodes of the second n-channel transistor 202a and the second p-channel transistor 202b are connected to the output terminal of the inverter INV, and the second terminal and the second p-channel transistor of the second n-channel transistor 202a are connected. A second terminal of the transistor 202b is connected to an input terminal of the inverter INV.

  The inverter INV includes an n-channel transistor 203a and a p-channel transistor 203b. The source electrode of the n-channel transistor 203a is kept at the low power supply potential Vss, and the drain electrode of the n-channel transistor 203a is connected to the drain electrode of the p-channel transistor 203b. The source electrode of the p-channel transistor 203b is kept at the high power supply potential Vdd. The gate electrodes of the n-channel transistor 203a and the p-channel transistor 203b are input terminals of the inverter INV, and the drain electrodes of the n-channel transistor 203a and the p-channel transistor 203b are output terminals of the inverter INV.

  FIG. 1B shows a timing chart showing an ideal driving method of the semiconductor circuit having the configuration shown in FIG. 1A, and its specific operation will be described below.

  The semiconductor circuit receives the timing control signal TP, the inverted timing control signal TPB in which the polarity of the timing control signal is inverted, and the input signal IN2. The timing control signal TP is input to the first terminal of the first n-channel transistor 201a, and the inverted timing control signal TPB is input to the first terminal of the first p-channel transistor 201b. An input signal IN2 is input to gate electrodes of the first n-channel transistor 201a and the first p-channel transistor 201b.

  The relationship between the input signal IN2, the timing control signal TP, and the inverted timing control signal TPB is as shown in the timing chart of FIG.

  In the first n-channel transistor 201a to which the timing control signal TP is input and the first p-channel transistor 201b to which the inverted timing control signal TPB is input, the potential of “Lo” is input to the input terminal by the input signal IN2. Then, the first p-channel transistor 201b is turned on. The output terminals of the first n-channel transistor 201a and the first p-channel transistor 201b become the potential of the inversion timing control signal TPB. That is, the output OUT2B has a “Hi” potential. At this time, the second n-channel transistor 202a and the second p-channel transistor 202b are turned off by the timing control signal TP and the inverted timing control signal TPB input to the first terminals.

  Next, when the input signal IN2 has a potential of “Hi”, the first n-channel transistor 201a and the first p-channel transistor 201b are turned off by the timing control signal TP and the inverted timing control signal TPB. Change.

  The gate electrodes of the second n-channel transistor 202a and the second p-channel transistor 202b are connected to the output OUT2B of the second terminal of the first n-channel transistor 201a and the first p-channel transistor 201b as an inverter. It is input via INV. In other words, the gate electrode of the second n-channel transistor 202a and the second p-channel transistor 202b is connected to the output OUT2B of the second terminal of the first n-channel transistor 201a and the first p-channel transistor 201b. A signal with the polarity reversed is input. With this signal, the timing control signal TP, and the inverted timing control signal TPB, the second p-channel transistor 202b is turned on. Thus, the output OUT2B of the second terminals of the second n-channel transistor 202a and the second p-channel transistor 202b becomes the potential “Hi” that is the potential of the timing control signal TP.

  Next, the first n-channel transistor 201a is turned on by the timing control signal TP and the inverted timing control signal TPB. Thus, the output OUT2B of the second terminals of the first n-channel transistor 201a and the first p-channel transistor 201b becomes the potential of the timing control signal TP and becomes the potential of “Lo”. At this time, the second n-channel transistor 202a and the second p-channel transistor 202b control the timing input to the first terminals of the second n-channel transistor 202a and the second p-channel transistor 202b. The signal TP and the inversion timing control signal TPB are in an off state.

  Next, when the start pulse SP becomes “Lo”, the first n-channel transistor 201a and the first p-channel transistor 201b are turned off by the timing control signal TP and the inverted timing control signal TPB. .

  The gate electrodes of the second n-channel transistor 202a and the second p-channel transistor 202b are connected to the output OUT2B of the second terminal of the first n-channel transistor 201a and the first p-channel transistor 201b as an inverter. It is input via INV. In other words, the gate electrode of the second n-channel transistor 202a and the second p-channel transistor 202b is connected to the output OUT2B of the second terminal of the first n-channel transistor 201a and the first p-channel transistor 201b. A signal with the polarity reversed is input. With this signal, the timing control signal TP, and the inverted timing control signal TPB, the second n-channel transistor 202a is turned on. Thus, the output OUT2B of the second terminals of the second n-channel transistor 202a and the second p-channel transistor 202b becomes the potential “Lo” that is the potential of the inversion timing control signal TPB.

  As described above, the outputs of the second terminals of the first n-channel transistor 201a and the second p-channel transistor 201b and the outputs of the second terminals of the n-channel transistor 202a and the p-channel transistor 202b change. To do. In this way, the output OUT2 outputs the input signal IN when the timing control signal TP is “Lo”, and holds the signal output until then when the timing control signal TP is “Hi”. Thus, the semiconductor circuit shown in FIG. 1A outputs a pulse.

  Note that this embodiment mode can be freely combined with any description in the embodiment examples in this specification.

  Examples of the present invention will be described below.

  FIG. 2A is a circuit intended to use the semiconductor circuit of the present invention as a shift register circuit. Here, the input signal IN is used as the start pulse SP, the timing control signal TP is used as the clock signal CK, and the inverted timing control signal TPB is used as the inverted clock signal CKB. The output is SR.

  FIG. 2B shows a timing chart of FIG. The description of the operation of the timing chart of FIG. 2B is omitted because it is shown in the first embodiment.

  FIG. 3A shows a 4-stage configuration of the shift register circuit of FIG. FIG. 3B shows a timing chart thereof. The shift register first stage output SR1, the shift register second stage output SR2, the shift register third stage output SR3, and the shift register fourth stage output SR4.

  In FIG. 3A, when a plurality of stages of shift register circuits are formed, the first n-channel transistor, the first p-channel transistor, the second n-channel transistor, and the second p-channel transistor are arranged. The clock signal and the inverted clock signal input to the first terminal are switched for each stage. As a result, the timing at which the previous stage input signal is captured and held is shifted by half a pulse of the clock signal CK and the inverted clock signal CKB as shown in FIG.

  FIG. 4A shows a diagram designed as a shift register. Moreover, the calculation result of the waveform is shown in FIG. The channel length and channel width of the transistors were set to 3.5 μm channel length and 10 μm channel width for both n-channel and p-channel transistors. The capacitance value was 10 fF. As operating conditions, the amplitudes of the input signal IN2, the clock signal CK, and the inverted clock signal CKB were L level = 0V, H level = 5V, and the power supply voltage of the circuit was Vdd = 5V and Vss = 0V. The driving frequency was 5 MHz. 4B, (1) shows the start pulse SP, (2) shows the clock signal CK, (3) shows the shift register first stage output SR1, and (4) shows the shift register second stage. The output SR2 is shown, (5) shows the shift register third stage output SR3, and (6) shows the shift register fourth stage output SR4. The transistor size, the capacitance value, and the operating conditions are attached because they are necessary for calculating the waveform, and are not limited to these values.

  Here, the calculation result of the waveform of FIG. 4B is the same as the output of the shift register first stage output SR1 when the same start pulse SP, clock signal CK, and inverted clock signal CKB are input as compared with FIG. 4B of FIG. 4B and SR1 of FIG. 3B coincide, and SR2 of FIG. 4B and FIG. 3B, which is the output of the shift register second stage output SR2. (5) in FIG. 4B, which is the output of the shift register third stage output SR3, and SR3 in FIG. 3 (b) match, and FIG. 4 (4) which is the output of the shift register fourth stage output SR4. b) (6) and SR4 in FIG. That is, the same operation as that of the conventional semiconductor circuit can be achieved by the circuit of the present invention in which the number of transistors is reduced. Therefore, the layout area can be reduced by reducing the number of transistors. In addition, variation in performance can be suppressed when a transistor is manufactured, so that yield can be improved.

  This embodiment can be implemented freely combining with any description in the above embodiment mode and other embodiments.

  FIG. 5A is a circuit intended to use the semiconductor circuit of the present invention as a latch circuit. Here, the input signal IN is used as the data signal DATA, the timing control signal TP is used as the sampling pulse LSP, and the inverted timing control signal TPB is used as the inverted sampling pulse LSPB. The output is D_OUT.

  5B, 5C, 5D, and 5E show timing charts of FIG. The initial state of the output D_OUT is “Lo”. The operation of the timing charts of FIGS. 5B, 5C, 5D, and 5E is described when the sampling pulse LSP is “Lo” as shown in the first embodiment. DATA is taken in, and when the sampling pulse LSP is “Hi”, the output until then is held. In any timing chart, it can be seen that the data signal DATA immediately before the sampling pulse LSP switches from “Lo” to “Hi” is kept.

  FIG. 6A shows a diagram actually designed as a latch circuit. The calculation results of the waveforms are shown in FIGS. 6B, 6C, 6D, and 6E. The channel length and channel width of the transistors were set to 3.5 μm channel length and 10 μm channel width for both n-channel and p-channel transistors. The capacitance value was 10 fF. As operating conditions, the amplitudes of the data signal DATA, the sampling pulse LSP, and the inverted sampling pulse LSPB were L level = 0V, H level = 5V, and the power supply voltage of the circuit was Vdd = 5V and Vss = 0V. 6B, 6C, 6D, and 6E, (1) indicates the data signal DATA, (2) indicates the sampling pulse LSP, and (3) indicates the output D_OUT. The transistor size, the capacitance value, and the operating conditions are attached because they are necessary for calculating the waveform, and are not limited to these values.

  Here, the calculation results of the waveforms in FIGS. 6B, 6C, 6D, and 6E are the same data signals as compared with FIGS. 5B, 5C, 5D, and 5E. DATA, a sampling pulse LSP, and an inverted sampling pulse LSPB are input, and coincide with D_OUT of FIG. 6B and FIG. 5B, which are outputs of the latch circuit, and (3) of FIG. ) And D_OUT in FIG. 5C, and in FIG. 6D, (3) and D_OUT in FIG. 5D, and in FIG. 6E, (3) and FIG. 5E. Matches D_OUT. That is, the same operation as that of the conventional semiconductor circuit can be achieved by the circuit of the present invention in which the number of transistors is reduced. Therefore, the layout area can be reduced by reducing the number of transistors. In addition, variation in performance can be suppressed when a transistor is manufactured, so that yield can be improved.

  This embodiment can be implemented freely combining with any description in the above embodiment modes and embodiments.

  FIG. 7 is an example in which the entire active matrix display device is shown in a block diagram. A source driver 302, a write gate driver 303, and an erase gate driver 304 are arranged around the pixel portion 301.

  The source driver 302 includes a shift register 305, a NAND circuit 306, a first latch circuit 307, a second latch circuit 308, and a level shifter buffer 309. The write gate driver 303 includes a shift register 310, a NAND circuit 311, and a level shifter buffer 312, and the erase gate driver 304 similarly includes a shift register 313, a NAND circuit 314, and a level shifter buffer 315. Yes.

  In the source driver 302, the shift register 305 sequentially outputs pulses from the first stage according to the source clock signal SCK, the inverted source clock signal SCKB, and the source start pulse SSP. An adjacent portion of pulses output from the shift register is extracted by the NAND circuit 306 and output as a sampling pulse LSP. In accordance with the sampling pulse LSP, the first latch circuit 307 samples the data signal DATA. In the stage where the capture is completed, the data is held in the memory portion provided in the first latch circuit 307 until the sampling in the final stage is completed. Eventually, after the sampling pulse output at the final stage is completed and sampling is completed at all stages of the first latch circuit 307, 1 held in the first latch circuit 307 according to the latch pulse LAT and the inverted latch pulse LATB. The data for the row is transferred to the second latch circuit 308 all at once. Thereafter, amplitude conversion is performed in the level shifter buffer 309 as necessary, and the source signal line is charged / discharged according to the video signal.

  Here, FIG. 8 illustrates a detailed connection example of the shift register 305, the NAND circuit 306, the first latch circuit 307, and the second latch circuit 308 of the source driver 302 in FIG.

  FIG. 8 shows a semiconductor circuit using the semiconductor circuit according to the first and second embodiments of the present invention for the shift register circuit, the first latch circuit, and the second latch circuit.

  FIG. 9 shows a timing chart of the semiconductor circuit of FIG. Here, the source start pulse SSP, the source clock signal SCK, and the inverted source clock signal SCKB are input to the shift register. Further, a shift register first stage output SSR1, a shift register second stage output SSR2, a shift register third stage output SSR3, a shift register fourth stage output SSR4, and a shift register last stage output SSRE + 1 are used.

  Here, the NAND circuit receives a signal sequentially output from two adjacent shift registers and outputs a sampling pulse LSP. Since the sampling pulse LSP output from each NAND circuit is a different signal, LSP1 and LSP2 are numbered sequentially from the left of the NAND circuit. Only the NAND circuit using the output SSRE + 1 of the final stage of the shift register as one of the inputs is set as LSPE.

  Next, in the first latch circuit, the data signal DATA is input from the outside, and the sampling pulses LSP1 to LSPE are input to each stage from the NAND circuit. In addition, signals obtained by inverting the polarities of the signals from the sampling pulses LSP1 to LSPE are input to each stage of the first latch circuit. The signal output from the first latch circuit is the output D_OUT1 if the input sampling pulse LSP is LSP1, and the output D_OUT2 if the input sampling pulse LSP is LSP2. The output of the latch circuit to which LSPE is input is D_OUTE.

  Finally, in the second latch circuit, the latch signal LAT and the inverted latch signal LATB are input from the outside over all stages. Further, the outputs D_OUT1 to D_OUTE of the first latch circuit are input to each stage. The output of each stage of the second latch circuit is output LOUT1 if the signal input from the first latch circuit is D_OUT1, and is output LOUT2 if the signal input from the first latch circuit is D_OUT2. The output of the latch circuit to which D_OUTE is input is LOUTE.

  Here, among the signals input from the outside, the data signal DATA may have an arbitrary signal waveform. The latch signal LAT and the inverted latch signal LATB are preferably signals such that the second latch circuit performs the capturing operation after the LSPE input to the first latch circuit. The latch signal LAT can be generated internally without being taken in from the outside. In this case, an extra shift register may be provided, and a signal output therefrom may be used as a latch signal.

  Further, the next time that the signal is input to the source start pulse SSP must be after the output of the second latch circuit is output, the source start pulse SP is input after the latch signal LAT is fetched.

  The description of the operation of the timing chart of FIG. 9 has already been described in the first and second embodiments, and is omitted here. If necessary, the description in the first and second embodiments is referred to. The operation of the NAND circuit is the same as that of a known NAND circuit, and thus will not be described here.

  The source driver circuit shown in this embodiment is shown as an example, and the present invention is not limited to this.

  This embodiment can be implemented by being freely combined with any description of the above embodiment modes and embodiments.

  Hereinafter, an example in which an N-channel transistor and a P-channel transistor included in a semiconductor circuit of the present invention are formed using a thin film transistor over a substrate having an insulating surface will be briefly described with reference to FIGS. The active matrix display device having the configuration shown in FIGS. 10 to 15 can realize a display device using a liquid crystal display device or an EL (Electro Luminescence) element.

First, as shown in FIG. 10A, a silicon oxide film and silicon nitride are formed on a glass substrate 401 such as barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass. A blocking layer 402 made of an insulating film such as a film or a silicon oxynitride film is formed. For example, a silicon oxynitride film formed from SiH ₄ , NH ₃ , and N ₂ O by plasma CVD is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm), and similarly oxidized from SiH ₄ and N ₂ O. A silicon hydride film is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm). Although the blocking layer 402 is shown as a two-layer structure in this embodiment, it may be formed as a single layer film of the insulating film or a structure in which two or more layers are stacked.

  The semiconductor layers 403 to 406 divided into islands are formed by converting a semiconductor film having an amorphous structure into a semiconductor film having a crystal structure by a heat treatment using a laser annealing method or a furnace annealing furnace (hereinafter referred to as a crystalline semiconductor film). Form with. The island-shaped semiconductor layers 403 to 406 are formed to have a thickness of 25 to 80 nm (preferably 30 to 60 nm). There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to manufacture a crystalline semiconductor film by a laser annealing method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO ₄ laser is used. Laser light output from the laser oscillator is collected in a linear form by an optical system and irradiated onto the semiconductor film. The conditions for annealing are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz and the laser energy density is 100 to 400 mJ / cm ² (typically 200 to 300 mJ / cm ² ). And In the case of using a YAG laser, the second harmonic is used, the pulse oscillation frequency is set to 1 to 10 kHz, and the laser energy density is set to 300 to 600 mJ / cm ² (typically 350 to 500 mJ / cm ² ). Then, laser light condensed linearly with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear laser light at this time is 80 to 98%.

  Next, a gate insulating film 407 is formed to cover the island-shaped semiconductor layers 403 to 406. The gate insulating film 407 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 nm. Needless to say, the gate insulating film 407 is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

  Then, a first conductive film 408 a and a second conductive film 408 b for forming a gate electrode are formed over the gate insulating film 407. In this embodiment, the first conductive film 408a is formed with tantalum nitride or titanium to a thickness of 50 to 100 nm, and the second conductive film 408b is formed with tungsten to a thickness of 100 to 300 nm. These materials are stable even in heat treatment at 400 to 600 ° C. in a nitrogen atmosphere, and the resistivity does not increase remarkably.

Next, as shown in FIG. 10B, a resist mask 409 is formed, and a first etching process for forming a gate electrode is performed. There is no limitation on the etching method, but an ICP (Inductively Coupled Plasma) etching method is preferably used. CF ₄ and Cl ₂ are mixed in an etching gas, and 500 W of RF (13.56 MHz) power is supplied to the coil electrode at a pressure of 0.5 to ₂ Pa, preferably 1 Pa, to generate plasma. 100 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, etching can be performed at a similar rate even in the case of a tungsten film, a tantalum nitride film, and a titanium film.

  Under the above etching conditions, the end portion can be tapered by the shape of the resist mask and the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is set to 25 to 45 degrees. In order to etch without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%. Since the selection ratio of the silicon oxynitride film to tungsten is 2 to 4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the over-etching process. Thus, the first shape conductive layers 410 to 415 (the first conductive films 410a to 415a and the second conductive films 410b to 415b) formed of the first conductive film and the second conductive film by the first etching treatment. Form. Reference numeral 416 denotes a gate insulating film, and a region not covered with the first shape conductive layer is etched and thinned by about 20 to 50 nm.

Then, as shown in FIG. 10C, a first doping process is performed to dope n-type impurities (donors). Doping is performed by ion doping or ion implantation. The ion doping method is performed at a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁴ / cm ² . As the impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. In this case, the acceleration voltage is controlled (for example, 20 to 60 keV), and the first shape conductive layer is used as a mask. Thus, first impurity regions 417 to 420 are formed. For example, the n-type impurity concentration in the first impurity regions 417 to 420 is formed in the range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

In the second etching process shown in FIG. 11A, similarly, an ICP etching apparatus is used, and CF ₄ , Cl _2, and O ₂ are mixed in an etching gas, and RF of 500 W is applied to a coil-type electrode at a pressure of 1 Pa. Electric power (13.56 MHz) is supplied to generate plasma. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. Under such conditions, the tungsten film is anisotropically etched to leave the tantalum nitride film or titanium film as the first conductive layer. Thus, second shape conductive layers 421 to 426 (first conductive films 421a to 426a and second conductive films 421b to 426b) are formed. The region of the gate insulating film that is not covered with the second shape conductive layers 421 to 426 is further etched by about 20 to 50 nm to be thinned.

Next, a second doping process is performed. The n-type impurity (donor) is doped under a condition of a high acceleration voltage with a lower dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 keV and the dose is 1 × 10 ¹³ / cm ² , and the second impurity is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. Regions 427 to 430 are formed. In this doping, the second conductive films 423b to 426b are used as masks against the impurity elements, and doping is performed so that the impurity elements are added to regions below the first conductive films 423a to 426a. In this impurity region, since the first conductive layers 423a to 426a remain with substantially the same film thickness, the difference in concentration distribution in the direction along the second shape conductive layer is small, and 1 × 10 ¹⁷ to An n-type impurity (donor) is included at a concentration of 1 × 10 ¹⁹ / cm ³ .

  Then, as shown in FIG. 11B, a third etching process is performed, and an etching process for the gate insulating film is performed. As a result, the second conductive films 421a to 426a are also etched, the end portions thereof are recessed and become smaller, and the third shape conductive layers 431 to 436 (the first conductive films 431a to 436a and the second conductive film 431b). ~ 436b) are formed. Reference numeral 437 denotes a remaining gate insulating film, which may be further etched to expose the surface of the semiconductor layer.

For p-channel TFTs, resist masks 438 and 439 are formed as shown in FIG. 11C, and p-type impurities (acceptors) are doped in the island-shaped semiconductor layers forming the p-channel TFTs. To do. The p-type impurity (acceptor) is selected from elements belonging to Group 13, and typically boron (B) is used. The impurity concentration of the third impurity regions 440a to 440c is set to 2 × 10 ²⁰ to 2 × 10 ²¹ / cm ³ . Although phosphorus is added to the third impurity region, boron is added at a concentration higher than that to reverse the conductivity type.

  Through the above steps, impurity regions are formed in the semiconductor layer. In FIG. 11, the third shape conductive layers 433 to 435 serve as gate electrodes, and the third shape conductive layer 436 serves as a capacitor wiring. The third shape conductive layers 431 and 432 form wirings such as source lines.

Next, in FIG. 12A, first, a first insulating film 441 made of a silicon nitride film (SiN: H) or a silicon oxynitride film (SiN _x O _y : H) is formed by a plasma CVD method. Then, a step of activating the impurity element added to each island-like semiconductor layer is performed for the purpose of controlling the conductivity type. Activation is preferably performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can also be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less in a nitrogen atmosphere at 400 to 700 ° C., typically 500 to 600 ° C. In this example, the temperature is 550 ° C. for 4 hours. Heat treatment is performed.

After that, a second insulating film 442 made of a silicon nitride film (SiN: H) or a silicon oxynitride film (SiN _x O _y : H) is formed over the first insulating film 441. And heat processing is performed at 350-500 degreeC. The semiconductor film is hydrogenated with hydrogen released from the second insulating film 442.

  Further, as shown in FIG. 12B, a third insulating film 443 made of an organic resin is formed to a thickness of about 1000 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Organic resin films other than those described above can also be used. Here, after applying to the substrate, a thermal polymerization type polyimide is used and baked at 300 ° C.

  Next, contact holes are formed in the third insulating film 443, the second insulating film 442, and the first insulating film 441, and aluminum (Al), titanium (Ti), tantalum (Ta), or the like is used. Connection electrodes 451 and source or drain wirings 444 to 447 are formed. In the pixel portion, a first pixel electrode 450, a gate wiring 449, and a connection electrode 448 are formed.

  Thus, a p-channel TFT 453 and an n-channel TFT 454 are formed on the same substrate. In FIG. 12B, only a cross-sectional view of the p-channel TFT 453 and the n-channel TFT 454 is shown; however, using these TFTs, a gate signal line driver circuit and a source signal line driver each including the semiconductor circuit of the present invention are used. The circuit can be formed integrally on the same substrate.

  The structure of the thin film transistor described in this embodiment is merely an embodiment, and is not necessarily limited to the manufacturing process and structure illustrated in FIGS. The semiconductor circuit of the present invention can be integrally formed over the same substrate by a known thin film transistor manufacturing method. Such a circuit can be formed at low cost over a substrate having a large area such as a glass substrate by being formed using a thin film transistor, so that the display device can have a large area and a low cost. Furthermore, the gate signal line driver circuit and the source signal line driver circuit including the semiconductor circuit of the present invention can greatly reduce the number of transistors, so that the layout area of the driver circuit portion around the pixel portion can be reduced. In addition, a product with a high yield can be manufactured.

  This embodiment can be implemented by being freely combined with any description of the above embodiment modes and embodiments.

  In this embodiment, a process for manufacturing an active matrix liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 13, interlayer films 461 and 462 are formed on the substrate in the state of FIG. 12B, a second pixel electrode 463 is formed thereon, and an alignment film 551 is formed thereon. In this embodiment, a polyimide film is used as the alignment film. A transparent conductive film 553 and an alignment film 554 are formed over the counter substrate 552. Note that a color filter or a shielding film may be formed on the counter substrate as necessary.

  Next, after forming an alignment film, a rubbing process is performed to adjust the liquid crystal molecules so that they are aligned with a certain pretilt angle. Then, the active matrix substrate on which the pixel portion, the drive circuit is formed, and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown), and the like by a known cell assembling process.

  Thereafter, liquid crystal 555 is injected between both substrates and completely sealed with a sealing material (not shown). A known liquid crystal material may be used for the liquid crystal. Thus, the active matrix type liquid crystal display device shown in FIG. 5 is completed.

  Next, the configuration of the active matrix liquid crystal display device will be described with reference to the perspective view of FIG. The active matrix substrate includes a pixel portion 602, a gate side driver circuit 603, and a source side driver circuit 604 that are formed over a glass substrate 601. A pixel TFT 605 in the pixel portion is an n-channel TFT and is connected to the pixel electrode 606 and the storage capacitor 607.

  The drive circuit provided in the periphery is configured based on the semiconductor circuit of the present invention. The gate side driver circuit 603 and the source side driver circuit 604 are connected to the pixel portion 602 through a gate wiring 608 and a source wiring 609, respectively. The external input / output terminal 611 to which the FPC 610 is connected is provided with input / output wirings (connection wirings) 612 and 613 for transmitting signals to the driving circuit. Reference numeral 614 denotes a counter substrate.

  The configuration of the active matrix liquid crystal display device described in this embodiment is merely an embodiment, and is not necessarily limited to the structure shown in FIGS. By a known method for manufacturing an active matrix liquid crystal display device, the semiconductor circuit of the present invention can be mounted on a driver circuit portion of the active matrix liquid crystal display device. The active matrix liquid crystal display device including the semiconductor circuit of the present invention can be formed at low cost on a substrate having a large area such as a glass substrate by being composed of thin film transistors, so that the display device has a large area and a low cost. Is possible. Further, the gate signal line driver circuit and the source signal line driver circuit including the semiconductor circuit of the present invention can greatly reduce the number of transistors, so that power consumption is reduced and the layout of the driver circuit portion around the pixel portion is reduced. By reducing the area, a frame can be formed and a product with a high yield can be manufactured.

  In this specification, the semiconductor device shown in FIG. 13 is called an active matrix liquid crystal display device, but a liquid crystal panel attached up to an FPC as shown in FIG. 14 is generally called a liquid crystal module. . Therefore, the active matrix liquid crystal display device in this embodiment may be called a liquid crystal module.

  This embodiment can be implemented by being freely combined with any description of the above embodiment modes and embodiments.

  In this example, the appearance of a panel corresponding to one mode of a light-emitting device including a semiconductor circuit of the present invention will be described with reference to FIGS. FIG. 15A is a top view of a panel in which a transistor and a light-emitting element formed over a first substrate are sealed with a sealant between the second substrate and FIG. 15B. FIG. 15A corresponds to a cross-sectional view taken along line AA ′ of FIG.

  A sealant 4020 is provided so as to surround the pixel portion 4002, the signal line driver circuit 4003, the first scan line driver circuit 4004, and the second scan line driver circuit 4005 provided over the first substrate 4001. It has been. In addition, a second substrate 4006 is provided over the pixel portion 4002, the signal line driver circuit 4003, the first scan line driver circuit 4004, and the second scan line driver circuit 4005. Therefore, the pixel portion 4002, the signal line driver circuit 4003, the first scan line driver circuit 4004, and the second scan line driver circuit 4005 include the first substrate 4001, the sealant 4020, and the second substrate 4006. Is sealed together with the filler 4007.

  Further, the pixel portion 4002, the signal line driver circuit 4003, the first scan line driver circuit 4004, and the second scan line driver circuit 4005 provided over the first substrate 4001 each include a plurality of transistors. FIG. 15B illustrates a transistor 4008 included in the signal line driver circuit 4003, and a driving transistor 4009 and a switching transistor 4010 included in the pixel portion 4002.

  Reference numeral 4011 corresponds to a light-emitting element, and a part of the wiring 4017 connected to the drain of the driving transistor 4009 functions as a first electrode of the light-emitting element 4011. The transparent conductive film functions as the second electrode 4012 of the light-emitting element 4011. Note that the structure of the light-emitting element 4011 is not limited to the structure shown in this embodiment. The structure of the light-emitting element 4011 can be changed as appropriate depending on the direction of light extracted from the light-emitting element 4011, the polarity of the driving transistor 4009, or the like.

  Further, various signals and voltages supplied to the signal line driver circuit 4003, the first scan line driver circuit 4004, the second scan line driver circuit 4005, or the pixel portion 4002 are not illustrated in the cross-sectional view in FIG. Although not provided, it is supplied from the connection terminal 4016 via the lead wirings 4014 and 4015.

  In this embodiment, the connection terminal 4016 is formed using the same conductive film as the second electrode 4012 included in the light-emitting element 4011. The lead wiring 4014 is formed from the same conductive film as the wiring 4017. The lead wiring 4015 is formed of the same conductive film as the gates of the driving transistor 4009, the switching transistor 4010, and the transistor 4008.

  The connection terminal 4016 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive film 4019.

  Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.

  Note that the second substrate 4006 located in the direction in which light is extracted from the light-emitting element 4011 must have a light-transmitting property. Therefore, the second substrate 4006 is formed using a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film.

  As the filler 4007, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicon resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.

  The drive circuit provided in the periphery is configured based on the semiconductor circuit of the present invention. The first scan line driver circuit 4004, the second scan line driver circuit 4005, and the signal line driver circuit 4003 are connected to the pixel portion through gate lines and source lines, respectively.

  This embodiment can be implemented in combination with the above embodiment mode and the above embodiments.

  The structure of the light-emitting device described in this embodiment is just an example, and is not necessarily limited to the structure illustrated in FIG. The semiconductor circuit of the present invention can be mounted on a driver circuit portion of a light emitting device by a known method for manufacturing a light emitting device. A light-emitting device including the semiconductor circuit of the present invention can be formed on a substrate having a large area such as a glass substrate by using a thin film transistor, so that the display device can have a large area and a low cost. . Further, the gate signal line driver circuit and the source signal line driver circuit including the semiconductor circuit of the present invention can greatly reduce the number of transistors, so that power consumption is reduced and the layout of the driver circuit portion around the pixel portion is reduced. By reducing the area, a frame can be formed and a product with a high yield can be manufactured.

  Note that in this specification, the semiconductor device illustrated in FIG. 15 is referred to as an active matrix light-emitting device, but in this specification, a panel using an EL element attached to an FPC as illustrated in FIG. It is called EL module.

  This embodiment can be implemented by being freely combined with any description of the above embodiment modes and embodiments.

  Hereinafter, an example in which an N-channel transistor and a P-channel transistor included in the semiconductor circuit of the present invention are formed over a single crystal substrate is described. A manufacturing procedure will be briefly described with reference to FIGS.

  First, a silicon substrate 1901 made of single crystal silicon is prepared. Then, an n-type well 1902 and a p-type well 1903 are selectively formed in the first element formation region of the main surface (element formation surface or circuit formation surface) of the silicon substrate, respectively.

  Next, a field oxide film 1904 serving as an element isolation region for partitioning the first element formation region and the second element formation region is formed. The field oxide film 1904 is a thick thermal oxide film and may be formed using a known LOCOS method. The element isolation method is not limited to the LOCOS method. For example, the element isolation region may have a trench structure using the trench isolation method, or may be a combination of the LOCOS structure and the trench structure.

  Next, a gate insulating film is formed by thermally oxidizing the surface of the silicon substrate, for example. The gate insulating film may be formed by a CVD method, and a silicon oxynitride film, a silicon oxide film, a silicon nitride film, or a stacked film thereof can be used. For example, a stacked film of a silicon oxide film having a thickness of 5 nm obtained by thermal oxidation and a silicon oxynitride film having a thickness of 10 nm to 15 nm obtained by a CVD method is formed.

Next, a stacked film of polysilicon layers 1905b and 1906b and silicide layers 1905a and 1906a is formed on the entire surface, and a stacked film is formed based on a lithography technique and a dry etching technique, thereby forming a gate electrode having a polycide structure on the gate insulating film. 1905 and 1906 are formed. The polysilicon layers 1905b and 1906b may be doped in advance with phosphorus (P) at a concentration of about 10 ²¹ / cm ³ in order to reduce the resistance, or after the formation of the polysilicon film, a deep n-type impurity May be diffused. The silicide layers 1905a and 1906a can be made of molybdenum silicide (MoSix), tungsten silicide (WSix), tantalum silicide (TaSix), titanium silicide (TiSix), or the like. Just do it.

  Next, in order to form an extension region, ion implantation is performed on the silicon semiconductor substrate through the gate insulating film. In this embodiment, the impurity region formed between each source region and drain region and the channel formation region is called an extension region. The impurity concentration of the extension regions 1907 and 1908 may be lower than the impurity concentration of the source region and the drain region, may be equal, or may be higher. That is, the impurity concentration in the extension region may be determined based on characteristics required for the semiconductor device.

  Since this embodiment is a case of manufacturing a CMOS circuit applied to the present invention, the first element formation region in which the p-channel FET is to be formed is covered with a resist material, and arsenic (As ) Or phosphorus (P) is implanted into the silicon substrate. Further, the second element formation region in which the n-channel FET is to be formed is covered with a resist material, and boron (B) that is a p-type impurity is implanted into the silicon substrate.

  Next, a first activation process is performed in order to activate the ion-implanted impurities and recover crystal defects in the silicon substrate generated by the ion implantation. The semiconductor substrate is heated to a temperature about the melting point of Si and activated.

  Next, sidewalls 1909 and 1910 are formed on the sidewalls of the gate electrode. For example, an insulating material layer made of silicon oxide may be made to have a volume by a CVD method over the entire surface, and the insulating material layer may be etched back to form a sidewall. The gate insulating film may be selectively removed in a self-aligned manner during the etch back. Further, the gate insulating film may be etched after the etch back. Thus, gate insulating films 1911 and 1912 having a total width of the width of the gate electrode and the widths of the sidewalls provided on both sides of the side wall of the gate electrode are formed.

  Next, ion implantation is performed on the exposed silicon substrate to form a source region and a drain region. A first element formation region in which a p-channel FET is to be formed is covered with a resist material, and n-type impurities such as arsenic (As) and phosphorus (P) are implanted into the silicon substrate to form a source region 1913 and a drain region 1914. Form. Further, a second element formation region in which an n-channel FET is to be formed is covered with a resist material, and boron (B) which is a p-type impurity is implanted into the silicon substrate to form a source region 1915 and a drain region 1916.

  Next, a second activation process is performed in order to activate the ion-implanted impurities and recover crystal defects in the silicon substrate generated by the ion implantation.

  Then, after activation, an interlayer insulating film, a plug electrode, a metal wiring, and the like are formed. The first interlayer insulating film 1917 is formed to a thickness of 100 to 2000 nm using a silicon oxide film, a silicon oxynitride film, or the like by using a plasma CVD method or a low pressure CVD method. Further, a second interlayer insulating film 1918 made of phosphorus glass (PSG), boron glass (BSG), or phosphorus boron glass (PBSG) is formed thereon. The second interlayer insulating film 1918 is manufactured by spin coating or atmospheric pressure CVD in order to improve flatness.

  The source electrodes 1919 and 1921 and the drain electrodes 1920 and 1922 are formed after forming contact holes reaching the source and drain regions of the respective FETs in the first interlayer insulating film 1917 and the second interlayer insulating film 1918. Therefore, it is preferable to use aluminum (Al) which is usually used as a low resistance material. Alternatively, a stacked structure of Al and titanium (Ti) may be used.

  Although not shown here, a contact hole reaching the gate electrode is provided in the first interlayer insulating film 1917 and the second interlayer insulating film 1918, and a wiring provided on the first interlayer insulating film and An electrically connected electrode is formed.

  Finally, a passivation film 1923 and a third interlayer insulating film 1924 are formed. In FIG. 16, the left side is a p-channel transistor 1925 and the right side is an n-channel transistor 1926.

  The passivation film 1923 is formed of a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film by a plasma CVD method. Further, the third interlayer insulating film 1924 is formed of an organic resin material with a thickness of 1 μm to 2 μm. As the organic resin material, polyimide, polyamide, acrylic, benzocyclobutene (BCB), or the like can be used. Advantages of using the organic resin film include that the film formation method is simple, that the parasitic capacitance can be reduced because the relative dielectric constant is low, and that it is suitable for planarization. Of course, organic resin films other than those described above may be used.

  In this manner, a p-channel transistor 1925 and an n-channel transistor 1926 are completed. The structure of the transistor described in this embodiment is just an embodiment and need not be limited to the manufacturing process and structure illustrated in FIGS. The semiconductor circuit of the present invention can be formed over a single crystal substrate by a known method for manufacturing a transistor over a single crystal substrate. Such a circuit can operate at high speed by being configured on a single crystal substrate, and can reduce power consumption by lowering a driving voltage. Furthermore, the gate signal line driver circuit and the source signal line driver circuit including the semiconductor circuit of the present invention can greatly reduce the number of transistors, so that the layout area of the driver circuit portion around the pixel portion can be reduced. In addition, a product with a high yield can be manufactured.

  As an electronic device including the semiconductor circuit of the present invention, a television receiver, a video camera, a digital camera, a goggle type display, a navigation system, a sound reproduction device (car audio component, etc.), a computer, a game device, a portable information terminal (mobile computer) A mobile phone, a portable game machine, an electronic book, etc.) and an image playback apparatus (specifically, a digital versatile disc (DVD)) provided with a recording medium, and a display capable of displaying the image. Device). Specific examples of those electronic devices are shown in FIGS. 17, 18, 19A to 19B, 20A to 20B, 21, 22A to 22 (). E).

  FIG. 17 shows a liquid crystal module in which a display panel 5001 and a circuit board 5011 are combined. A circuit board 5011 is provided with a control circuit 5012, a signal dividing circuit 5013, and the like, and is electrically connected to the display panel 5001 through a connection wiring 5014.

  The display panel 5001 includes a pixel portion 5002 provided with a plurality of pixels, a scanning line driver circuit 5003, and a signal line driver circuit 5004 for supplying a video signal to the selected pixel. Note that in the case of manufacturing a liquid crystal module, the display panel 5001 may be manufactured using the above embodiment. In addition, a control driver circuit portion such as the scan line driver circuit 5003 or the signal line driver circuit 5004 can be manufactured using the thin film transistor formed in the above embodiment or the transistor over a single crystal substrate. As described above, the liquid crystal module liquid crystal television shown in FIG. 17 can be completed.

  FIG. 18 is a block diagram showing the main configuration of a liquid crystal television receiver. A tuner 5101 receives a video signal and an audio signal. The video signal includes a video signal amplifying circuit 5102, a video signal processing circuit 5103 that converts a signal output from the video signal into a color signal corresponding to each color of red, green, and blue, and the video signal as input specifications of the driver IC. Processing is performed by a control circuit 5012 for conversion. The control circuit 5012 outputs a signal to each of the scanning line side and the signal line side. In the case of digital driving, a signal dividing circuit 5013 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied.

  Of the signals received by the tuner 5101, the audio signal is sent to the audio signal amplifier circuit 5105, and the output is supplied to the speaker 5107 through the audio signal processing circuit 5106. The control circuit 5108 receives control information on the receiving station (reception frequency) and volume from the input unit 5109 and sends a signal to the tuner 5101 and the audio signal processing circuit 5106.

  As shown in FIG. 19A, a television receiver can be completed by incorporating a liquid crystal module into a housing 5201. A display screen 5202 is formed by the liquid crystal module. In addition, a speaker 5203, an operation switch 5204, and the like are provided as appropriate.

  FIG. 19B shows a television receiver that can carry only a display wirelessly. A housing and a signal receiver are incorporated in the housing 5212, and the display portion 5213 and the speaker portion 5217 are driven by the battery. The battery can be repeatedly charged by a charger 5210. The charger 5210 can transmit and receive a video signal, and can transmit the video signal to a signal receiver of the display. The housing 5212 is controlled by operation keys 5216. The device illustrated in FIG. 19B can also be called a video / audio two-way communication device because a signal can be sent from the housing 5212 to the charger 5210 by operating the operation key 5216. In addition, by operating the operation key 5216, a signal is transmitted from the housing 5212 to the charger 5210, and further, a signal that can be transmitted by the charger 5210 is received by another electronic device, thereby controlling communication of the other electronic device. It can be said to be a general-purpose remote control device. The present invention can be applied to the scan line driver circuit 5003 and the signal line driver circuit 5004.

  The number of transistors in the gate signal line driver circuit and the source signal line driver circuit can be greatly reduced by using the television receiver shown in FIGS. 17, 18, 19A to 19B. Therefore, the layout area of the driver circuit portion around the pixel portion can be reduced, and a product with a high yield can be provided to the customer.

  Of course, the present invention is not limited to a television receiver, and is applied to various uses as a display medium of a particularly large area such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do.

  FIG. 20A shows a module in which a display panel 5301 and a printed wiring board 5302 are combined. The display panel 5301 includes a pixel portion 5303 provided with a plurality of pixels, a first scan line driver circuit 5304, a second scan line driver circuit 5305, and a signal line driver circuit that supplies a video signal to the selected pixel. 5306 is provided.

  The printed wiring board 5302 is provided with a controller 5307, a central processing unit (CPU) 5308, a memory 5309, a power supply circuit 5310, an audio processing circuit 5311, a transmission / reception circuit 5312, and the like. The printed wiring board 5302 and the display panel 5301 are connected by a flexible wiring board (FPC) 5313. The printed wiring board 5313 may be provided with a capacitor, a buffer circuit, or the like so that noise is added to the power supply voltage or the signal or the rise of the signal is not slowed. The controller 5307, the audio processing circuit 5311, the memory 5309, the CPU 5308, the power supply circuit 5310, and the like can be mounted on the display panel 5301 using a COG (Chip On Glass) method. The scale of the printed wiring board 5302 can be reduced by the COG method.

  Various control signals are input and output through an interface (I / F) unit 5314 provided in the printed wiring board 5302. An antenna port 5315 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 5302.

  FIG. 20B is a block diagram of the module shown in FIG. This module includes a VRAM 5316, a DRAM 5317, a flash memory 5318, and the like as the memory 5309. The VRAM 5316 stores image data to be displayed on the panel, the DRAM 5317 stores image data or audio data, and the flash memory stores various programs.

  The power supply circuit 5310 supplies power for operating the display panel 5301, the controller 5307, the CPU 5308, the sound processing circuit 5311, the memory 5309, and the transmission / reception circuit 5312. Depending on the specifications of the panel, the power supply circuit 5310 may be provided with a current source.

  The CPU 5308 includes a control signal generation circuit 5320, a decoder 5321, a register 5322, an arithmetic circuit 5323, a RAM 5324, an interface 5319 for the CPU 5308, and the like. Various signals input to the CPU 5308 through the interface 5319 are temporarily held in the register 5322 and then input to the arithmetic circuit 5323, the decoder 5321, and the like. The arithmetic circuit 5323 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 5321 is decoded and input to the control signal generation circuit 5320. The control signal generation circuit 5320 generates a signal including various instructions based on the input signal, and a location designated by the arithmetic circuit 5323, specifically, a memory 5309, a transmission / reception circuit 5312, an audio processing circuit 5311, a controller 5307, and the like. Send to.

  The memory 5309, the transmission / reception circuit 5312, the sound processing circuit 5311, and the controller 5307 operate according to the received commands. The operation will be briefly described below.

  A signal input from the input unit 5325 is sent to the CPU 5308 mounted on the printed wiring board 5302 via the I / F unit 5314. The control signal generation circuit 5320 converts the image data stored in the VRAM 5316 into a predetermined format according to a signal sent from the input unit 5325 such as a pointing device or a keyboard, and sends the image data to the controller 5307.

  The controller 5307 performs data processing on a signal including image data sent from the CPU 5308 in accordance with the specifications of the panel, and supplies the processed signal to the display panel 5301. Further, the controller 5307 generates an Hsync signal, a Vsync signal, a clock signal CLK, an AC voltage (AC Cont), and a switching signal L / R based on the power supply voltage input from the power supply circuit 5310 and various signals input from the CPU 5308. Generated and supplied to the display panel 5301.

  In the transmission / reception circuit 5312, signals transmitted / received as radio waves in the antenna 5328 are processed. Specifically, high-frequency signals such as an isolator, a band-pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun are used. Includes circuitry. A signal including audio information among signals transmitted and received in the transmission / reception circuit 5312 is sent to the audio processing circuit 5311 in accordance with a command from the CPU 5308.

  A signal including audio information sent in accordance with a command from the CPU 5308 is demodulated into an audio signal by the audio processing circuit 5311 and sent to the speaker 5327. An audio signal sent from the microphone 5326 is modulated in the audio processing circuit 5311 and sent to the transmission / reception circuit 5312 in accordance with a command from the CPU 5308.

  The controller 5307, the CPU 5308, the power supply circuit 5310, the sound processing circuit 5311, and the memory 5309 can be mounted as a package of this embodiment. This embodiment can be applied to any circuit other than a high-frequency circuit such as an isolator, a band pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun.

  FIG. 21 illustrates one mode of a mobile phone including the module illustrated in FIGS. 20 (A) to 20 (B). The display panel 5301 is incorporated in a housing 5330 so as to be detachable. The shape and size of the housing 5330 can be changed as appropriate in accordance with the size of the display panel 5301. The housing 5330 to which the display panel 5301 is fixed is fitted to the printed board 5331 and assembled as a module.

  The display panel 5301 is connected to the printed board 5331 through the FPC 5313. A signal processing circuit 5335 including a speaker 5332, a microphone 5333, a transmission / reception circuit 5334, a CPU, a controller, and the like is formed over the printed circuit board 5331. Such a module is combined with the input means 5336, the battery 5337, and the antenna 5340 and stored in the housing 5339. The pixel portion of the display panel 5301 is arranged so that it can be seen from an opening window formed in the housing 5339.

  The mobile phone according to the present embodiment can be transformed into various modes according to the function and application. For example, even if the display panel is provided with a plurality of display panels or the case is divided into a plurality of cases and opened and closed by a hinge, the number of transistors in the gate signal line driver circuit and the source signal line driver circuit in the display panel is greatly increased. Since it can be reduced, the layout area of the drive circuit portion around the pixel portion can be reduced, and a product with a high yield can be provided to the customer.

  By using the present invention in the mobile phone shown in FIGS. 20A to 20B and FIG. 21, the number of transistors in the gate signal line driver circuit and the source signal line driver circuit in the display panel can be greatly reduced. Therefore, the layout area of the driver circuit portion around the pixel portion can be reduced, and a product with a high yield can be provided to the customer.

  FIG. 22A illustrates a liquid crystal display which includes a housing 6001, a support base 6002, a display portion 6003, and the like. The invention can be applied to the driver circuit of the display portion 6003 by using the structure of the liquid crystal module shown in FIG. 13 and the display panel shown in FIG.

  By using the present invention, the number of transistors in the gate signal line driver circuit and the source signal line driver circuit of the display portion 6003 can be significantly reduced, so that the layout area of the driver circuit portion around the pixel portion can be reduced. This makes it possible to provide customers with high yield products.

  FIG. 22B illustrates a computer, which includes a main body 6101, a housing 6102, a display portion 6103, a keyboard 6104, an external connection port 6105, a pointing mouse 6106, and the like. The present invention can be applied to the display portion 6103 using the structure of the liquid crystal module shown in FIG. 13 and the display panel shown in FIG.

  By using the present invention, the number of transistors in the gate signal line driver circuit and the source signal line driver circuit of the display portion 6103 can be significantly reduced, so that the layout area of the driver circuit portion around the pixel portion can be reduced. This makes it possible to provide customers with high yield products.

  FIG. 22C illustrates a portable computer, which includes a main body 6201, a display portion 6202, a switch 6203, operation keys 6204, an infrared port 6205, and the like. The present invention can be applied to the display portion 6202 by using the liquid crystal module shown in FIG. 13 and the structure of the display panel shown in FIG.

  By using the present invention, the number of transistors in the gate signal line driver circuit and the source signal line driver circuit of the display portion 6202 can be significantly reduced, so that the layout area of the driver circuit portion around the pixel portion can be reduced. This makes it possible to provide customers with high yield products.

  FIG. 22D illustrates a portable game machine including a housing 6301, a display portion 6302, speaker portions 6303, operation keys 6304, a recording medium insertion portion 6305, and the like. The present invention can be applied to the display portion 6302 using the structure of the liquid crystal module shown in FIG. 13 and the display panel shown in FIG.

  By using the present invention, the number of transistors in the gate signal line driver circuit and the source signal line driver circuit of the display portion 6302 can be significantly reduced, so that the layout area of the driver circuit portion around the pixel portion can be reduced. This makes it possible to provide customers with high yield products.

  FIG. 22E shows a portable image playback device (specifically, a DVD playback device) provided with a recording medium, which includes a main body 6401, a housing 6402, a display portion A 6403, a display portion B 6404, and a recording medium (such as a DVD). A reading unit 6405, operation keys 6406, a speaker unit 6407, and the like are included. The display portion A 6403 mainly displays image information, and the display portion B 6404 mainly displays character information. The present invention can be applied to the display portion A 6403, the display portion B 6404, the control circuit portion, and the like using the structure of the liquid crystal module shown in FIG. 13 and the display panel shown in FIG. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

  By using the present invention, the number of transistors in the gate signal line driver circuit and the source signal line driver circuit in the display portion A 6403 and the display portion B 6404 can be significantly reduced, so that the layout area of the driver circuit portion in the periphery of the pixel portion can be reduced. It is possible to provide a customer with a product with a high yield.

  Display devices used in these electronic devices can use not only a glass substrate but also a heat-resistant plastic substrate depending on the size, strength, or purpose of use. As a result, the weight can be further reduced.

  It should be noted that the examples shown in this embodiment are just examples, and the present invention is not limited to these applications.

  This embodiment can be implemented by being freely combined with any description of the above embodiment modes and embodiments.

FIG. 2 is a circuit diagram and a timing chart showing the configuration of the first embodiment. FIG. 2 is a circuit diagram and a timing chart illustrating the configuration of the first embodiment. FIG. 2 is a circuit diagram and a timing chart illustrating the configuration of the first embodiment. FIG. 3 is a circuit diagram of a shift register according to the first embodiment and an output diagram of waveforms. FIG. 6 is a circuit diagram and a timing chart showing the configuration of Embodiment 2. The circuit diagram which shows the structure of Example 2, and the output diagram of a waveform. FIG. 9 is a block diagram of a third embodiment. FIG. 6 is a circuit diagram of Example 3. Timing chart of Example 3 FIG. 10 is a cross-sectional view of a manufacturing process of the transistor of Example 4; FIG. 10 is a cross-sectional view of a manufacturing process of the transistor of Example 4; FIG. 10 is a cross-sectional view of a manufacturing process of the transistor of Example 4; Sectional drawing of the liquid crystal module of Example 5. FIG. FIG. 10 is a perspective view of a liquid crystal module according to a fifth embodiment. The perspective view and sectional drawing of EL module of Example 6. FIG. 9 is a cross-sectional view of a transistor of Example 7. FIG. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. FIG. 11 illustrates an example of an electronic device to which the present invention is applied. The circuit diagram which shows the structure of a prior art example. The circuit diagram which shows the structure of a prior art example.

Explanation of symbols

201a n-channel transistor 201b p-channel transistor 202a n-channel transistor 202b p-channel transistor 203a n-channel transistor 203b p-channel transistor 301 pixel portion 302 source driver 303 writing gate driver 304 erasing gate driver 305 shift register 306 NAND circuit 307 Latch circuit 308 Latch circuit 309 Level shifter buffer 310 Shift register 311 NAND circuit 312 Level shifter buffer 313 Shift register 314 NAND circuit 315 Level shifter buffer 401 Glass substrate 402 Blocking layer 403 Semiconductor layer 404 Semiconductor layer 405 Semiconductor layer 406 Semiconductor Layer 407 gate insulating film 408a first conductive film 408b first Conductive film 409 mask 410 first shape conductive layer 410a first conductive film 410b second conductive film 411 first shape conductive layer 411a first conductive film 411b second conductive film 412 first shape Conductive layer 412a first conductive film 412b second conductive film 413 first shape conductive layer 413a first conductive film 413b second conductive film 414 first shape conductive layer 414a first conductive film 414b Second conductive film 415 first shape conductive layer 415a first conductive film 415b second conductive film 416 gate insulating film 417 first impurity region 418 first impurity region 419 first impurity region 420 first Impurity region 421 second-shaped conductive layer 421a first conductive film 421b second conductive film 422 second-shaped conductive layer 422a first conductive film 422b second conductive film 423 Second shape conductive layer 423a first conductive layer 423b second conductive layer 424 second shape conductive layer 424a first conductive film 424b second conductive film 425 second shape conductive layer 425a first Conductive film 425b second conductive film 426 second shape conductive layer 426b first conductive film 426a second conductive film 427 second impurity region 428 second impurity region 428 second impurity region 429 second Impurity region 430 Second impurity region 431 Third shape conductive layer 431a First conductive layer 431b Second conductive layer 432 Third shape conductive layer 432a First conductive layer 432b Second conductive layer 433 3 shape conductive layer 433a first conductive film 433b second conductive film 434 third shape conductive layer 434a first conductive film 434b second conductive film 435 third shape conductive layer 435a First conductive film 435b Second conductive film 436 Third shape conductive layer 436a First conductive film 436b Second conductive film 437 Gate insulating film 438 Resist mask 439 Resist mask 440a Third impurity region 440b Third Impurity region 440c Third impurity region 441 Insulating film 442 Insulating film 443 Insulating film 444 Drain wiring 445 Drain wiring 446 Drain wiring 447 Drain wiring 448 Connection electrode 449 Gate wiring 450 Pixel electrode 451 Connection electrode 452 Pixel portion 453 p-channel TFT
454 n-channel TFT
455 pixel TFT
456 Storage capacitor 461 Interlayer film 462 Interlayer film 463 Pixel electrode 551 Alignment film 552 Counter substrate 553 Transparent conductive film 554 Alignment film 555 Liquid crystal 601 Glass substrate 602 Pixel portion 603 Gate side driver circuit 604 Source side driver circuit 605 Pixel TFT
606 Pixel electrode 607 Retention capacitor 608 Gate wiring 609 Source wiring 610 FPC
611 External input / output terminal 612 Input / output wiring 613 Input / output wiring 614 Counter substrate 1901 Silicon substrate 1902 n-type well 1903 p-type well 1904 field oxide film 1905 gate electrode 1905a silicide layer 1905b polysilicon layer 1906 gate electrode 1906a silicide layer 1906b polysilicon Layer 1907 Extension region 1908 Extension region 1909 Side wall 1910 Side wall 1911 Gate insulating film 1912 Gate insulating film 1913 Source region 1914 Drain region 1915 Source region 1916 Drain region 1917 Interlayer insulating film 1918 Interlayer insulating film 1919 Source electrode 1920 Drain electrode 1921 Source electrode 1922 Drain electrode 1923 Passivation film 1924 Interlayer insulation 1925 p-channel transistor 1926 n-channel transistor 4001 substrate 4002 pixel portion 4003 signal line driver circuit 4004 first scan line driver circuit 4005 second scan line driver circuit 4006 substrate 4007 filling material 4008 transistor 4009 driving transistor 4010 for switching Transistor 4011 Light emitting element 4012 Electrode 4014 Wiring 4015 Wiring 4016 Connection terminal 4017 Wiring 4018 FPC
4019 Anisotropic conductive film 4020 Sealing material 5001 Display panel 5002 Pixel portion 5003 Scan line driver circuit 5004 Signal line driver circuit 5011 Circuit board 5012 Control circuit 5013 Signal dividing circuit 5014 Connection wiring 5101 Tuner 5102 Video signal amplifier circuit 5103 Video signal processing circuit 5105 Audio signal amplifying circuit 5106 Audio signal processing circuit 5107 Speaker 5108 Control circuit 5109 Input unit 5201 Case 5202 Display screen 5203 Speaker 5204 Operation switch 5210 Battery charger 5212 Case 5213 Display unit 5216 Operation key 5217 Speaker unit 5301 Display panel 5302 Print wiring Substrate 5303 Pixel portion 5304 First scan line driver circuit 5305 Second scan line driver circuit 5306 Signal line driver circuit 5307 Controller 5308 CPU
5309 Memory 5310 Power supply circuit 5311 Audio processing circuit 5312 Transmission / reception circuit 5313 Flexible printed circuit board (FPC)
5314 I / F Unit 5315 Antenna Port 5316 VRAM
5317 DRAM
5318 Flash memory 5320 Control signal generation circuit 5321 Decoder 5322 Register 5323 Arithmetic circuit 5324 RAM
5325 Input means 5326 Microphone 5327 Speaker 5328 Antenna 5330 Housing 5331 Printed circuit board 5332 Speaker 5333 Microphone 5334 Transmission / reception circuit 5335 Signal processing circuit 5336 Input means 5337 Battery 5339 Case 5340 Antenna 6001 Case 6002 Support base 6003 Display portion 6101 Main body 6102 Case 6103 Display unit 6104 Keyboard 6105 External connection port 6106 Pointing mouse 6201 Main body 6202 Display unit 6203 Switch 6204 Operation key 6205 Infrared port 6301 Case 6302 Display unit 6303 Speaker unit 6304 Operation key 6305 Recording medium insertion unit 6401 Main unit 6402 Case 6403 Display unit A
6404 Display portion B
6405 Recording medium reading unit 6406 Operation key 6407 Speaker unit

Claims (21)

A first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, and an inverter circuit;
A gate of the first n-channel transistor to which a first signal is input and a gate of the first p-channel transistor;
A first terminal of the first n-channel transistor to which a timing control signal is input;
A first terminal of the first p-channel transistor to which an inversion timing control signal is input;
And a second terminal electrically connected to the second terminal and the first p-channel transistor of the first n-channel transistor, the other,
Wherein said second terminal and said second terminal of said first p-channel transistor of the first n-channel transistor is electrically connected to an input terminal of said inverter circuit,
A gate of the second n-channel transistor and a gate of the second p-channel transistor to which the second signal output from the output terminal of the inverter circuit is input;
A first terminal of the second p-channel transistor to which the timing control signal is input;
A first terminal of the second n-channel transistor to which the inversion timing control signal is input;
And a second terminal of the second terminal and the second p-channel transistor of the electrically connected the second n-channel transistor, the other,
Wherein said second terminal of said second terminal and said second p-channel transistor of the second n-channel transistor is a semiconductor, characterized in that is electrically connected to an input terminal of the inverter circuit circuit. A first n-channel transistor, a first p-channel transistor, a second n-channel transistor, a second p-channel transistor, and an inverter circuit;
A gate of the first n-channel transistor to which a first signal is input and a gate of the first p-channel transistor;
A first terminal of the first p-channel transistor to which a timing control signal is input;
A first terminal of the first n-channel transistor to which an inversion timing control signal is input;
And a second terminal electrically connected to the second terminal and the first p-channel transistor of the first n-channel transistor, the other,
Wherein said second terminal and said second terminal of said first p-channel transistor of the first n-channel transistor is electrically connected to an input terminal of said inverter circuit,
A gate of the second n-channel transistor and a gate of the second p-channel transistor to which the second signal output from the output terminal of the inverter circuit is input;
A first terminal of the second n-channel transistor to which the timing control signal is input;
A first terminal of the second p-channel transistor to which the inversion timing control signal is input;
And a second terminal of the second terminal and the second p-channel transistor of the electrically connected the second n-channel transistor, the other,
Wherein said second terminal of said second terminal and said second p-channel transistor of the second n-channel transistor is a semiconductor, characterized in that is electrically connected to an input terminal of the inverter circuit circuit. 3. The timing control signal or the inverted timing control signal according to claim 1 or 2, wherein the timing control signal or the inverted timing control signal is supplied to the first terminal of the first n-channel transistor or the first terminal of the first p-channel transistor. A semiconductor circuit which is directly input. In any one of claims 1 to 3, wherein the timing control signal is a latch signal, a semiconductor circuit wherein the inversion timing control signal is an inverted latch signal. In any one of claims 1 to 3, wherein the timing control signal is a clock signal, a semiconductor circuit wherein the inversion timing control signal is an inverted clock signal. First n-channel transistor, first p-channel transistor, second n-channel transistor, second p-channel transistor, first inverter circuit, and third n-channel transistor A third p-channel transistor, a fourth n-channel transistor, a fourth p-channel transistor, and a second inverter circuit,
A gate of the first n-channel transistor to which a first signal is input and a gate of the first p-channel transistor;
A first terminal of the first n-channel transistor to which a clock signal is input;
A first terminal of the first p-channel transistor to which an inverted clock signal is input;
And a second terminal electrically connected to the second terminal and the first p-channel transistor of the first n-channel transistor, the other,
Wherein said second terminal of said second terminal and said first p-channel transistor of the first n-channel transistor is electrically connected to an input terminal of the first of the first inverter circuit,
A gate of the second n-channel transistor and a gate of the second p-channel transistor to which the second signal output from the output terminal of the first inverter circuit is input;
A first terminal of the second p-channel transistor to which the clock signal is input;
A first terminal of the second n-channel transistor to which the inverted clock signal is input;
And a second terminal of the second terminal and the second p-channel transistor of the electrically connected the second n-channel transistor, the other,
Wherein said second terminal of said second terminal and said second p-channel transistor of the second n-channel transistor is electrically connected to an input terminal of said first inverter circuit,
A gate of the third n-channel transistor and a gate of the third p-channel transistor to which the second signal is input;
A first terminal of the third p-channel transistor to which the clock signal is input;
A first terminal of the third n-channel transistor to which an inverted clock signal is input;
And a second terminal of the second terminal and the third p-channel transistor electrically connected to said third n-channel transistor, the other,
Wherein the second terminal of the third n-channel transistor and said second terminal of said third p-channel transistor is electrically connected to an input terminal of said second inverter circuit,
A gate of the fourth n-channel transistor and a gate of the fourth p-channel transistor to which a third signal output from the output terminal of the second inverter circuit is input;
A first terminal of the fourth n-channel transistor to which the clock signal is input;
A first terminal of the fourth p-channel transistor to which the inverted clock signal is input;
And a second terminal electrically connected to the second terminal and the fourth p-channel transistors of said fourth n-channel transistors, each other,
Wherein said second terminal of said second terminal and said fourth p-channel transistor of the fourth n-channel transistor is characterized by being electrically connected to an input terminal of the second inverter circuit A semiconductor circuit. First n-channel transistor, first p-channel transistor, second n-channel transistor, second p-channel transistor, first inverter circuit, and third n-channel transistor A third p-channel transistor, a fourth n-channel transistor, a fourth p-channel transistor, and a second inverter circuit,
A gate of the first n-channel transistor to which a first signal is input and a gate of the first p-channel transistor;
A first terminal of the first p-channel transistor to which a clock signal is input;
A first terminal of the first n-channel transistor to which an inverted clock signal is input;
And a second terminal electrically connected to the second terminal and the first p-channel transistor of the first n-channel transistor, the other,
Wherein said second terminal of said second terminal and said first p-channel transistor of the first n-channel transistor is electrically connected to an input terminal of the first of the first inverter circuit,
A gate of the second n-channel transistor and a gate of the second p-channel transistor to which the second signal output from the output terminal of the first inverter circuit is input;
A first terminal of the second n-channel transistor to which the clock signal is input;
A first terminal of the second p-channel transistor to which the inverted clock signal is input;
And a second terminal of the second terminal and the second p-channel transistor of the electrically connected the second n-channel transistor, the other,
Wherein said second terminal of said second terminal and said second p-channel transistor of the second n-channel transistor is electrically connected to an input terminal of said first inverter circuit,
A gate of the third n-channel transistor and a gate of the third p-channel transistor to which the second signal is input;
A first terminal of the third n-channel transistor to which the clock signal is input;
A first terminal of the third p-channel transistor to which the inverted clock signal is input;
And a second terminal of the second terminal and the third p-channel transistor electrically connected to said third n-channel transistor, the other,
Wherein the second terminal of the third n-channel transistor and said second terminal of said third p-channel transistor is electrically connected to an input terminal of said second inverter circuit,
A gate of the fourth n-channel transistor and a gate of the fourth p-channel transistor to which a third signal output from the output terminal of the second inverter circuit is input;
A first terminal of the fourth p-channel transistor to which the clock signal is input;
A first terminal of the fourth n-channel transistor to which the inverted clock signal is input;
And a second terminal electrically connected to the second terminal and the fourth p-channel transistors of said fourth n-channel transistors, each other,
Wherein said second terminal of said second terminal and said fourth p-channel transistor of the fourth n-channel transistor is characterized by being electrically connected to an input terminal of the second inverter circuit A semiconductor circuit. 8. The clock signal or the inverted clock signal according to claim 6, wherein the clock signal or the inverted clock signal is directly input to the first terminal of the first n-channel transistor or the first terminal of the first p-channel transistor. A semiconductor circuit characterized by being made. N-channel transistor and the p-channel transistor according to any one of claims 1 to 8, a semiconductor circuit, characterized in that each is a thin film transistor formed on a glass substrate. N-channel transistor and the p-channel transistor according to any one of claims 1 to 8, the semiconductor circuit being formed on a single crystal substrate. A gate driver, a source driver, and the pixel driver electrically connected to the gate driver and the source driver;
The source driver includes a shift register circuit and a latch circuit,
The gate driver includes a shift register circuit,
The shift register circuit and latch circuit of the source driver and the shift register circuit of the gate driver are respectively a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, A semiconductor circuit including two p-channel transistors and an inverter circuit;
The semiconductor circuit is:
A gate of the first n-channel transistor to which a first signal is input and a gate of the first p-channel transistor;
A first terminal of the first n-channel transistor to which a timing control signal is input;
A first terminal of the first p-channel transistor to which an inversion timing control signal is input;
And a second terminal electrically connected to the second terminal and the first p-channel transistor of the first n-channel transistor, the other,
Wherein said second terminal and said second terminal of said first p-channel transistor of the first n-channel transistor is electrically connected to an input terminal of said inverter circuit,
A gate of the second n-channel transistor and a gate of the second p-channel transistor to which the second signal output from the output terminal of the inverter circuit is input;
A first terminal of the second p-channel transistor to which the timing control signal is input;
A first terminal of the second n-channel transistor to which the inversion timing control signal is input;
And a second terminal of the second terminal and the second p-channel transistor of the electrically connected the second n-channel transistor, the other,
Display the second terminal of said second terminal and said second p-channel transistor of the second n-channel transistor is characterized in that it is electrically connected to an input terminal of the inverter circuit apparatus. A gate driver, a source driver, and the pixel driver electrically connected to the gate driver and the source driver;
The source driver includes a shift register circuit and a latch circuit,
The gate driver includes a shift register circuit,
The shift register circuit and latch circuit of the source driver and the shift register circuit of the gate driver are respectively a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, A semiconductor circuit including two p-channel transistors and an inverter circuit;
The semiconductor circuit is:
A gate of the first n-channel transistor to which a first signal is input and a gate of the first p-channel transistor;
A first terminal of the first p-channel transistor to which a timing control signal is input;
A first terminal of the first n-channel transistor to which an inversion timing control signal is input;
And a second terminal electrically connected to the second terminal and the first p-channel transistor of the first n-channel transistor, the other,
Wherein said second terminal and said second terminal of said first p-channel transistor of the first n-channel transistor is electrically connected to an input terminal of said inverter circuit,
A gate of the second n-channel transistor and a gate of the second p-channel transistor to which the second signal output from the output terminal of the inverter circuit is input;
A first terminal of the second n-channel transistor to which the timing control signal is input;
A first terminal of the second p-channel transistor to which the inversion timing control signal is input;
And a second terminal of the second terminal and the second p-channel transistor of the electrically connected the second n-channel transistor, the other,
Display the second terminal of said second terminal and said second p-channel transistor of the second n-channel transistor is characterized in that it is electrically connected to an input terminal of the inverter circuit apparatus. A gate driver, a source driver, and the pixel driver electrically connected to the gate driver and the source driver;
The source driver includes a shift register circuit and a latch circuit,
The gate driver includes a shift register circuit,
The shift register circuit of the source driver and the shift register circuit of the gate driver are respectively a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, and a second p-channel transistor. A channel transistor, a first inverter circuit, a third n-channel transistor, a third p-channel transistor, a fourth n-channel transistor, a fourth p-channel transistor, and a second A plurality of semiconductor circuits composed of the inverter circuit of
The semiconductor circuit is:
A gate of the first n-channel transistor to which a first signal is input and a gate of the first p-channel transistor;
A first terminal of the first n-channel transistor to which a clock signal is input;
A first terminal of the first p-channel transistor to which an inverted clock signal is input;
And a second terminal electrically connected to the second terminal and the first p-channel transistor of the first n-channel transistor, the other,
Wherein said second terminal of said second terminal and said first p-channel transistor of the first n-channel transistor is electrically connected to an input terminal of the first of the first inverter circuit,
A gate of the second n-channel transistor and a gate of the second p-channel transistor to which the second signal output from the output terminal of the first inverter circuit is input;
A first terminal of the second p-channel transistor to which the clock signal is input;
A first terminal of the second n-channel transistor to which the inverted clock signal is input;
And a second terminal of the second terminal and the second p-channel transistor of the electrically connected the second n-channel transistor, the other,
Wherein said second terminal of said second terminal and said second p-channel transistor of the second n-channel transistor is electrically connected to an input terminal of said first inverter circuit,
A gate of the third n-channel transistor and a gate of the third p-channel transistor to which the second signal is input;
A first terminal of the third p-channel transistor to which the clock signal is input;
A first terminal of the third n-channel transistor to which the inverted clock signal is input;
And a second terminal of the second terminal and the third p-channel transistor electrically connected to said third n-channel transistor, the other,
Wherein the second terminal of the third n-channel transistor and said second terminal of said third p-channel transistor is electrically connected to an input terminal of said second inverter circuit,
A gate of the fourth n-channel transistor and a gate of the fourth p-channel transistor to which a third signal output from the output terminal of the second inverter circuit is input;
A first terminal of the fourth n-channel transistor to which the clock signal is input;
A first terminal of the fourth p-channel transistor to which the inverted clock signal is input;
And a second terminal electrically connected to the second terminal and the fourth p-channel transistors of said fourth n-channel transistors, each other,
Wherein said second terminal of said second terminal and said fourth p-channel transistor of the fourth n-channel transistor is characterized by being electrically connected to an input terminal of the second inverter circuit Display device. A gate driver, a source driver, and the pixel driver electrically connected to the gate driver and the source driver;
The source driver includes a shift register circuit and a latch circuit,
The gate driver includes a shift register circuit,
The shift register circuit of the source driver and the shift register circuit of the gate driver are respectively a first n-channel transistor, a first p-channel transistor, a second n-channel transistor, and a second p-channel transistor. A channel transistor, a first inverter circuit, a third n-channel transistor, a third p-channel transistor, a fourth n-channel transistor, a fourth p-channel transistor, and a second A plurality of semiconductor circuits composed of the inverter circuit of
The semiconductor circuit is:
A gate of the first n-channel transistor to which a first signal is input and a gate of the first p-channel transistor;
A first terminal of the first p-channel transistor to which a clock signal is input;
A first terminal of the first n-channel transistor to which an inverted clock signal is input;
And a second terminal electrically connected to the second terminal and the first p-channel transistor of the first n-channel transistor, the other,
Wherein said second terminal of said second terminal and said first p-channel transistor of the first n-channel transistor is electrically connected to an input terminal of the first of the first inverter circuit,
A gate of the second n-channel transistor and a gate of the second p-channel transistor to which the second signal output from the output terminal of the first inverter circuit is input;
A first terminal of the second n-channel transistor to which the clock signal is input;
A first terminal of the second p-channel transistor to which the inverted clock signal is input;
And a second terminal of the second terminal and the second p-channel transistor of the electrically connected the second n-channel transistor, the other,
Wherein said second terminal of said second terminal and said second p-channel transistor of the second n-channel transistor is electrically connected to an input terminal of said first inverter circuit,
A gate of the third n-channel transistor and a gate of the third p-channel transistor to which the second signal is input;
A first terminal of the third n-channel transistor to which the clock signal is input;
A first terminal of the third p-channel transistor to which the inverted clock signal is input;
And a second terminal of the second terminal and the third p-channel transistor electrically connected to said third n-channel transistor, the other,
Wherein the second terminal of the third n-channel transistor and said second terminal of said third p-channel transistor is electrically connected to an input terminal of said second inverter circuit,
A gate of the fourth n-channel transistor and a gate of the fourth p-channel transistor to which a third signal output from the output terminal of the second inverter circuit is input;
A first terminal of the fourth p-channel transistor to which the clock signal is input;
A first terminal of the fourth n-channel transistor to which the inverted clock signal is input;
And a second terminal electrically connected to the second terminal and the fourth p-channel transistors of said fourth n-channel transistors, each other,
Wherein said second terminal of said second terminal and said fourth p-channel transistor of the fourth n-channel transistor is characterized by being electrically connected to an input terminal of the second inverter circuit Display device. 13. The timing control signal or the inverted timing control signal according to claim 11 or 12, wherein the timing control signal or the inverted timing control signal is supplied to the first terminal of the first n-channel transistor or the first terminal of the first p-channel transistor. A display device that is directly input. 15. The clock signal or the inverted clock signal according to claim 13, wherein the clock signal or the inverted clock signal is directly input to the first terminal of the first n-channel transistor or the first terminal of the first p-channel transistor. A display device. N-channel transistor and the p-channel transistor according to any one of claims 11 to 16, a display device, characterized in that each is a thin film transistor formed on a glass substrate. N-channel transistor and the p-channel transistor according to any one of claims 11 to 16, the display device characterized by being formed on a single crystal substrate. Display device according to any one of claims 11 to 18, a display device, characterized in that in which a liquid crystal or EL element. An electronic device characterized by using the display device according to any one of claims 11 to 19. The electronic device according to claim 20 is a television receiver, a video camera, a digital camera, a goggle type display, a navigation system, a sound reproduction device, a computer, a game device, a mobile computer, a mobile phone, a portable game machine, an electronic book, An electronic device characterized by being an image reproducing device.

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