JP4941103B2 - Multiprocessor system, exclusive control method, vehicle electronic control unit - Google Patents

Description

  The present invention relates to a multiprocessor system and the like, and more particularly to a multiprocessor system, an exclusive control method, and a vehicle electronic control unit that perform exclusive control when a plurality of CPUs access a shared memory.

  In a multi-processor system (hereinafter referred to as MPS) including a plurality of arithmetic units such as a CPU core, each arithmetic unit may access a shared memory such as a RAM, and thus exclusive processing to the shared memory is required.

  An RMW (Read Modify Write) instruction is known as an exclusive process. FIG. 7A shows a conceptual diagram of processing by the RMW instruction. In the RMW instruction of FIG. 7A, a series of processes are executed: a) reading data 204 at a predetermined address, b) processing the data 204, and c) writing the processed data 204 to the original address. The

  In FIG. 7A, a predetermined bit (for example, flag) of the read data 204 is rewritten and written to the original address of the RAM 200. Even if the CPU core 100b rewrites the same data 204 while the CPU core 100a is executing the process b), the CPU core 100a subsequently overwrites the data 204 by the process c). The data 204 that should have been written will be lost. For this reason, the RMW instruction has an interrupt prohibiting function, and prohibits the accelerator of the CPU core 100b to the RAM 200 during the series of processes a) to c).

  However, if the RMW instruction is described in the source code, the compiler automatically recognizes it and can execute the above exclusion process. However, the compiler recognizes the RMW process that does not use the RMW instruction (through several steps). Can not. For this reason, it is necessary for the programmer to describe the exclusive process from the start to the end of the RMW process.

  For example, in control software such as an engine, when calculating data representing the state of the engine as an input value, the input value data is acquired in the first process, and other data associated with the RMW process is calculated in the intermediate process. There are many RMW processes that do not use the RMW instruction, such as updating the data of the input value in the last process, but it is necessary to describe the exclusive process in all such broad RMW processes.

  In addition, during the RMW process, if the CPU core 100a prohibits access by using the RAM 200 as one resource for the exclusive process, the CPU core 100b cannot access the RAM 200 during that time, resulting in an increase in overhead.

With regard to this point, a technique has been proposed that prohibits the access of other CPUs only to addresses that are processed by the CPU (see, for example, Patent Document 1). Patent Document 1 describes an MPS that holds its memory address when its own CPU executes RMW processing and detects whether the address output to the system bus matches the memory address. When a match is detected, an access interruption signal is sent to the other CPU, thereby prohibiting the other CPU from accessing only the address to be processed.
JP-A-7-93259

  However, in the technique described in Patent Document 1, since access is prohibited based on the coincidence of memory addresses, other CPUs cannot access the shared memory in both read and write accesses, and there is a problem that overhead is large. is there. In addition, when the own CPU accesses another memory address while executing the RMW process, the other CPU can access the target variable (the above input value data) of the RMW process. There is a risk of rewriting.

  By the way, as an MPS exclusion process, in addition to the RMW (read-modify-write) process, a process for ensuring simultaneity can be mentioned.

  FIG. 7B shows a conceptual diagram of a conventional MPS in which two CPU cores 100 a and 100 b share the RAM 200. Ensuring simultaneity means that, for example, a plurality of related data is required to be updated simultaneously (in a series of processes) in preference to other processes. For example, in the control software for controlling the engine, the engine state is represented by a plurality of data. However, if the original engine state changes, the plurality of data must be updated simultaneously. For example, when the data 201 to 203 is related data and the CPU core 100a updates the data 201 to 203, the CPU core 100b may access the data 203 in connection with another control of the engine. In order to ensure simultaneity, it is necessary to describe an instruction for prohibiting access to the RAM 200 during the update of the data 201 to 203 on the program. However, since there are many pieces of data that need to ensure simultaneity in the control software, if a forbidden instruction is described in all the processes that access the RAM 200, man-hours will increase and the burden on the programmer will increase. There's a problem.

  SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a multiprocessor system, an exclusive control method, and a vehicle that realizes a process for ensuring simultaneity by reducing overhead of RMW processing and suppressing an increase in the number of man-hours in exclusive processing of a multiprocessor system. An object of the present invention is to provide an electronic control unit.

  In order to solve the above problems, the present invention stores a first data ID of data accessed by a first CPU core (for example, the CPU core 11a) in a multiprocessor system in which a plurality of CPU cores execute a program in parallel. A first data ID register (for example, usage ID register 11a) and a second data ID register (for example, usage ID register 11b) for storing a second data ID of data accessed by the second CPU core (for example, CPU core 11b) And a data table storage means (for example, RAM 10) shared by a plurality of CPU cores, which stores a data table in which at least a part of the data ID is matched with a plurality of related data, and a first data ID Stored in the first data ID and second data ID registers stored in the register When the comparison result by the data ID comparison means (for example, the comparison circuit 16) for comparing the second data ID and the data ID comparison means indicates coincidence, either the first CPU core or the second CPU core accesses the data table. Is suspended.

  To provide a multiprocessor system, an exclusive control method, and a vehicular electronic control unit that realizes a process for ensuring simultaneity by reducing overhead of RMW processing and suppressing an increase in the number of man-hours in exclusive processing of a multiprocessor system. it can.

The best mode for carrying out the present invention will be described below with reference to the drawings.
FIG. 1 is a schematic configuration diagram of a multiprocessor system (hereinafter referred to as MPS) 100 according to the present embodiment. The MPS 100 of this embodiment is described in the program 21 so as to associate a plurality of related data, and is compiled so that a data ID at least partially matching the plurality of related data is given by the compiler. When the CPU cores 11a and 11b access data, the data ID of the data is stored in the use ID registers 12a and 12b. When any of the CPU cores 11a and 11b accesses data, the data in the use ID register 12a is stored. If the ID matches the data ID of the use ID register 12b, the CPU core 11a or 11b suspends access. While one of the CPU cores 11a and 11b is processing data with the same data ID, the other cannot access data with the same data ID, so that the simultaneity of a plurality of related data can be ensured.

  In addition, use RMWID registers 13a and 13b that store data IDs to be processed in the RMW process are provided, and when any of the CPU cores 11a (11b) has write access to data, the data in the use ID register 12a (12b) The exclusive process during the RMW process is realized by comparing the ID and the data ID of the used RMWID register 13b (13a), and if the IDs match, the writing is suspended.

  The MPS 100 is one form of a computer incorporated in a control system ECU such as an engine ECU (electronic control unit) and a brake ECU, or a body system ECU such as a body ECU and an air conditioner ECU. The MPS 100 is connected to another ECU via an in-vehicle LAN such as a CAN (Controller Area Network) or a LIN (Local Interconnect Network), and realizes cooperative control of the in-vehicle device.

  The MPS 100 includes a ROM 15, CPU cores 11a and 11b (if not distinguished, simply referred to as CPU core 11), RAM 10, use ID registers 12a and 12b (if not distinguished, simply referred to as use ID register 12), and use RMWID registers 13a and 13b ( If they are not distinguished, the used RMWID register 13 is simply connected to the internal bus. In addition, you may provide the input / output interface connected to in-vehicle LAN, and a communication apparatus with other ECU. The CPU cores 11a and 11b may be the same CPU core, or may be CPU cores having different configurations.

  The ROM 15 stores files such as a program (object code) 21 converted into an execution format by compilation, a control map, and setting information. By executing the program 21 by the CPU cores 11a and 11b, for example, the throttle opening of the engine, the fuel injection amount, and the like are controlled.

  The CPU cores 11a and 11b execute each thread of the program 21 upon occurrence of a predetermined procedure or event. For example, the processing distribution circuit 14 distributes the threads associated at the time of compilation to the CPU cores 11a and 11b, or distributes the threads to lighter loads while monitoring the loads on the CPU cores 11a and 11b.

  When executing the program 21, the CPU cores 11a and 11b develop a part or the whole of the program 21 in the RAM 10, and execute the program 21 using the RAM 10 as a work area. The CPU cores 11a and 11b repeat the steps of fetching (reading) reading instructions and data in the RAM 10 for each word unit, decoding to decode the instructions, calculation according to the instructions, and storing (writing) the calculation results in the RAM 10.

  The MPS 100 of this embodiment stores a data ID for identifying data in the use ID register 12a and the use RMWID register 13a connected to the CPU core 11a, and the use ID register 12b and the use RMWID register 13b connected to the CPU core 11b. To do. These registers are preferably dedicated registers, and store the data ID in the procedure described later.

  Further, the MPS 100 compares the data IDs stored in the usage ID register 12a and the usage ID register 12b, and the comparison unit 17 compares the data IDs stored in the usage ID register 12a and the usage RMWID register 13b. The comparison means 18 for comparing the data IDs stored in the use ID register 12b and the use RMWID register 13a, the comparison means 19 for comparing the data IDs stored in the use ID register 12a and the use RMWID register 13a, and the use ID register Comparing means 20 for comparing the data IDs stored in 12b and the used RMWID register 13b is provided so that the CPU cores 11a and 11b can detect the comparison results.

[Data ID]
First, the data ID will be described. FIG. 2 shows an example of the data table 22 stored in the RAM 10. The data table 22 is included in the program 21 and is expanded simultaneously when the program 21 is expanded in the RAM 10. Note that the address of the data may be stored instead of the data itself.

In the data table 22, data IDs are associated with the structures st_A and st_B, the array array, and the variables data_X and data_Y. The structures st_A and st_B are forms of variables for handling the variables a and b in association with each other, and are described as follows in the C language, for example.
struct {
float a;
float b;
} st_A, st_B;
Float a and float b are called structure members in the C language, and allow variables st_A.a and st_A.b and st_B.a and st_B.b to be handled in association with each other.

The array array is one form of variables for handling variables stored in a plurality of areas secured by the array in association with each other, and is described as follows in the C language.
float ary [2]
By declaring the array arrey, it becomes possible to associate and handle the variables stored in array [0] and the variables stored in array [1].
You can also associate other variables with structures and arrays. For example, when the variable data_X is associated with the structures st_A and st_B, the structure is described as follows.
struct {
float a;
float b;
float c;
} st_A;
float data_X;
int main () {
st_A.c = data_X;
Variables described in a predetermined format by compiling using a compiler in which a compile rule is set so that the format is determined in advance and the same data ID or a partially matching data ID is assigned to the format. Can be compiled to give the same data ID or a partially matching data ID. In FIG. 2, the variables st_A.a and st_A.b have the same data ID (10 in the figure), st_B.a and st_B.b have the same data ID (20 in the figure), and array [0] The variable ID stored in array [1] and the variable stored in array [1] both have the same data ID (22 in the figure). The data ID “11” of the variable data_X associated with the structure st_A partially matches the data ID “10” of st_A.

  The comparison circuits 16, 17, 18, 19, 20 have, for example, an EXNOR circuit that compares whether each bit matches, and when all the bits match, and when a predetermined number of bits or more match Outputs the comparison result that matches. Thereby, a plurality of data whose data IDs do not completely match can be handled as matching.

  For example, when the MPS 100 controls the engine, the plurality of related data is a plurality of data representing the state of the engine. By associating a plurality of data with the source code, it is possible to automatically give a matching data ID by compilation. Since the data ID is assigned by the compiler, it is not necessary for the programmer to correct the data ID even when the source code of the program 21 is corrected.

[Ensuring simultaneity]
The securing of the simultaneity of a plurality of related data using the use ID registers 12a and 12b will be described. FIG. 3 shows a transition diagram of the data ID stored in each register in the process of ensuring simultaneity.

  The use ID register 12a stores the data ID based on the access request of the CPU core 11a and the use ID register 12b stores the data ID based on the access request. The comparison circuit 16 uses the use ID register 12a and the use ID register 12b each time the data ID is stored. The CPU core 11 suspends access to the data table 22 when the comparison result indicates a match.

  i) When the CPU core 11a first accesses data (eg, st_A.a) having a predetermined data ID, the use ID register 12a stores the data ID (eg, “10”) of the data.

  ii) Next, when the CPU core 11b accesses data of a predetermined data ID (for example, st_A.b), the use ID register 12b stores the data ID of the data (for example, “10”).

  During this time, the CPU core 11a performs, for example, update processing of st_A.a and st_A.b that are related data.

  iii) Since the comparison circuit 16 outputs the comparison result compared with the data ID of the usage ID register 12a and the usage ID register 12b, the CPU core 11b suspends access to the RAM 10 when the comparison result indicates a match. If the match is not indicated, the CPU core 11b does not interrupt the access to the RAM 10, so that the CPU core 11b can process the thread being executed.

  iv) Each time the CPU core 11a accesses the data table 22, the use ID register 12a stores (overwrites) the data ID of the data to be accessed. Therefore, when the CPU core 11a accesses unrelated data, the use ID register 12a is also written. change.

  v) The comparison circuit 16 repeats the comparison of the data ID every predetermined cycle time, and the CPU core 11b accesses the RAM 10 when the comparison result does not indicate coincidence.

  Therefore, while the CPU core 11a is performing update processing or the like for a plurality of related data that needs to be updated at the same time, the other CPU cores 11b cannot access the related data. Simultaneity can be ensured. For example, the CPU core 11b can access the data after a plurality of related data is updated.

  Since there is no need for a description for ensuring simultaneity in the program 21 except for the description of a plurality of related data, an increase in the man-hour of the program 21 can be suppressed. In addition, since the use ID register 12 controls the prohibition / permission of the access to the CPU core 11, processing can be performed at a high speed, and the overhead required for ensuring the simultaneity can be minimized.

  In addition, related data that cannot be grouped into a structure or array is handled as data related to a structure or array by adding a description according to the grammar in addition to the declaration of the structure or array. Therefore, related data can be set flexibly.

[RMW processing]
Exclusion processing during RMW processing using the use ID registers 12a and 12b and the use RMWID registers 13a and 13b will be described.

For RMW processing that cannot be recognized by the compiler, a description indicating RMW processing is added to the source code of the program 21 in order to cause the MPS 100 to detect that the series of processing is RMW processing. For example, an RMW_start instruction that indicates the start of the RMW process is described immediately before the RMW process, and an RMW_end instruction that indicates the end of the RMW process is described immediately after.
RMW_start
RMW processing (target variable)
RMW_end
Further, the CPU cores 11a and 11b include RMW detection means 23a and 23b for detecting RMW_start and RMW_end, respectively. When detecting the RMW_start, the CPU cores 11a and 11b store the data ID of the target variable of the RMW process in the use ID registers 12a and 12b and the use RMWID registers 13a and 13b. Each RMW process and the target variable are associated at the time of compilation.

  When the CPU core 11b executes the RMW process, the data ID of the use ID register 12b is overwritten one after another because of the process accompanying the RMW process during the RMW process, but the data ID of the use RMWID register 13 is RMW_end Will not be deleted until is detected.

  Therefore, for example, the CPU core 11a not performing the RMW process can access the data table 22 while the CPU core 11b performs the RMW process as long as the data IDs of the use ID registers 12a and 12b do not match.

  However, while the CPU core 11b is executing the RMW process, inconsistency occurs when the other CPU core 11a writes to the target variable of the RMW process, so the CPU core 11a only executes the write command. The comparison circuit 17 is requested to compare the data IDs of the use ID register 12a and the use RMWID register 13b, and the CPU core 11a suspends the writing when the comparison result indicates coincidence. With this configuration, during the RMW process, the other CPU core 11a can access the data table 22 except for a write command. The comparison circuits 17 and 18 may output a comparison result every time data is accessed.

  A procedure for storing the data ID in the use ID register 12a and the use RMWID register 13a when the CPU core 11a performs the RMW process will be described with reference to the transition diagram of the data ID stored in each register of FIG.

  i) When the RMW detection circuit 23a detects RMW_start, the CPU core 11a uses the data ID (eg, “22”) of the RMW processing target variable (eg, array [0]) in the use ID register 12a and the use RMWID register 13a. Store in each. For example, the compiler generates a data ID storage instruction in advance in, for example, a description location of RMW_start.

  ii) Next, the CPU core 11a successively stores data IDs of other data to be processed in accordance with the RMW process in the use ID register 12a. For this reason, the data ID stored in the use ID register 12a often fluctuates during RMW processing.

  iii) Next, when the CPU core 11b accesses predetermined data (for example, array [1]), the CPU core 11b stores the data ID (for example, “22”) of the data in the use ID register 12b.

  iv) During the RMW process, the data IDs stored in the usage ID registers 12a and 12b often do not match, so the data IDs stored in the usage ID registers 12a and 12b do not match, and the CPU core 11b You can access the data.

  However, only when the CPU core 11b executes a write command, the CPU core 11b requests the detection circuit 18 to compare the data IDs of the use ID register 12b and the use RMWID register 13a. If the comparison result indicates a match, the CPU core 11b suspends access to the data table 22. If they do not match, the CPU core 11b can write to the data table 22, and the CPU core 11b can process the thread being executed.

  v) Since the CPU core 11a always stores the processing result of the target variable of the RMW process in the data table 22 before RMW_end, the data ID of the target variable is stored in the use ID register 12a.

  As a result, when the CPU core 11b holds the access, the same data ID is stored in the use ID register 12a and the use ID register 12b, and this time the CPU core 11a accesses the data table 22. It will be prohibited. However, in order to give priority to storing the result of the RMW process, when executing the write command, the CPU core 11a requests the comparison circuit 19 to compare the data IDs of the use ID register 12a and the use RMWID register 13a, and the comparison result indicates coincidence. In this case, the CPU core 11a accesses the target variable of the data table 22.

  vi) Next, when the CPU core 11a detects RMW_end, the CPU core 11a deletes the data ID of the target variable stored in the use ID register 12a and the use RMWID register 13a.

  As a result, the data IDs stored in the use ID registers 12a and 12b do not match, and the CPU core 11b can write to the target variable.

  With the above procedure, exclusive processing can be realized for RMW processing that cannot be recognized by a compiler or the like. Even if access to the target variable of RMW processing occurs, access other than the write command is permitted, so that overhead can be suppressed to a minimum. Further, even when a write command is issued, the exclusive process is executed only for access to the target variable of the RMW process, so that access to the entire RAM 10 is not prohibited and overhead can be reduced.

  By the way, the CPU cores 11a and 11b may partially overlap in time and execute the same RMW processing (that is, the same target variable).

CPU core 11a CPU core 11b
RMW_start
RMW processing (target variable) RMW_start
RMW_end RMW processing (target variable)
RMW_end
In this case, the CPU core 11a reads and writes the target variable first. However, since the CPU core 11b reads and writes the same target variable after that, it is difficult to ensure the consistency of the target variable. For this reason, for example, access is restricted as follows.

  Since the data ID of the target variable is stored first in either the used RMWID register 13a or 13b, the CPU core 11 that will execute the RMW process will compare the data ID of the target variable with the data ID of the other used RMWID register 13. However, if they match, the CPU core 11 that performs RMW processing later may suspend access (reading).

The access rules in the above RMW processing can be summarized as follows. Here, it is assumed that the CPU core 11a executes the RMW process.
A. When the data IDs of the usage ID register 12a and the usage ID register 12b match, the CPU cores 11a and 11b are prohibited from accessing the RAM 10.
B. However, access is permitted in the following cases.

  b1: When the case where the CPU core 11a executes a write command is assumed, the use ID register 12a and the use RMWID register 13a have the same data ID. Thereby, the CPU core 11a can write the processing result of the RMW process in the data table 22.

  b2: When the case where the CPU core 11b executes a write command is assumed, there is no value in the use ID register 12b, or the data IDs of the use ID register 12b and the use RMWID register 13a do not match. Thereby, the CPU core 11b can write data other than the target variable of the RMW process. The use ID register 12b has no value when, for example, accessing data without a data ID (exclusion processing is not required).

  b3: Assuming that the CPU core 11a executes a read instruction, the data IDs of the use ID register 12a and the use RMDID register 13a match, and the use ID register 12a, the use ID register 12b, and the use ID register 12a The data IDs in the RMWID register 13b do not match. Thereby, the CPU core 11a can read the target variable when the CPU core 11b is not executing the same RMW process.

  b4: Assuming that the CPU core 11a executes a read instruction, the use RMWID register 13a has no value. If there is no value in the used RMWID register 13a, a new RMW process can be executed.

[Processing procedure of MPS 100]
5 and 6 are flowcharts showing a procedure in which the MPS 100 ensures simultaneity and performs exclusive processing during RMW processing. The process shown in FIG. 5 starts when the MPS 100 is activated by, for example, ignition on.

  The CPU core 11a or 11b determines whether access to the data table 22 or RMW_start is detected (S1-1). If neither is detected, the determination in step S1-1 is repeated, and if RMW_start is detected, the process proceeds to step S2-1 in FIG.

  If the CPU core 11a detects access to the data table 22, the CPU core 11a stores the data ID of the data to be accessed in the use ID register 12a (S1-2).

  Next, the CPU core 11a determines whether or not the data IDs of the use ID register 12a and the use RMWID register 13a match (S1-3). This determination is a determination for enabling writing of the processing result of the RMW process.

  That is, if they match (Yes in S1-3), the CPU core 11a determines whether the access instructed by the program 21 is a write command (S1-10), and if it is a write command (Yes in S1-10). The CPU core 11a accesses (writes) the data in order to write the processing result of the RMW process (S1-7). If it is not a write command (No in S1-10), it can be handled in the same manner as the case where the data IDs of the used RMWID register 13a and the used ID register 12a do not match, so the process proceeds to step S1-4.

  If they do not match (No in S1-3), the CPU core 11a determines whether or not the data IDs in the use register ID 12a and the use ID register 12b match (S1-4). If they match (Yes in S1-4), the CPU core 11a suspends access to the data and repeats the determination in step S1-4 (S1-5). Thereby, the simultaneity of a plurality of related data can be secured.

  If the data IDs of the use register ID 12a and the use ID register 12b do not match (No in S1-4), the CPU core 11a determines whether the access instructed by the program 21 is a write command (S1-6).

  If it is not a write command (No in S1-6), the CPU core 11a accesses the data in the data table 22 (S1-7).

  In the case of a write command (Yes in S1-6), the CPU core 11a determines whether or not the data IDs in the use ID register 12a and the use RMWID register 13b match (S1-8). By this determination, when the CPU core 11b is executing the RMW process, the CPU core 11b can realize the exclusive process of the target variable.

  Therefore, if they match (Yes in S1-8), the CPU core 11a suspends access to the data and repeats the determination in step S1-8 (S1-9).

  If they do not match (No in S1-8), even if the CPU core 11b is not performing RMW processing or not, the target variable and the data accessed by the CPU core 11a are different. Access (S1-7).

  Proceeding to step S2-1 in FIG. 6, when RMW_start is detected, the CPU core 11a determines whether or not the data ID of the target variable of the RMW process matches the data ID of the used RMWID register 13b (S2- 1). If they match (Yes in S2-1), the CPU core 11a and the CPU core 11b are about to execute the RMW process on the same target variable, so the CPU core 11a finishes the RMW process of the CPU core 11b. (Until the data ID of the used RMWID register 13b is deleted), the CPU core 11a suspends access to the data (S2-8).

  If they do not match (Yes in S2-1), the CPU core 11a stores the data ID of the target variable for RMW processing in the usage ID register 12a (S2-2) and also stores it in the usage RMWID register 13a (S2- 3).

  Next, the CPU core 11a reads the target variable of the RMW process (S2-4), and performs arithmetic processing according to the RMW process on the target variable (S2-5).

  When the arithmetic processing is completed, the CPU core 11a writes the target variable to the data table 22 (S2-6). Here, since the data IDs of the usage ID register 12a and the usage ID register 12b are not compared, the CPU core 11a can preferentially write the target variable of the RMW process even if they match.

  Next, the CPU core 11a deletes the data ID in the used RMWID register 13a (S2-7). Note that the use ID register 12a is overwritten and may or may not be erased.

  As described above, the MPS 100 of the present embodiment describes the program 21 so that the same data ID is assigned to a plurality of related data, and when the data IDs of the usage ID registers 12a and 12b match, Since the access of the CPU core 11 to be processed is prohibited, the simultaneity of a plurality of related data can be ensured. Further, even if the data IDs do not completely match, if the data IDs are partially in common, access to the CPU core 11 is prohibited, so that related data can be designed flexibly.

  Since it is realized by data declaration and register, the program 21 does not need to describe access control and can be executed at high speed.

  Also, the RMW process is exclusive only when the other CPU core 11 writes, and access to the entire RAM 10 is permitted, so the overhead of the exclusive process can be reduced. For RMW processing that cannot be recognized by the compiler, exclusive processing can be realized simply by describing the start and end of the RMW processing.

  In this embodiment, the number of CPU cores 11 is two. However, when three or more CPU cores 11 are provided, each CPU core 11 is provided with a use ID register 12 and a use RMWID register 13, and other CPU cores 11. The MPS 100 of this embodiment can be suitably realized by connecting so that it can be compared with this register.

It is a schematic block diagram of a multiprocessor system. It is a figure which shows an example of the data table memorize | stored in RAM. It is a transition diagram of data ID stored in each register in the process of ensuring simultaneity. It is a transition diagram of data ID stored in each register in RMW processing. FIG. 11 is a flowchart showing a procedure for ensuring simultaneity by the multiprocessor system and performing exclusive processing during RMW processing. FIG. 11 is a flowchart showing a procedure for ensuring simultaneity by the multiprocessor system and performing exclusive processing during RMW processing. It is an example of the conceptual diagram of the process by the conventional RMW instruction, and the conceptual diagram of the concurrency of a process.

Explanation of symbols

10 RAM
11a, 11b CPU core 12a, 12b Use ID register 13a, 13b Use RMWID register 14 Processing distribution circuit 15 ROM
16, 17, 18, 19, 20 Comparison circuit 21 Program
22 Data table 23a, 23b RMW detection means 100 Multiprocessor system

Claims (6)

In a multiprocessor system in which a plurality of CPU cores execute a program in parallel,
A first data ID register that stores a first data ID of data accessed by the first CPU core; a second data ID register that stores a second data ID of the data accessed by the second CPU core;
A data table storage means shared by a plurality of the CPU cores, which stores a data table in which a data ID at least a part of which corresponds to a plurality of the related data in advance is stored;
Data ID comparing means for comparing the first data ID stored in the first data ID register and the second data ID stored in the second data ID register;
If the comparison result by the data ID comparison means indicates a match, either the first CPU core or the second CPU core suspends access to the data table.
A multiprocessor system characterized by that. The data ID comparing means outputs a comparison result that the first data ID and the second data ID match when a part of the first data ID and the second data ID match.
The multiprocessor system according to claim 1, wherein: The data ID is given by a compiler that compiles a source code in which the data is described.
The multiprocessor system according to claim 2, wherein: Detection means provided for each CPU core for detecting the start of predetermined processing;
A first predetermined processing data ID register for storing a first target data ID of a target variable accessed by the first CPU core when the detection means of the first CPU core detects the start of the predetermined processing;
A second predetermined processing data ID register for storing a second target data ID of a target variable accessed by the second CPU core when the detection means of the second CPU core detects the start of the predetermined processing;
A comparison means A for comparing the first data ID stored in the first data ID register with the second target data ID stored in the second predetermined processing data ID register;
Comparing means B for determining whether or not the second data ID stored in the second data ID register matches the first target data ID stored in the first predetermined processing data ID register,
The first CPU core suspends execution of the write instruction when the first CPU core executes the write instruction and the comparison result by the comparison unit A indicates a match,
The second CPU core suspends execution of the write command when the second CPU core executes the write command and the comparison result by the determination unit B indicates a match.
The multiprocessor system according to claim 1, wherein: A first data ID register for storing a first data ID of data accessed by the first CPU core;
A second data ID register for storing a second data ID of the data accessed by the second CPU core;
Data table storage means for storing a data table in which a plurality of data related in advance are associated with data IDs that at least partially match, and a data table storage means shared by the plurality of CPU cores. A control method,
A step of comparing the first data ID stored in the first data ID register with the second data ID stored in the second data ID register;
If the comparison result of the step indicates a match, one of the first CPU core and the second CPU core suspends access to the data table;
An exclusive control method for a multiprocessor system, comprising: An electronic control unit for a vehicle on which the multiprocessor system according to claim 1 is mounted.

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