JP4941222B2 - Sampling frequency monitoring method - Google Patents

Description

  The present invention relates to a digital protection relay device that protects a protection target by a plurality of relay functions, and more particularly to a voltage / current sampling frequency monitoring system.

  This type of digital protection relay device takes in a sampling of analog signal sampling and A / D conversion of voltage / current measurement and A / D conversion from a protection target that becomes a power system or a power device to each of a plurality of CPUs. Are configured to individually perform protection relay calculations.

  For example, in the main detection relay, the current and voltage of the transmission line are sampled and the protection operation is performed by the short-circuit distance relay element and the short-circuit overcurrent element. In the accident detection relay, the current of the transmission line is sampled and the current change width relay element is used. Locks the erroneous output from the protective relay when the main detection relay malfunctions.

  The main detection relay and the accident detection relay each sample the measurement analog signal captured by the transformer by the sample hold circuit, and sequentially convert the sample value to a digital value by the A / D converter, and this digital data string is stored in the CPU and the memory. Further, the calculation data of the protection calculation unit configured by software or the like is used.

  Here, since sampling in the main detection relay and the accident detection relay is important for reliable protection calculation to have sampling pulses of the same frequency, the sampling frequency is monitored for abnormalities ( For example, refer nonpatent literature 1).

In the frequency monitoring method of this patent document, as shown in FIG. 2, the main detection relay and the accident detection relay each divide a pulse signal from a reference oscillator such as a crystal oscillator provided on different substrates by a frequency dividing circuit. The sampling pulse signal is generated, and the deviation (ΔT) of the frequency (cycle) of the sampling pulse signal is monitored by time measurement (timer function) by the CPU having each relay.
Electric Cooperative Research, Volume 50, No. 1, Second Generation Digital Relay

  The digital protective relay device consisting of a main detection relay and an accident detection relay is configured with a reference oscillator (an oscillation circuit such as a crystal oscillator and a frequency divider) that generates sampling pulses for main detection and accident detection. As a result, the number of parts increases.

  Each CPU of the main detection relay and accident detection relay has a counter / timer function for determining the frequency of the sampling pulse and a monitoring function for determining normality / abnormality from the deviation between this frequency and the set frequency as software. It is necessary to mount it, which increases the load on the CPU.

  An object of the present invention is to provide a sampling frequency monitoring method that eliminates the need for a reference oscillator for generating a sampling pulse and further reduces the load on the CPU.

In order to solve the above-described problem, the present invention performs a protection operation for each of a plurality of CPUs by generating a sampling pulse by dividing the clock from each of the CPUs and individually acquiring sampling data. Separately, one CPU increments the counter at a sampling frequency every certain time (sampling pulse cycle) , and the other CPU reads the value of this counter every certain time (for example, 1 second) , so that the sampling frequency is within an allowable error range. By checking whether the sampling frequency is within or not, the presence or absence of an abnormality in the sampling frequency is monitored, and the following configuration is characteristic.

(1) Measurement of voltage / current from the object to be protected Sampling of analog signals and sampling data obtained by A / D conversion are taken into a plurality of CPUs, and a plurality of relay functions in which a plurality of CPUs individually perform protection relay calculations are mounted. In digital protection relay device,
The plurality of CPUs are provided with means for generating a sampling pulse by dividing the clock of each of the CPUs,
Among the plurality of CPUs, one CPU is provided with a means for incrementing a counter by 1 at a sampling frequency every predetermined time (sampling pulse cycle) ,
Of the plurality of CPUs, the other CPU includes means for reading the value of the counter at regular intervals and checking whether the sampling frequency is within an allowable error range.

As described above, according to the present invention, a plurality of CPUs divide each clock from the respective clocks to generate sampling pulses and individually take sampling data to perform protection operations separately. One CPU increments the counter at a certain frequency (sampling pulse cycle) at the sampling frequency, and the other CPU reads the value of this counter every certain time (for example, 1 second) to determine whether the sampling frequency is within the allowable error range. By checking whether or not there is an abnormality in the sampling frequency, the reference oscillator for generating the sampling pulse is unnecessary, and the load on the CPU can be reduced.

  FIG. 1 is a main part configuration diagram showing an embodiment of the present invention. The main detection CPU 1 is mounted as a protection calculation unit for the main detection relay, and performs a main detection relay calculation based on a voltage / current detection signal. The accident detection CPU 2 is mounted as a protection calculation unit of the accident detection relay, and performs an accident detection relay calculation based on a voltage / current detection signal. The CPUs 1 and 2 are coupled to a ROM, a RAM, a digital I / O, and the like, and are connected to an external analog I / O, a sampling hold circuit, and an A / D converter. Also, the sampling pulse is generated by dividing the clocks of both CPUs 1 and 2. This clock can be obtained by receiving time information from a digital oscillation circuit or a GPS satellite.

  The shared memory (CRAM) 3 is configured as a two-port memory that can be accessed by the main detection CPU 1 and the accident detection CPU 2.

  Both CPUs 1 and 2 perform mutual monitoring of the sampling frequency by writing / reading data to / from the shared memory 3. The shared memory 3 serving as the data writing / reading means is used for writing and reading counter data and flag data for monitoring the sampling frequency.

In the monitoring process of the sampling frequency between the CPUs 1 and 2, the main detection CPU 1 increments the counter at the sampling frequency every fixed time (sampling pulse cycle) , and the value of the counter is detected by the accident detection CPU 2 for a fixed time (for example, 1 second). ) To check whether the sampling frequency is abnormal or not by checking whether the sampling frequency is within an allowable error range. This process is as follows.

(S1) The main detection CPU 1 increments the counter data of the CRAM 3 by +1 at a sampling frequency every fixed time (sampling pulse cycle) .

  (S2) The accident detection CPU 2 reads the counter data in the CRAM 3 every second, checks that this data is within ± 5% of the sampling frequency, and clears the counter value to zero.

  As a result of the above processing, the accident detection CPU 2 outputs an alarm as “abnormal sampling frequency” of any CPU when the sampling frequency is outside the range of ± 5% for two times (2 seconds).

  The main detection CPU 1 sets a flag of the CRAM 3 at the time of initialization, and locks the abnormality detection operation by the accident detection relay CPU 2.

  Therefore, even if any sampling frequency of main detection CPU1 and accident detection CPU2 changes, it can detect.

  In addition, a reference oscillator (such as a crystal oscillator and a frequency dividing circuit) for generating a sampling pulse is not necessary. Further, in the monitoring process, the CPU 1 has a processing function of incrementing the counter data of the CRAM 3 every 1 Hz by the sampling frequency, and the accident detection CPU 2 reads the counter data of the CRAM 3 every second, and this data is ± 5% of the sampling frequency. It is sufficient to have a simple processing function for checking that the load is within the range, and the load on the CPUs 1 and 2 can be reduced.

  Although the embodiment shows a case where the CRAM 3 is used as a memory for monitoring the sampling frequency, a counter area equivalent to the CRAM 3 is allocated to the RAM of the CPU 1 or 2, and the result of +1 processing by the CPU 1 for this counter area is assigned to the CPU 2. The design can be changed as appropriate, such as a transfer configuration.

  Moreover, although the embodiment shows the case of a protective relay device having a main detection relay and an accident detection relay configuration, a plurality of relay functions are applied to a device having each CPU as a central part to obtain the same effect. be able to.

The principal part block diagram which shows embodiment of this invention. Functional explanatory drawing of the conventional frequency monitoring system.

Explanation of symbols

1 Main detection CPU
2 Accident detection CPU
3 Shared memory (CRAM)

Claims (1)

Voltage / current measurement from the object to be protected Digital type sampling with analog signal sampling and A / D converted sampling data loaded into multiple CPUs, and multiple CPUs individually performing protection relay calculations In the relay device,
The plurality of CPUs are provided with means for generating a sampling pulse by dividing the clock of each of the CPUs,
Among the plurality of CPUs, one CPU is provided with a means for incrementing a counter by 1 at a sampling frequency every predetermined time (sampling pulse cycle) ,
A sampling frequency monitoring system, comprising: a means for reading out the value of the counter at regular intervals and checking whether or not the sampling frequency is within an allowable error range among the plurality of CPUs.

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