JP4941738B2 - Bit alignment correction mechanism in ultra high-speed AD conversion - Google Patents

Description

  The present invention provides a transmission delay that differs for each quantization bit or an independent demultiplexer for each quantization bit when the output of the high-speed AD converter is delivered to a digital processing unit such as a digital data output unit or a digital signal processing unit. The present invention relates to signal processing for achieving bit alignment by correcting a shift between bits caused by serial / parallel conversion by a simple method.

  When a wide-band analog signal is converted from analog to digital by a high-speed AD converter that reaches a sampling frequency of several GHz and digital data output or digital signal processing (hereinafter referred to as digital processing) is performed, it is sampled inside the AD converter and is 2 bits. The data converted into the above digital value is output as a plurality of bits of data from the AD converter by an independent signal line for each bit, and passed to the subsequent digital processing unit. An example of such a configuration is shown in FIG. At this time, in order to correctly transmit and process the AD-converted data in the digital processing unit, each bit of data (MSB and LSB in the case of 2-bit quantization) constituting the sampled digital value is AD converted. Need to be sent to the digital processor in the same correct combination as when sampled by the instrument. Such a combination of quantized bits correctly aligned with respect to the sampling time is called bit alignment.

  In general, since multiple bits of data output from an AD converter are transmitted in synchronization with a single clock, if the digital processor captures the clock at an appropriate timing, the bit alignment is not impaired. However, in the case of a high-speed system in which the clock cycle is 1 nanosecond or less, the bit alignment is impaired because it is difficult to capture at the correct timing due to the difference in delay time in the transmission path of each bit. Sometimes.

  In general, the operation speed of the digital processing unit is not so high, and high-speed serial data output output from the AD converter cannot be processed as it is. Hereinafter, serial / parallel conversion is often performed in which the data is parallelized by DEMUX) and converted into a plurality of parallel data synchronized with a slower clock frequency. In this case, the multi-bit serial data output from the AD converter is input to each independent DEMUX. An example of such a configuration is shown in FIG.

In general, the DEMUX performs an operation of distributing input data to an n-bit output by a counter value inside the DEMUX, and the value of this counter is called a DEMUX phase. Since the DEMUX phase variation has the same effect as the delay variation with respect to the original serial data, the DEMUX phase of all DEMUXs to which multiple bits of serial data are input must completely match in order to maintain bit alignment correctly. Need to be. For this reason, a method is adopted in which a common reset signal is supplied to all the DEMUXs, and a plurality of DEMUXs are initialized at the same time, thereby matching the DEMUX phases. Some DEMUX elements having a reset input for use in such a method operate at a relatively high speed (see, for example, Non-Patent Document 1), but the operation speed is about 2 GHz. There are many DEMUXs that operate at higher speeds, for example, 8 GHz or higher (for example, see Non-Patent Document 2), but they only support 1-bit data, and reset input. Therefore, bit alignment cannot be realized by the above method.
Atmel AT84CS001 data sheet Vitesse VSC1236 catalog

A method of matching the DEMUX phases of a plurality of DEMUXs using a DEMUX element having no reset input has been devised (Patent Document 1). In this method, a time phase difference between n-divided clocks output from a plurality of 1: nDEMUXs is detected, and the phase of a clock signal applied to each DEMUX is changed so that the phase difference is a predetermined value or less. Thus, the DEMUX phases of all DEMUX can be matched. In this way, if a plurality of bits of quantized data is input to the input of the DEMUX in a state where the DEMUX phases coincide with each other, bit alignment of parallel data output from the DEMUX can be achieved.
Patent Publication 2006-324752

  When the serial output of the AD converter is directly input to the digital processing unit as shown in FIG. 2, in the case of a high-speed system in which the clock cycle, that is, the sampling cycle is 1 nanosecond or less, bit alignment is performed. In order to realize the above, it is necessary to control the timing in picosecond order which is a fraction of the sampling period in the circuit design, which is costly.

  In addition, when the serial output of the AD converter as shown in FIG. 3 is once converted into low-speed parallel data and input to the digital processing unit, in the conventional system using the reset input of the DEMUX, the AD converter When the sampling frequency is high, it is difficult to obtain a DEMUX element having a reset input, and it is difficult to achieve bit alignment.

  Even when a DEMUX element having a reset input can be used, it is necessary to input the reset signal at a sufficiently high speed with respect to the input clock cycle of the DEMUX, and when the AD converter sampling frequency is high, a reset signal is generated. In addition, the distribution is expensive and difficult to realize.

  According to the method shown in Patent Document 1, it is possible to synchronize the phases of a plurality of DEMUXs with a DEMUX that does not have a reset input, but in order to adopt this method, the input data is independent of the DEMUX. Although it is necessary to vary only the phase of the clock, a generally available DEMUX element for optical communication (for example, Non-Patent Document 2) having an operation speed of several GHz can generate a clock from timing information superimposed on input data itself. This is a method for generating and operating the internal DEMUX unit and does not have an independent clock input, so this method cannot be adopted.

  Therefore, the problem to be solved by the present invention is that the bit alignment in the case of digitally processing a plurality of bits of quantized data output from the AD converter is a high-speed system having a time system that is less than a fraction of the sampling period. It is to be realized without using a timing control technique or a high-speed DEMUX element having a reset circuit.

  The present invention achieves bit alignment by analyzing and evaluating the occurrence probability of data output from an AD converter. Measures and aligns the bit distribution of small amplitude random noise signals that occur naturally when there is no input, so it does not require any high-speed timing control technology or additional control units such as a DEMUX reset circuit. The feature is that the device can be realized.

  Normally, when a complete DC potential corresponding to a threshold value at which the output digital value is just switched is input to the analog input of the AD converter, the digital value that is positioned above and below the threshold value is randomly output. This is because the analog input value is in an indistinguishable region (dead zone) of the AD converter, and the AD converter cannot uniquely determine the output digital value.

  When the output of the AD converter is an offset binary code, when the center potential, that is, the potential corresponding to the dead zone of the threshold at which the sign bit of the output digital value is just switched, is input to the input of the AD converter, the output digital value is If the most significant bit is a sign bit, there are only two values located above and below the threshold at which the sign bit is switched, that is, only the value of the minimum amplitude. For example, when the number of quantization bits is 2 bits, “01” and “10” It becomes only. In general, the input of a wideband AD converter is biased to the center potential, and the input signal is connected to the AD converter by AC coupling. Therefore, such an output can be obtained simply by short-circuiting the input signal to 0V. be able to.

  In the digital value sampled by the AD converter, an index indicating how often the digital value included in a certain time is distributed with respect to each value from the minimum value to the maximum value is called a bit distribution. The bit distribution as a result of AD conversion of the test signal as described above is distributed only to “01” and “10” if bit alignment is achieved, and other values, that is, “00” and “11” are All become 0%. As an example, when a constant potential is input to the dead zone between “01” and “10” as shown in FIG. 4, the MSB in the digital value output from the AD converter is achieved if bit alignment is achieved. The combination of LSB and LSB is as shown in FIG. In FIG. 5, the bit distribution in the section A is 0% for “00”, 50% for “01”, 50% for “10”, and 0% for “11”. What is important here is that the bit distribution of “00” and “11” is 0%.

  Here, when the bit alignment is broken due to a delay difference until the output of the AD converter is introduced to the bit distribution measuring unit or a DEMUX phase mismatch (DEMUX phase shift), the measured bit distribution is “01” and A value other than “10” appears. As an example, FIG. 6 shows a combination of LSB and MSB when LSB data is shifted forward by one sample from the original timing. In FIG. 6, the bit distribution in the section A is “00” which is 20%, “01” is 30%, “10” is 20%, “11” is 30%, and “00” which should not appear originally. Bits are distributed in “11”. By utilizing this property, it is possible to determine whether or not bit alignment is achieved by measuring the bit distribution of the output data of the AD converter.

  Here, before the bit distribution measurement unit, a delay correction unit that adds a delay in units of bits for each quantized bit is provided, and the amount of delay is assumed between the AD converter and the bit distribution measurement unit. When the bit distribution is measured while changing within the range of the delay difference and the DEMUX phase shift, “00” is obtained only when the delay amount added by the delay correction unit matches the delay amount due to the delay difference and the DEMUX phase shift. , “11” indicates a singular point where the bit distribution is 0%, and in other cases, each bit distribution indicates a uniform value. Therefore, bit alignment can be achieved by searching for a delay correction value whose bit distribution shows the former value.

  Therefore, the AD converter output is introduced into the digital processing unit without correcting the delay difference between the quantized bits and the DEMUX phase mismatch, and delay correction and bit distribution measurement are performed inside the digital processing unit. By performing the delay correction so that the bit distribution becomes a singular point by the procedure as described above, and introducing the result into the original digital processing unit as it is, correct digital processing can be performed with bit alignment achieved. It becomes possible. In general, the output of a high-speed AD converter is introduced into a device such as a high-speed FPGA as serial data, or is serially parallel-converted by an external or internal DEMUX such as an FPGA and then configured inside the FPGA or the like. The necessary digital processing is performed in the digital processing unit. For this reason, if the delay correction unit and the bit distribution measurement unit are configured inside the same FPGA as the digital processing unit, or if the delay correction and the bit distribution measurement are performed after sufficiently slowing down via the DEMUX, Since the data transmission to the original digital processing unit can ensure the clock-synchronized transfer, the bit alignment due to the delay difference between the bits and the DEMUX phase shift is not impaired.

  Although the case of 2-bit quantization has been described above, the same applies to the case of the number of quantization bits of 3 bits or more. In the case of 3 bits or more, the output obtained when a potential corresponding to the dead zone of the central potential is input to the input of the AD converter as described in item 14 is “0111...” And “1000. It is limited, and other values are not output, but if the bit alignment is broken, values other than the above appear. Therefore, the bit alignment is achieved by searching for a singular point where the values other than “0111...” And “1000. It becomes possible.

  So far, the case where the input of the AD converter uses 0V as the center voltage has been described. However, even when the input center voltage of the AD converter is not 0V, the same applies if a DC voltage corresponding to the threshold of the center voltage is input. For this purpose, a simple constant voltage generator may be provided at the input unit.

  The same effect can be obtained by inputting random noise as input without using the dead zone of the AD converter. If a small amplitude noise that crosses the threshold of the center voltage of the AD converter and does not exceed the range of the upper and lower quantization levels is input, the minimum same as that described in the item 14 from the output of the AD converter A random output of amplitude is obtained. If the amplitude of the noise is larger than the above, the output will be distributed not only at the minimum amplitude value but also at a larger amplitude value, but noise generally decreases as the amplitude increases, so the bit appears. If the alignment is correctly achieved, the bit distribution at values other than the minimum amplitude value becomes relatively small. On the other hand, when the bit alignment is not achieved, the output bit distribution of the AD converter is almost uniform. Therefore, the bit distribution other than the minimum amplitude value is minimized while correcting the delay amount described in the item 17. Bit alignment can be achieved by searching for a singular point of the bit distribution that is relatively smaller than the bit distribution of the amplitude value.

  In a state where bit alignment is achieved by the configuration and procedure described so far, correct digital processing can be realized by switching the input of the AD converter to an input signal to be originally processed.

  As is clear from the above description, a delay correction unit and a bit distribution measurement unit are arranged between the AD converter and the digital processing unit, and the bit distribution is measured, so that the sampling period of the AD converter is more accurate. Bit alignment can be achieved without performing timing control or DEMUX reset operation, and correct digital processing can be realized.

  By eliminating the DEMUX reset operation, it is possible to use a DEMUX element for optical communication that does not have a generally available reset terminal, and a system with a processing speed of several GHz or more can be obtained at low cost. Can be realized. Even when a DEMUX element having a reset terminal is used, precise timing control for generating a reset signal is not required, so that the system can be realized at low cost.

  When the distance between the AD converter and the digital processing unit is remote, the output of the AD converter is transmitted to the digital processing unit by optical transmission means or the like. In the conventional method, it is necessary to correctly place the bit alignment of the output data of the AD converter on the transmission line, and further, a mechanism for preventing the bit alignment from being destroyed in the transmission line is required. In this case, it is possible to correct the delay difference of the transmission path when the multi-bit output of the AD converter is transmitted through the independent transmission path as serial data and finally reaches the digital processing unit. It is possible to simplify the configuration of the AD converter and the intermediate transmission path.

  Hereinafter, an embodiment of the present invention will be described with reference to FIG.

  In FIG. 1, when the analog input changeover switch 103 is connected to the signal ground 102 side and is set to 0 V, the input of the AD converter 201 connected via the AC coupling 104 becomes a biased center potential, which is exactly the positive side. Enter the indistinguishable region (dead zone) at the threshold of the negative boundary. At this time, the AD converter outputs a random digital value having the same minimum amplitude as that described in item 14. In this figure, since an example of 2-bit quantization is shown, the MSB data 21 indicating the most significant bit and the LSB data 22 indicating the least significant bit are output from the AD converter as separate signal lines, respectively. .

  The MSB data and the LSB data are respectively introduced into the MSB DEMUX 301 and the LSB DEMUX 302, and serial-parallel converted to 1: n. Since these DEMUX are not reset at the same time, the bit alignment of the parallel converted MSB data 31 and the parallel converted LSB data 32 is generally not achieved.

  The MSB data 31 and the LSB data 32 are introduced into the MSB delay correction unit 401 and the LSB delay correction unit 402, respectively. In the first stage, the relative delay amount between the MSB delay correction unit and the LSB delay correction unit is set to zero.

  The MSB data 41 and LSB data 42 output from the delay correction unit are introduced into the bit distribution measurement unit 501, and each bit distribution of “00”, “01”, “10”, and “11” is set at a constant time interval. It is measured.

  The bit distribution measurement result 51 is read by the delay amount control unit 601, and the values “00” and “11” are 0%, and the sum of the bit distributions “01” and “10” is 100%. If not, it is determined that bit alignment is not achieved, and the delay amounts 61 and 62 of the delay correction unit are controlled so that the relative delay between the MSB and LSB becomes +1 bit, and the bit distribution is measured again. To do.

  The procedure of the item 31 is repeated to search for a delay amount at which the bit distribution becomes a singular point shown in the item 31. If the singular point of the bit distribution is not found even if the relative delay amount reaches the assumed limit (for example, 16 bits when using 1:16 DEMUX), the relative delay amount is changed to-and the same procedure is performed. repeat.

  If the bit distribution becomes a singular point as a result of the search, the relative delay amount is fixed, and the input selector switch 103 is switched to the analog signal input terminal 101 side.

  In this state, since the bit alignment of the 2-bit data (MSB and LSB) input to the digital processing unit 701 has been achieved, the original digital processing can be started.

  It is a block diagram of the analog-digital converter which implement | achieves bit alignment, without performing DEMUX reset by the method of this invention.   It is a block diagram of the analog-digital converter which introduces the output of AD converter into a digital processing part with the conventional method with serial data.   FIG. 10 is a block diagram of an analog-digital conversion apparatus that serial-parallel converts an output of an AD converter by a DEMUX element having a reset input and introduces the digital processing unit by a conventional technique.   An example of a dead zone of an AD converter and a digital value output from the AD converter when a constant potential is input thereto.   The bit distribution of MSB and LSB when the bit alignment is achieved in the output of the AD converter as shown in FIG. 4 is shown.   The bit distribution of MSB and LSB when the bit alignment is not achieved in the output of the AD converter as shown in FIG. 4 is shown.

Explanation of symbols

11 Analog signal to be processed 12 Test signal 13 DC signal of 0V 21 Most significant bit (MSB) of A / D converted digital value
22 Least significant bit (LSB) of AD converted digital value
31 Parallel MSB data after serial / parallel conversion 32 Parallel LSB data after serial / parallel conversion 41 Parallel MSB data after delay correction 42 Parallel LSB data after delay correction 51 Bit distribution measurement result 61 Delay correction amount for MSB 62 Delay correction for LSB Quantity 81 DEMUX reset signal 101 Analog signal input terminal 102 Signal ground 103 Analog input changeover switch 104 AC coupling 201 AD converter 301 with 2-bit quantization and offset binary output DEMUX for MSB
302 DEMUX for LSB
401 MSB delay correction unit 402 LSB delay correction unit 501 bit distribution measurement unit 601 delay amount control unit 701 digital processing unit 801 DEMUX reset signal generation unit

Claims (4)

In an analog-to-digital conversion apparatus that performs analog-to-digital conversion of an analog signal with a quantization bit number of 2 bits or more and outputs the digital data
Delay correction means for digitally delaying the output of the AD converter independently for each bit;
Means for measuring the bit distribution of the delay-corrected data;
An analog-to-digital converter provided with a control means for controlling the amount of delay correction based on the bit distribution measurement result.   The output of the AD converter is serial-parallel converted by a demultiplexer provided for each bit and then transmitted to the delay correction unit, and the delay correction unit and the subsequent steps are performed on the data parallelized by the demultiplexer. The analog-digital conversion apparatus according to claim 1.   3. The analog-to-digital conversion apparatus according to claim 1, wherein the AD converter and the data output unit are connected by a transmission means that is independent of each bit and has an arbitrary fixed delay amount. .   In a digital signal processing apparatus that inputs an analog signal, performs analog-to-digital conversion inside, and performs signal processing in a digital manner, the AD converter and the digital signal processing section are connected to each other as claimed in claim 1, claim 2, Alternatively, a digital signal processing apparatus employing the method of claim 3.

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