JP4944741B2 - Semiconductor integrated circuit device having diode element suppressing parasitic effect - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device incorporating a spark killer diode suitable for output transistor protection.

  For example, in a three-phase motor driver, transistors (Tr1-Tr2, Tr3-Tr4, Tr5-Tr6) connected in series between the DC power supplies VCC and GND are connected in parallel as shown in FIG. Then, a circuit configuration in which an output terminal taken out between Tr1-Tr2, Tr3-Tr4 and Tr5-Tr6 is connected to the motor M is adopted.

  Thus, when the load is an inductive load, an electromotive force in the forward / reverse direction is generated due to rotation / stop of the motor. Conventionally, a protective diode is connected between the collector and emitter of an IC-connected series connection transistor. The diode 4 is turned on when the output terminal is lower than the GND potential or higher than the VCC potential by the reverse electromotive force. As a result, the electromotive force is released to a fixed potential, and the inside of the IC including the transistors connected in series is protected. In particular, when a large current of several A is passed through the diode 4, the diode 4 is configured using individual components.

  Here, from the user side, there is also a demand for the diode 4 to be integrated into an IC in order to reduce the number of parts of the device. However, when diodes that carry a large current of several A are integrated, there is a risk that parasitic current may flow due to parasitic transistor effects that inevitably occur in the integrated circuit. The parasitic current flows as a reactive current, and in the worst case, there is a risk of latch-up.

  In view of this, a structure described in, for example, Japanese Patent Laid-Open No. 6-100459 has been proposed as a structure for preventing a parasitic current.

As shown in FIG. 15, an N + type buried layer 3 is provided between a P type semiconductor substrate 1 and an N type semiconductor substrate 2. A P + type isolation region 4 is diffused from the surface of the semiconductor layer 2 to the semiconductor substrate 1 so as to surround the buried layer 3 to form one island 5. A P + type buried layer 6 is formed on the buried layer 3 so as to partially overlap. An N + type lead-out region 7 that surrounds the P + type buried layer 6 and reaches the N + type buried layer 3 from the surface of the semiconductor layer 2 is provided. An N + type diffusion region 8 is formed in the enclosed region. Further, in a region surrounded by the derivation region 7, a P + type derivation region 9 that surrounds the diffusion region 8 and reaches the P + type buried layer 6 from the semiconductor layer 2 is provided. Further, a cathode electrode 10 is provided in the diffusion region 8, and an anode electrode 11 is provided in the P + type lead-out region 9, and this electrode is electrically connected to the N + type lead-out region 7.

That is, the P + type lead-out region 9 and the P + type buried layer 6 serve as an anode region, and the N type semiconductor region surrounded by the N + type diffusion region 8 and the lead-out region 9 serves as a cathode region, thereby forming a diode.
In such a diode element, a PNP-type parasitic transistor Tr2 is generated in which the N + type buried layer 3 is the base, the P + type buried layer 6 is the emitter, and the P type semiconductor substrate 1 or the P + type isolation region 4 is the collector. . However, since the base and emitter of the parasitic transistor Tr2 have the same potential due to the connection of the anode electrode, it is possible to prevent the parasitic PNP transistor Tr2 from being turned on.
Japanese Patent Laid-Open No. 6-100459

  As described above, in the conventional semiconductor integrated circuit device, as shown in FIG. 14, when the load is an inductive load, an electromotive force in the forward / reverse direction is generated along with the rotation / stop of the motor. Therefore, a protective diode is connected between the collector and emitter of the series-connected transistor that is made into an IC. Then, when the output terminal is lower than the GND potential or higher than the VCC potential by the reverse electromotive force, the diode 4 is turned on to release the electromotive force to the fixed potential. And the inside of the IC including the transistors connected in series was protected. In particular, when a large current of several A is passed through the diode 4, the diode 4 is configured using individual components.

  Then, in order to reduce the number of parts of the device, the diode 4 that integrates a large current of several A is integrated in response to a request to make the diode 4 an IC. However, due to problems such as parasitic current flowing due to parasitic transistor effects that inevitably occur in the integrated circuit and reactive current flowing, a structure in which a diode is incorporated in the IC as shown in FIG.

  However, as described above, the diode 4 could be incorporated into the IC. However, as shown in FIG. 15, the diode 4 may be turned off, that is, the cathode electrode 10 may have a higher voltage than the anode electrode 11. . At this time, a withstand voltage is required to cope with the destruction of the semiconductor element due to the breakdown current at the PN junction surface of the parasitic transistor TR1. In other words, in the conventional structure, the width of the P + type buried layer 6 as the base region of the parasitic transistor TR1 is narrow, it is difficult to suppress the current amplification factor hfe, and the breakdown voltage of the parasitic transistor TR1 cannot be secured. was there.

  Further, as shown in FIG. 15, in the conventional structure, the parasitic transistor TR2 is configured to have the same potential between the base and the emitter in order to suppress the ON operation, but leakage current flows through the substrate. End up. Therefore, there is a problem that a desired forward current cannot be obtained due to a leakage current due to the parasitic transistor TR2.

The present invention has been made in view of the above-described conventional problems.
A semiconductor substrate of one conductivity type;
A reverse conductivity type semiconductor layer formed on the surface of the semiconductor substrate;
An isolation region of one conductivity type that arrives at the semiconductor substrate from the surface of the semiconductor layer and forms an island region of a reverse conductivity type;
A reverse conductivity type first buried layer formed between the semiconductor substrate and the semiconductor layer in the island region;
It is formed between the semiconductor substrate and the semiconductor layer so as to overlap with the first buried layer and to be derived from at least the upper direction of the first buried layer and from above the first buried layer. A second buried layer of one conductivity type,
The semiconductor layer as a cathode, a cathode contact region of a reverse conductivity type formed on the surface of the semiconductor layer,
A cathode electrode connected to the cathode contact region ;
A diffusion region of one conductivity type formed so as to reach the second buried layer from the surface of the semiconductor layer and surround the cathode contact region; an anode region comprising the second buried layer;
A reverse conductivity type diffusion region formed so as to reach the first buried layer from the surface of the semiconductor layer and surround the one conductivity type diffusion region;
A one-conductive type parasitic resistance adjustment region formed from the one-conductive type diffusion region formed from the surface of the semiconductor layer and reaching the second buried layer;
The problem is solved by an anode electrode that contacts the parasitic resistance adjustment region and the reverse conductivity type diffusion region reaching the first buried layer.

  The operation of the parasitic PNP transistor when the diode element is ON can be reliably suppressed, and the leakage current to the substrate can be significantly suppressed.

  The semiconductor integrated circuit device of the present invention will be described in detail below with reference to FIGS. FIG. 1 illustrates the first embodiment of the present embodiment, and FIG. 4 illustrates the second embodiment of the present embodiment.

First Embodiment FIG. 1A is a cross-sectional view showing a structure of a semiconductor integrated circuit device of the present invention, and FIG. 1B is a circuit diagram of a semiconductor integrated circuit device of the present invention. In this embodiment, only the region where the diode element of the semiconductor integrated circuit device is formed is shown and described, but in the other region, a vertical PNP transistor element, an NPN transistor element, and the like are formed.

  As shown in FIG. 1A, a first epitaxial layer 22 having a thickness of 2 to 10 μm is formed on a P− type single crystal silicon substrate 21, and a thickness of 8 μm is formed on the first epitaxial layer 22. A second epitaxial layer 23 of 10 μm to 10 μm is formed. The first and second epitaxial layers 22 and 23 are each formed so that the total thickness of the two layers is about 8 to 16 μm. In the substrate 21 and the first and second epitaxial layers 22 and 23, an island region for forming a diode element is formed by a P + type isolation region 24 penetrating them. As described above, only the diode element is illustrated in this embodiment, but in addition, an island region for forming a vertical PNP transistor element, an NPN transistor element, and the like is formed by the P + type isolation region 24. .

  The isolation region 24 includes a first isolation region 25 diffused in the vertical direction from the surface of the substrate 21, a second isolation region 26 diffused in the vertical direction from the boundary between the first and second epitaxial layers 22, 23, 2 comprises a third isolation region 27 formed from the surface of the epitaxial layer 23. The first and second epitaxial layers 22 and 23 are separated in an island shape by connecting the three.

  Below, the diode element which is this invention is demonstrated. As illustrated, an N + type first buried layer 28 and a P + type first buried layer 29 are formed so as to overlap each other between the substrate 21 and the first epitaxial layer 22. A P + -type second buried layer 31 and an N + -type second buried layer 30 are formed at the boundary between the first and second epitaxial layers 22 and 23. The N + type second buried layer 30 and the P + type second buried layer 31 overlap with the N + type first buried layer 28 and the P + type first buried layer 29, respectively, in a part thereof. Yes. Further, a P + type first diffusion region 34 reaching the P + type second buried layer 31 from the surface of the second epitaxial layer 23 is formed. The N− type first and second epitaxial layers 22 and 23 sandwiched between the P + type regions 31 and 34 are formed as cathode regions to form a PN junction diode. At this time, an N + type first diffusion region 38 reaching the N + type second buried layer 30 from the surface of the second epitaxial layer 23 is formed.

In the present invention, the P + type second diffusion region 32 is formed from the surface of the second epitaxial layer 23, and a part of the P + type second diffusion region 32 is replaced with the P + type first diffusion region 34. Superimpose. Then, a contact hole 38 for connecting to the anode electrode 39 is formed in the insulating layer 36 formed on the surface of the second epitaxial layer 23. At this time, the contact hole 38 is formed immediately above the P + type second diffusion region 32 in order to connect the P + type second diffusion region 32 and the anode electrode 39. The N + type first diffusion region 33 and the P + type second diffusion region 32 are short-circuited via the anode electrode 39. Although the details will be described later, the base and collector of the parasitic NPN transistor TR1 and the base and emitter of the parasitic PNP transistor TR2 are short-circuited. Although details will be described later, the P + type second diffusion region 32 is formed for the purpose of making the resistance value on the emitter side of the parasitic PNP transistor TR2 higher than the resistance value on the base side. Therefore, the position of the contact hole 38 can be arbitrarily changed depending on a desired resistance value.

  In the present embodiment, an N + type first buried layer 28 and a P + type first buried layer 29 are formed so as to overlap each other between the substrate 21 and the first epitaxial layer 22. For example, the N + type first buried layer 28 is formed using antimony (Sb), and the P + type first buried layer 29 is formed using boron (B). Therefore, a structure in which the P + type first buried layer 29 is formed above and below the N + type first buried layer 28 as shown in FIG. 1 due to the difference in impurity diffusion rate and impurity use concentration. Have. As described above, the P + type first and second buried layers 29 and 31 and the P + type first and second diffusion regions 34 and 32 are used as anode regions, and the first and second epitaxial layers 22 and 23 are used. A PN junction diode having a cathode region is formed. An N + type second diffusion region 35 is formed as a cathode lead-out region in the second epitaxial layer 23 formed as the cathode region. The N + type diffusion region 35 and the P + type first buried layer 29 are formed so as to be separated in the depth direction.

  With the structure of the present invention described above, when the diode element is in an OFF state, that is, on the PN junction surface formed by the P + type first buried layer 29 and the N− type first epitaxial layer 22. A reverse bias may be applied. In this case, a depletion layer forming region can be greatly obtained in the N-type region composed of the first and second epitaxial layers 22 and 23. By securing a breakdown voltage with a depletion layer formed in the N-type region, it is possible to suppress internal element breakdown due to breakdown current.

  The surface of the second epitaxial layer 23 is covered with an insulating layer 36, and various aluminum electrodes are provided through contact holes 37, 38, and 40 formed in the insulating layer 36. Although not shown, the substrate 21 is grounded for bonding separation.

  As shown in FIGS. 1A and 1B, in the structure of the present embodiment, when the diode element is turned on, a parasitic NPN transistor TR1, a parasitic PNP transistor TR2, and parasitic resistors R1 and R2 are mainly formed. . The operation of the parasitic transistor that affects the leakage current to the substrate 24 when the diode element is ON will be described below.

  First, the parasitic NPN transistor TR1 is configured with the N + type first buried layer 28 as a collector, the P + type first buried layer 29 as a base, and the first and second epitaxial layers 22 and 23 as emitters. . A parasitic resistor R1 including P + type first and second buried layers 29 and 31, and P + type first and second diffusion regions 34 and 32 is formed at the base of the parasitic NPN transistor TR1. . On the other hand, a parasitic resistance R2 including N + type first and second buried layers 28 and 30 and an N type first diffusion region 33 is formed at the collector of the parasitic NPN transistor TR1. As shown in the figure, the present invention is characterized in that P + type first and second diffusion regions 34 and 32 are formed in the second epitaxial layer 23. Then, both are formed so as to overlap each other, and are connected to the anode electrode 39 on the P + type second diffusion region 32.

  As a result, the resistance value of the parasitic resistance R1 can be increased by the amount corresponding to the region of the P + type second diffusion region 32. The resistance value of the parasitic resistance R1 can be arbitrarily changed depending on the intended use and can be adjusted by the formation region of the P + type second diffusion region 32 or the formation position of the contact hole 38. In this embodiment, the P + type second diffusion region 32 is formed so that the resistance value of the parasitic resistance R1 is increased by about 1 to 3Ω. That is, the resistance value of the parasitic resistance R1 is larger than the resistance value of the parasitic resistance R2. As a result, the parasitic NPN transistor TR1 is connected to the same anode electrode 39 and short-circuited between the base and the collector, but the collector potential can be maintained higher than the base potential. Since the parasitic NPN transistor TR1 allows a current to flow in the same direction as the forward current (If) of the diode element, the characteristics of the forward current (If) of the diode element can be improved.

  On the other hand, the parasitic PNP transistor TR2 has a P− type substrate 21 as a collector, an N + type first buried layer 28 as a base, and a P + type first buried layer 29 as an emitter. The parasitic PNP transistor TR2 has an emitter formed of a parasitic resistance R1 including P + type first and second buried layers 29 and 31, and P + type first and second diffusion regions 34 and 32. . On the other hand, a parasitic resistance R2 including N + type first and second buried layers 28 and 30 and an N type first diffusion region 33 is formed at the base of the parasitic PNP transistor TR2. As described above, the present invention is characterized in that the P + type second diffusion region 32 is formed, and the resistance value of the parasitic resistance R1 is larger than the resistance value of the parasitic resistance R2.

  As a result, the parasitic PNP transistor TR2 is connected to the same anode electrode 39 and short-circuited between the base and the emitter, but the base potential can be maintained higher than the emitter potential. As a result, in the parasitic PNP transistor TR2, the base potential can be reliably maintained higher than the emitter potential by the P + -type second diffusion region 32. Then, the ON operation of the parasitic PNP transistor TR2 can be prevented, and the leakage current to the substrate 21 can be suppressed as much as possible through the parasitic PNP transistor TR2.

  FIG. 2 is a relationship diagram between the forward current (If) of the diode element and the leakage current (Isub) to the substrate 21 when the P + type second diffusion region 32 is formed and not formed. Specifically, the line indicated by the alternate long and short dash line does not form the P + type second diffusion region 32, and the P + type first diffusion region 34 and the N + type first diffusion region 33 are made the same anode. This is a case where the electrodes 39 are connected. On the other hand, the solid line shows the P + type second diffusion region 32, and the P + type second diffusion region 32 and the N + type first diffusion region 33 are connected by the same anode electrode 39. Is the case. As shown in the figure, when obtaining the forward current (If) of the diode element, for example, 2.5 (A), if the P + type second diffusion region 32 is not formed, the leakage current (Isub) to the substrate 21 is About 300 × 10−3 (A) occurs. On the other hand, when the P + type second diffusion region 32 is formed, a leakage current (Isub) to the substrate 21 is generated about 50 × 10 −3 (A). It has been proved by experiments that the difference in leakage current (Isub) to the substrate 21 increases as the forward current (If) of the diode element increases. That is, by forming the P + type second diffusion region 32 and making the resistance value of the parasitic resistance R1 larger than the resistance value of the parasitic resistance R2, the leakage current (Isub) to the substrate 21 is reduced, and the diode element The forward current (If) can be increased.

  Here, the structure shown in FIG. 3 will be described. FIG. 3 shows the case where the P + type second diffusion region 32 according to the present invention is not formed and polysilicon 42 is formed on the surface of the second epitaxial layer 22 where the P + type first diffusion region 34 is formed. It is sectional drawing. As shown in the figure, by forming polysilicon 42 on the surface of the second epitaxial layer 22 and using the polysilicon 42 as a resistor, the same effect as the structure of FIG. 1A can be obtained. In this case, the resistance value of the polysilicon 42 can be freely changed by the amount of impurities introduced into the polysilicon 42, and can be handled in the same manner as the P + type second diffusion region 32. Other structures and effects are the same as those of the structure of FIG. 1A described above, and the description is omitted here with reference to the above description.

  Further, as shown in FIG. 5A, an N + type well region 43 is formed so as to overlap and surround the N + type second diffusion region 35 of the diode element shown in FIG. You can also With this structure, the N + type well region 40 reduces the parasitic resistance in the second epitaxial layer 23 when the diode element is ON. That is, in the PN junction of the diode element according to the present invention, the resistance value of the N-type region composed of the first and second epitaxial layers 22 and 23 can be lowered. As a result, the forward voltage (VBEF) of the diode element can be reduced, and the forward current (If) of the diode element can be improved. However, by forming the N + type well region 43, the depletion layer forming region extending from the PN junction surface is reduced, and the breakdown voltage of the diode element at OFF is lowered. Therefore, whether or not the N + type well region 43 is to be formed is determined according to the use application in which importance is attached to the breakdown voltage characteristic or the forward current (If) characteristic.

  In addition, various modifications can be made without departing from the scope of the present invention.

Second Embodiment FIG. 4A is a cross-sectional view showing a structure of a semiconductor integrated circuit device of the present invention, and FIG. 4B is a circuit diagram of a semiconductor integrated circuit device of the present invention. In the present embodiment, only the region where the diode element of the semiconductor integrated circuit device is formed is illustrated and described as in the first embodiment. However, in other regions, vertical PNP transistor elements, NPN Transistor elements and the like are formed.

  As shown in FIG. 4A, a first epitaxial layer 52 having a thickness of 2 to 10 μm is formed on a P− type single crystal silicon substrate 51, and a thickness of 8 is formed on the first epitaxial layer 52. A second epitaxial layer 53 of 10 μm to 10 μm is formed. The first and second epitaxial layers 52 and 53 are each formed so that the total thickness of the two layers is about 8 to 16 μm. In the substrate 51 and the first and second epitaxial layers 52 and 53, an island region for forming a diode element is formed by a P + type isolation region 54 penetrating them. As described above, only the diode element is illustrated in the present embodiment, but in addition, an island region for forming a vertical PNP transistor element, an NPN transistor element, and the like is formed by the P + type isolation region 54. .

  The isolation region 54 is diffused in the vertical direction from the boundary between the first and second epitaxial layers 22 and 23, and the downward direction is formed by the first isolation region 55 reaching the substrate 51 and the surface of the second epitaxial layer 53. 2 separation regions 56. Then, the first and second epitaxial layers 52 and 53 are separated into islands by connecting the both. With this structure, in the second embodiment, the number of masks can be reduced by one compared to the first embodiment.

  Below, the diode element which is this invention is demonstrated. As shown, an N + type first buried layer 57 is formed between the substrate 51 and the first epitaxial layer 52. In the N + type first buried layer 57, a P + type buried layer 58 formed from the boundary portion between the first and second epitaxial layers 52 and 53 is partially overlapped. An N + type second buried layer 59 is formed at the boundary between the first and second epitaxial layers 52 and 53. The N + type second buried layer 59 overlaps with the N + type first buried layer 59 at a part thereof. Further, a P + type first diffusion region 60 reaching the P + type buried layer 58 from the surface of the second epitaxial layer 53 is formed. The N− type second epitaxial layer 53 sandwiched between the P + type regions 58 and 60 is formed as a cathode region, thereby forming a PN junction diode. At this time, an N + type first diffusion region 61 reaching the N + type second buried layer 59 from the surface of the second epitaxial layer 53 is formed.

  In the present invention, the P + type second diffusion region 62 is formed from the surface of the second epitaxial layer 53, and a part of the P + type second diffusion region 62 is replaced with the P + type first diffusion region 60. Superimpose. Then, a contact hole 66 for connecting to the anode electrode 68 is formed in the insulating layer 64 formed on the surface of the second epitaxial layer 23. At this time, the contact hole 66 is formed immediately above the P + type second diffusion region 62 in order to connect the P + type second diffusion region 62 and the anode electrode 68. The N + type first diffusion region 61 and the P + type second diffusion region 62 are short-circuited via the anode electrode 68. As a result, although details will be described later, the base and collector of the parasitic NPN transistor TR1 and the base and emitter of the parasitic PNP transistor TR2 are short-circuited. Although details will be described later, the P + type second diffusion region 62 is formed for the purpose of making the resistance value on the emitter side of the parasitic PNP transistor TR2 higher than the resistance value on the base side. Therefore, the position of the contact hole 66 can be arbitrarily changed depending on a desired resistance value.

  Then, as described above, the P + type buried layer 58, the P + type first and second diffusion regions 60 and 62 as the anode region, and the PN junction diode with the second epitaxial layer 53 as the cathode region are formed. Yes. Further, an N + type second diffusion region 63 is formed as a cathode lead-out region in the second epitaxial layer 53 formed as the cathode region. The N + type second diffusion region 63 and the P + type buried layer 58 are formed so as to be separated in the depth direction.

  According to the structure of the present invention described above, when the diode element is in the OFF state, that is, the reverse bias is applied to the PN junction surface formed by the P + type buried layer 58 and the N− type second epitaxial layer 53. May be applied. In this case, a depletion layer forming region can be obtained in the N-type region composed of the second epitaxial layer 23 and the P-type region composed of the P + type buried layer 58. By securing a breakdown voltage with the depletion layers formed in the N-type region and the P-type region, it is possible to suppress internal element breakdown due to breakdown current.

  Note that the surface of the second epitaxial layer 53 is covered with an insulating layer 64, and various Al electrodes are provided through contact holes 65, 66, 67 formed in the insulating layer 64. Although not shown, the substrate 51 is grounded for bonding separation.

In the present embodiment, the parasitic NPN transistor TR3 is configured by using the first epitaxial layer 53 as an emitter, the P + type buried layer 58 as a base, and the N + type first buried layer 57 as a collector. The parasitic PNP transistor TR4 includes a P + type buried layer 58 as an emitter, an N + type first buried layer 57 as a base, and a P− type substrate 51 as a collector. The parasitic resistance R3 is composed of P + type first and second diffusion regions 60 and 62 and a P + type buried layer 58. The parasitic resistance R4 includes N-type first and second buried layers 57 and 59 and an N-type first diffusion region 61. The above four relationships are as shown in the circuit diagram of FIG. 4B, which is the same as the circuit in the first embodiment shown in FIG. As in the first embodiment, the P + type second diffusion region 62 is formed also in the second embodiment, and the resistance value of the parasitic resistance R1 is made larger than the resistance value of the parasitic resistance R2. There is a feature. For this reason, the effects described in the first embodiment can be obtained in the same manner in the second embodiment, so the description in the first embodiment is referred to and the description is omitted here.

Also in this embodiment, as shown in FIG. 3 in the first embodiment, the P + type second diffusion region 62 can be changed to a resistor made of polysilicon. In this case, the same effect can be obtained. As shown in FIG. 5B, also in the present embodiment, the N + type well region 70 is used depending on the usage purpose, which emphasizes the withstand voltage characteristic or the forward current (If) characteristic. Whether or not to form is determined.
In addition, various modifications can be made without departing from the scope of the present invention.

  Next, a method for manufacturing the semiconductor integrated circuit device of the present invention shown in FIG. 1 will be described with reference to FIGS.

  First, as shown in FIG. 6, a P-type single crystal silicon substrate 21 is prepared, and the surface of the substrate 21 is thermally oxidized to form a silicon oxide film on the entire surface, for example, about 0.03 to 0.05 μm. . Thereafter, a photoresist having an opening in a portion where the N + type first buried layer 28 is formed is formed using a known photolithography technique as a selection mask. Thereafter, N-type impurities such as antimony (Sb) are ion-implanted and diffused at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 13 to 1.0 × 10 15 / cm 2.

  Next, as shown in FIG. 7, on the silicon oxide film formed in FIG. 6, the first isolation region 25 of the isolation region 24 and the P + type first buried layer 29 are formed by a known photolithography technique. A photoresist having an opening is formed as a selection mask. Then, a P-type impurity such as boron (B) is ion-implanted and diffused at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 13 to 1.0 × 10 15 / cm 2. Thereafter, the photoresist is removed. At this time, the N + type first buried layer 28 is simultaneously diffused.

  Next, as shown in FIG. 8, all of the silicon oxide film formed in FIG. 6 is removed, and the substrate 21 is placed on the susceptor of the epitaxial growth apparatus. Then, a high temperature of, for example, about 1000 ° C. is given to the substrate 21 by lamp heating, and SiH 2 Cl 2 gas and H 2 gas are introduced into the reaction tube. Thereby, the first epitaxial layer 22 having a specific resistance of 1.25 Ω · cm and a thickness of 2.0 to 10.0 μm is grown on the substrate 21. Thereafter, the surface of the first epitaxial layer 22 is thermally oxidized to form a silicon oxide film of about 0.03 to 0.05 μm, for example. Then, a photoresist having an opening in a portion where the N + type second buried layer 30 is formed is formed using a known photolithography technique as a selection mask. Then, an N-type impurity such as phosphorus (P) is ion-implanted and diffused at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 13 to 1.0 × 10 15 / cm 2. Thereafter, the photoresist is removed. At this time, the N + type first buried layer 28, the P + type first isolation region 25, and the P + type first buried layer 29 are simultaneously diffused.

  Next, as shown in FIG. 9, the second isolation region 26 of the isolation region 24 and the P + type second buried layer 31 are formed on the silicon oxide film formed in FIG. 8 by a known photolithography technique. A photoresist having an opening is formed as a selection mask. Then, a P-type impurity such as boron (B) is ion-implanted and diffused at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 13 to 1.0 × 10 15 / cm 2. Thereafter, the photoresist is removed. At this time, the N + type second buried layer 30 is simultaneously diffused.

  Next, as shown in FIG. 10, all of the silicon oxide film formed in FIG. 8 is removed, and the substrate 21 is placed on the susceptor of the epitaxial growth apparatus. Then, a high temperature of, for example, about 1000 ° C. is given to the substrate 21 by lamp heating, and SiH 2 Cl 2 gas and H 2 gas are introduced into the reaction tube. Thereby, the second epitaxial layer 22 having a specific resistance of 1.25 Ω · cm and a thickness of 8.0 to 10.0 μm, for example, is grown on the substrate 21. Thereafter, the surface of the second epitaxial layer 22 is thermally oxidized to form a silicon oxide film of about 0.03 to 0.05 μm, for example. Then, a photoresist having an opening in a portion where the N + type first diffusion region 33 is formed is formed using a known photolithography technique as a selection mask. Then, an N-type impurity such as phosphorus (P) is ion-implanted and diffused at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 13 to 1.0 × 10 15 / cm 2. Thereafter, the photoresist is removed. At this time, the N + type second buried layer 30, the P + type second isolation region 26, and the P + type second buried layer 31 are simultaneously diffused.

  Next, as shown in FIG. 11, on the silicon oxide film formed in FIG. 10, the third isolation region 26 of the isolation region 24 and the P + type first diffusion region 34 are formed by a known photolithography technique. A photoresist having an opening is formed as a selection mask. Then, a P-type impurity such as boron (B) is ion-implanted and diffused at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 13 to 1.0 × 10 15 / cm 2. Thereafter, the photoresist is removed. At this time, the N + type first diffusion region 33 is simultaneously diffused.

  Next, as shown in FIG. 12, on the silicon oxide film formed in FIG. 10, a photoresist in which an opening is provided in a portion where the P + type second diffusion region 32 is formed by a known photolithography technique is selected. Form as a mask. Then, a P-type impurity such as boron (B) is ion-implanted and diffused at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 13 to 1.0 × 10 15 / cm 2. Thereafter, the photoresist is removed. At this time, the third isolation region 26 and the P + type first diffusion region 34 are simultaneously diffused.

  Next, as shown in FIG. 13, on the silicon oxide film formed in FIG. 10, a photoresist in which an opening is provided in the portion where the N + type second diffusion region 35 is formed by a known photolithography technique is selected. Form as a mask. Then, an N-type impurity such as phosphorus (P) is ion-implanted and diffused at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 13 to 1.0 × 10 15 / cm 2. Thereafter, the photoresist is removed. At this time, the P + type second diffusion region 32 is simultaneously diffused.

  Finally, an anode electrode 39 and a cathode electrode 41 made of, for example, Al are formed through contact holes 37, 38, and 40 formed in the insulating layer 36. At this time, in this embodiment, the common anode electrode 39 is connected to the N + type first diffusion region 33 and the second diffusion region 32 through the contact holes 37 and 38 as described above. Then, the diode element shown in FIG. 1A is completed.

  In the present embodiment, the manufacturing method using only the diode element has been described. However, a vertical PNP transistor element, an NPN transistor element, and the like are formed in other island regions. In addition, various modifications can be made without departing from the scope of the present invention.

  The effect will be described below.

  First, in the diode element of the semiconductor integrated circuit device of the present invention, P-type first and second diffusion regions are formed from the surface of the second epitaxial layer, and a part of both is superimposed on each other. Form. And it is characterized in that it is connected to the anode electrode immediately above the P-type second diffusion region. As a result, the parasitic resistance including the P-type second diffusion region can be increased. Then, the base potential of the parasitic PNP transistor can be reliably set higher than the emitter potential. As a result, it is possible to reliably suppress the operation of the parasitic PNP transistor when the diode element is ON, and to significantly suppress the leakage current to the substrate.

  Second, the diode element of the semiconductor integrated circuit device according to the present invention is characterized in that the parasitic resistance including the P-type second diffusion region can be increased as in the first effect. As a result, the collector potential of the parasitic NPN transistor can be reliably set higher than the base potential. As a result, the forward current of the diode element can be greatly increased by the operation of the parasitic NPN transistor.

  Third, in the diode element of the semiconductor integrated circuit device of the present invention, the same effect can be obtained by forming polysilicon doped with impurities on the surface of the second epitaxial layer instead of the P-type second diffusion region. Can be obtained. That is, the first and second effects described above can be obtained by increasing the parasitic resistance with polysilicon as in the case of the P-type second diffusion region.

  Fourth, the diode element of the semiconductor integrated circuit device according to the present invention is characterized in that an N-type well region is formed in the second epitaxial layer so as to surround the cathode extraction region in accordance with the intended use. As a result, the N-type well region reduces the resistance value of the N-type region of the PN junction, thereby reducing the forward voltage (VBEF). As a result, the forward current (If) characteristics of the diode element can be greatly improved. Then, an N-type well region can be formed by arbitrary selection in consideration of the breakdown voltage characteristic and the forward current (If) characteristic.

It is (A) sectional drawing (B) equivalent circuit schematic for demonstrating the diode element of the semiconductor integrated circuit device of this invention. It is a characteristic view which shows the relationship between the forward current of the semiconductor integrated circuit device of this invention, and the leakage current to a board | substrate. 1 is a sectional view for explaining a semiconductor integrated circuit device of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a sectional view for explaining a semiconductor integrated circuit device of the present invention, and FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view for explaining a method for manufacturing a semiconductor integrated circuit device of the present invention. 1 is a sectional view for explaining a method for manufacturing a semiconductor integrated circuit device of the present invention. 1 is a sectional view for explaining a method for manufacturing a semiconductor integrated circuit device of the present invention. 1 is a sectional view for explaining a method for manufacturing a semiconductor integrated circuit device of the present invention. 1 is a sectional view for explaining a method for manufacturing a semiconductor integrated circuit device of the present invention. 1 is a sectional view for explaining a method for manufacturing a semiconductor integrated circuit device of the present invention. 1 is a sectional view for explaining a method for manufacturing a semiconductor integrated circuit device of the present invention. 1 is a sectional view for explaining a method for manufacturing a semiconductor integrated circuit device of the present invention. It is an equivalent circuit diagram for explaining a conventional semiconductor integrated circuit device. It is sectional drawing for demonstrating the diode element of the conventional semiconductor integrated circuit device.

Claims (2)

A semiconductor substrate of one conductivity type;
A reverse conductivity type semiconductor layer formed on the surface of the semiconductor substrate;
An isolation region of one conductivity type that arrives at the semiconductor substrate from the surface of the semiconductor layer and forms an island region of a reverse conductivity type;
A reverse conductivity type first buried layer formed between the semiconductor substrate and the semiconductor layer in the island region;
It is formed between the semiconductor substrate and the semiconductor layer so as to overlap with the first buried layer and to be derived from at least the upper direction of the first buried layer and from above the first buried layer. A second buried layer of one conductivity type,
The semiconductor layer as a cathode, a cathode contact region of a reverse conductivity type formed on the surface of the semiconductor layer,
A cathode electrode connected to the cathode contact region ;
A diffusion region of one conductivity type formed so as to reach the second buried layer from the surface of the semiconductor layer and surround the cathode contact region; an anode region comprising the second buried layer;
A reverse conductivity type diffusion region formed so as to reach the first buried layer from the surface of the semiconductor layer and surround the one conductivity type diffusion region;
A one-conductive type parasitic resistance adjustment region formed from the one-conductive type diffusion region formed from the surface of the semiconductor layer and reaching the second buried layer;
A semiconductor integrated circuit device having a diode element that suppresses a parasitic effect, comprising: an anode electrode that contacts the parasitic resistance adjustment region and a reverse conductivity type diffusion region reaching the first buried layer. 2. The semiconductor integrated circuit device having a diode element with suppressed parasitic effect according to claim 1, wherein poly-Si is provided on the semiconductor layer instead of the parasitic resistance adjusting region.

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