JP4945868B2 - Integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to an integrated circuit such as a high voltage IC.
[0002]
[Prior art]
  Power devices are widely used in many fields such as inverters and converters for motor control, inverters for lighting, various power supplies, and switches for driving solenoids and relays. The driving and control of this power device has been conventionally performed by an electronic circuit configured by combining individual semiconductor elements and electronic components, but in recent years, several tens of years using LSI (high integration IC, IC is an integrated circuit) technology. V-class low voltage IC and several hundred V-class high voltage IC are put into practical use, and power ICs with integrated drive / control circuits and power devices on the same semiconductor substrate are used to convert inverters, converters, etc. Miniaturization and high reliability of devices and the like are achieved.
[0003]
  FIG. 17 is a circuit diagram illustrating the power portion of the motor control inverter. The power devices used to drive the three-phase motor Mo (here, the IGBTs Q1 to Q6 and the diodes D1 to D6 are shown) constitute a bridge circuit and have a power module structure housed in the same package. Yes. Here, IGBT is an insulated gate bipolar transistor. Main power supply V_CCIs usually a high voltage of 100 to 400 VDC. Main power supply V_CCThe high potential side of_CCH, V on the low potential side_CCLV_CCHIn order to drive the IGBTs Q1 to Q3 connected to the IGBT, the potential of the gate electrode of the IGBT becomes higher than this, so that the driving circuit includes a photocoupler (PC: Photo Coupler) or a high voltage IC (HVIC: High). (Voltage Integrated Circuit) is used. The input / output terminal I / O (Input / Output) of the drive circuit is normally connected to a microcomputer, and the microcomputer controls the entire inverter.
[0004]
  FIG. 18 shows a block diagram of an internal configuration unit of the high voltage IC (HVIC) used in FIG. The configuration will be described next. A control circuit CU (Control Unit) that exchanges signals with the microcomputer through the input / output terminal I / O, generates a control signal for turning on and off which IGBT, and a signal from the control circuit CU. The signals are received by the input lines SIN4 to SIN6 and output from the IGBT gate drive output lines OUT4 to OUT6. The overcurrent of the IGBT is detected by the current detection terminals OC4 to 6, and the overheat is detected by the temperature terminals OT4 to 6. The abnormal signal is output through the output lines SOUT4 to SOUT6, and the main power supply V in FIG._CCLow potential side V_CCLGate drive circuits GDU (Gate Drive Unit) 4 to 6 for driving IGBTs Q4 to Q6 connected to the main power supply V with the same function as GDU4 to 6_CCHigh potential side V_CCHGate drive circuits GDU1 to GDU1 to drive Q1 to Q3 connected to V, and V_CCLLevel control circuit CU signal and V_CCHLevel and V_CCLIt is composed of a level shift circuit LSU (Level Shift Unit) that acts as an intermediary between signals of GDU 1 to 3 (SIN 1 to 3, SOUT 1 to 3) that go back and forth between levels.
[0005]
  Drive power supply for GDU 1 to 3 (see FIG. 19) V_DD1~ V_DD3The high potential side of_DDH1~ V_DDH3, V on the low potential side_DDL1~ V_DDL3The GDU4-6 drive power supply is a common power supply V_DDC(This is also omitted in FIG. 19)._DDCThe high potential side of_DDHC, V on the low potential side_DDLCIt shows with. GDU4-6 and CU drive common power supply V_DDCIs about 10-20V, and this common power supply V_DDCLow potential side V_DDLCIs the main power supply V in FIG._CCLow potential side V_CCLConnect to.
[0006]
  FIG. 19 shows a more detailed connection diagram between GDU1 and IGBT Q1 of FIG. Other GDUs and IGBTs are omitted here. GDU1 drive power supply V_DD1Is about 10 to 20V, and its low potential side V_DDL1Is IGBTQ₁Connected to the U phase of the inverter output, and the collector terminal C of the IGBT Q1 is connected to the main power source V._CCHigh potential side V_CCHIt is connected to the. Therefore, when IGBTQ1 is turned on, V_DDL1The potential of V is V_CCHWhen the IGBT Q1 is turned off._DDL1The potential of V is V_CCLIs substantially equal to the potential. Therefore, the main power supply V is not connected between the GDU 1 and other circuit units._CCTherefore, a higher withstand voltage is required than GDUs 2 and 3. The level shift circuit LSU must itself have a high breakdown voltage. In the figure, the IGBT Q1 includes a current detection terminal M, a temperature detection element θ, and a temperature detection terminal Temp. The gate drive circuit GDU1 detects an abnormality of the IGBT Q1 by the current detection terminal OC1 and the temperature detection terminal OT1, and outputs an abnormality signal to the output line SOUT1. Output from. OUT1 is a gate drive terminal.
[0007]
  FIG. 20 is a plan view of the high voltage IC (HVIC) chip shown in FIG. 18 so that the arrangement of each circuit unit can be understood. The GDU 1 that needs to be separated from other circuit units at a high breakdown voltage is formed in an island that is electrically isolated by junction isolation or dielectric isolation, and the periphery of the GDU 1 is formed at a high breakdown voltage junction termination structure HVJT (insulation). In order to achieve this, it is surrounded by a junction end structure to which a high voltage is applied. In the level shift circuit LSU, the main power supply V_CCV on the low potential side_CCLLevel signal to drive power supply V_DD1V on the low potential side_DDL1A high breakdown voltage n-channel MOSFET (HVN) is provided for level shifting to a level signal (signal on the input line SIN1).
[0008]
  This high breakdown voltage n-channel MOSFET has a central drain electrode D._NIs surrounded by a high voltage junction termination structure HVJT. There is a VDU in the isolated island of GDU1._DDL1Level signal (output line SOUT1 signal) is V_CCLA high breakdown voltage p-channel MOSFET (HVP) for level shifting to a level signal is provided, and also in this case, the drain electrode D_PIs surrounded by a high voltage junction termination structure HVJT. The input line SIN1 and the output line SOUT1 of the GDU1 are routed between the GDU1 and the LSU over the high voltage junction termination structure HVJT. Each GDU is provided with the OUT terminal, OC terminal, and OT terminal shown in FIG. 19, and GDU1 to GDU3 have V terminals._DDH1~ V_DDH3Terminal, V_DDL1~ V_DDL3Terminals are arranged, and GDU4 to GDU6 have V_DDHCTerminal and V_DDLCTerminals are arranged. In the same figure, GDU1 and GDU4 are described in detail, and detailed arrangement description of other GDUs is omitted.
[0009]
  The above is the contents described in the section of the prior art in JP-A-9-74198. Next, another conventional example of the portion corresponding to the breakdown voltage junction termination structure HVJT and the high breakdown voltage MOS of FIG. 20 will be described.
  FIG. 21 is a plan view of the main part of the high voltage IC. In the following description, the high withstand voltage termination structure is denoted by reference numeral 3.
[0010]
  A floating potential reference circuit such as a gate drive circuit or a protection circuit of the upper arm at a high potential is formed in the floating potential reference circuit region 1 and is surrounded by a high withstand voltage junction structure 3 (peripheral region) so as to have a low potential. A reference potential is separated from a ground potential reference circuit region 2 in which a ground potential reference circuit, which is a ground reference control circuit such as a control circuit, a gate drive circuit, and a protection circuit of a lower arm, is formed. Is independent in terms of potential.
[0011]
  Signal transmission from the ground potential reference circuit to the floating potential reference circuit is performed, for example, by level up using a high voltage NMOS 5 (NMOS: n-channel MOSFET) for level up. As shown in FIG. 21, the high breakdown voltage NMOS 5 has a high breakdown voltage NMOS 5 in order to sufficiently increase the parasitic resistance R1 shown in FIG. p⁺JP-A-9-55498, JP-A-10-27853, etc. show that the distance L1 between the drain region 21 and the floating potential reference circuit region 1 is sufficiently large. 26 is a cross-sectional view of a main part taken along line NN in FIG. 24, and FIG. 27 is an example of a cross-sectional view of the main part different from FIG.
[0012]
  Signal transmission from the floating potential reference circuit to the ground potential reference circuit is performed, for example, by level shift down using a high voltage PMOS 4 (PMOS: p-channel MOSFET) for level down. As shown in FIG. 22 corresponding to the enlarged view of the part A in FIG. 21, the high breakdown voltage PMOS 4 has a purpose of reducing the parasitic leakage current 26, and in order to sufficiently increase the parasitic resistance R0, Japanese Patent Application Laid-Open No. 9-55498. As disclosed in Japanese Patent Laid-Open No. 10-27853 and Japanese Patent Application Laid-Open No. 10-27853, the high-voltage PMOS p.⁺The drain region 15 and the GND potential p⁺It is necessary to make the distance L2 with the region 19 sufficiently large.
[0013]
  Further, as shown in FIG. 21, when the high breakdown voltage PMOS 4 is formed in the high breakdown voltage junction termination structure 3, as shown in FIG. 21, an enlarged view around the level down high breakdown voltage PMOS 4 in FIG. As shown in FIG.^-Insert a slit 14 in the offset region 13 and p^-Separated from the offset regions 13a and 13b, the p of the high breakdown voltage PMOS 4⁺The drain region 15 and p at the GND potential^-Japanese Laid-Open Patent Publication No. 10-27853 discloses a method of electrically isolating regions 19 to suppress parasitic leakage current 27.
[0014]
  FIG. 25 is a cross-sectional view of a principal part taken along line XX in FIG. p^-An n well region 12 is formed on the surface layer of the substrate 11, and p is formed on the surface layer of the n well region 12.^-An offset region 13a is formed. This p^-In contact with the offset region 13a or p^-In the offset area 13a, p⁺A drain region 15 is formed and p^-P apart from the offset region 13a⁺A source region 17 is formed. Further, the gate electrode 16 is formed through a gate insulating film (not shown). p^-An insulating film 31 is formed on the offset region 13a. N⁺P adjacent to source region 17⁺Region 18 is formed and p^-P to take the potential of the substrate 11⁺Region 20 is formed.
[0015]
  FIG. 28 is a cross-sectional view of a principal part taken along line YY of FIG. P with which high voltage PMOS is formed^-Offset region 13a and p in which PMOS is not formed^-The offset regions 13b are separated by slits 14, respectively. The size (width) of the slit 14 is p.^-The size of the resist mask (not shown) at the time of ion implantation when forming the offset regions 13a and 13b, and 32 and 33 in the figure indicate the ends of the resist mask. By providing this slit 14, p of the high voltage PMOS 4 is provided.⁺Drain region 15 and p at GND potential⁺Between regions 19 (p^-Offset region 13a and p^-The structure is such that the parasitic leakage current 27 between the offset region 13b) is reduced.
[0016]
  In FIGS. 22 and 23, reference numeral 16 denotes a gate electrode, and 17 denotes p.⁺Source region, 18 and 20 are p⁺It is an area. In FIG. 24, reference numeral 22 denotes a p-well region, and 23 denotes n.⁺A source region 24 is a gate electrode.
[0017]
[Problems to be solved by the invention]
  As described above, when the high breakdown voltage NMOS 5 or the high breakdown voltage PMOS 4 used for level shift up and level shift down of the high breakdown voltage IC is used, as described in the prior art, the drain of the high breakdown voltage NMOS and the floating potential reference circuit region 1 which is the same potential as the distance L1 of 1, the drain of the high breakdown voltage PMOS, and the ground potential reference circuit region 2⁺The distance L2 from the region 19 is sufficiently large, or in the high breakdown voltage PMOS 4, p^-It is necessary to insert a slit 14 in the offset region 13.
[0018]
  The distance L1 between the drain of the high voltage NMOS and the floating potential reference circuit region 1 and the distance between the drain of the high voltage PMOS and the ground potential reference circuit region 2 (p⁺Drain region 15 and p⁺When the space (space 19) is sufficiently large, the chip size increases and the chip cost increases.
  p^-When the slit 14 is inserted in the offset region 13, the generation of the parasitic leakage current 27 is suppressed, and the chip size does not increase. However, p constituting the high-voltage junction termination structure 3 at the 14 positions of the slits.^-Substrate 11, n-well region 12, p^-The breakdown voltage decreases due to the loss of the charge balance in the offset regions 13a and 13b.
[0019]
  This will be described with reference to FIGS. Normal region without slit 14 (n well region 12 and p^-In the case where the pn junction 25 in the offset region is flat indicated by a dotted line), p^-The charge amount per unit area of the offset region and the n-well region (so-called RESURF (Reduced Surface Field) condition) is p below the breakdown voltage.^-All offset regions are depleted. This charge amount is 1.2 × 10¹²cm^-2Degree.
[0020]
  On the other hand, in the place where the slit 14 is present, p^-The charge amount (acceptor amount) in the offset regions 13a and 13b is smaller than the charge amount satisfying the RESURF condition, and the charge amount (donor amount) in the n-well region 12 is larger than the charge amount satisfying the RESURF condition. .
  This is because, in the n-well region 12, the n-well region 12 and p^-When the pn junction 25 in the offset region is flat, the donor amount in the D portion increases relative to the donor amount in the C portion region of the n-well region 12, and p^-In the offset regions 13a and 13b, the acceptor amount of the D portion is reduced as compared with the case where the pn junction is flat. For this reason, the charge balance in this portion is broken, and depletion is not properly performed. As shown in FIG. 30 showing the state of the depletion layer 41 in the n-well region 12, the depletion is present in the n-well region 12 below the slit 14. A cavity region E where the layer 41 does not expand is formed, yielding occurs, and the breakdown voltage decreases. Although not shown, p^-All regions of the offset regions 13a and 13b are depleted, and p^-A part of the board is also air-proofed.
[0021]
An object of the present invention is to solve the above-described problems and provide an integrated circuit capable of suppressing a parasitic leakage current without increasing a chip size and preventing a decrease in breakdown voltage.
[0022]
[Means for Solving the Problems]
  To achieve the above object, a well region of a second conductivity type formed in a surface layer of a semiconductor substrate of a first conductivity type and having a high voltage circuit therein, and substantially surrounding the high voltage circuit, the well In an integrated circuit having an offset region of a first conductivity type formed in a surface layer of a terminal portion of a region and at least one independent isolation region in which a part of the offset region is independently isolated, the offset region and the independent isolation It is assumed that the diffusion depth of the well region at a location sandwiched between the regions is shallower than the diffusion depth other than the location.
[0023]
  Also, a second conductivity type well region which is diffused and formed in the surface layer of the first conductivity type semiconductor substrate and contains the high voltage circuit, and substantially surrounds the high voltage circuit, and is formed on the end surface layer of the well region. First conductivity type offset region to be formed and the offset regionAreaConnectionYouIn the integrated circuit having at least one first conductivity type independent region, the offset region and the independent region are formed by diffusion., MutualThe surface portion is in contact with each other, and the diffusion depth of the well region under the vicinity of the contact portion is the vicinity.underofOther thanThe structure is shallower than the diffusion depth.
  Also, a second conductivity type well region which is diffused and formed in the surface layer of the first conductivity type semiconductor substrate and contains the high voltage circuit, and substantially surrounds the high voltage circuit, and is formed on the end surface layer of the well region. In an integrated circuit having a first conductivity type offset region to be formed and at least one independent separation region in which a part of the offset region is independently separated, in the vicinity of a portion sandwiched between the offset region and the independent separation region In the lower well region, a first conductivity type region is formed apart from the offset region.
[0024]
  Also, a second conductivity type well region which is diffused and formed in the surface layer of the first conductivity type semiconductor substrate and contains the high voltage circuit, and substantially surrounds the high voltage circuit, and is formed on the end surface layer of the well region. First conductivity type offset region to be formed and the offset regionAreaConnectionYouIn an integrated circuit having at least one first conductivity type independent region, MutualThe surface portion is in contact, and the first conductivity type region is formed apart from the offset region in the well region near the contacted portion.
  Also,A diffusion region formed on the surface layer of the first conductivity type semiconductor substrate and having a high voltage circuit and a second conductivity type well region substantially surrounding the high voltage circuit and formed on the termination surface layer of the well region; An integrated circuit having an offset region of a first conductivity type and at least one independent isolation region in which a part of the offset region is independently isolated,A plurality of the well regions are formed apart from each other, and the offset region or the independent isolation region is formed in the surface layer of each of the plurality of well regions.
[0025]
  In addition, the independent separation regionOr the independent regionA first conductivity type source region formed on the high voltage circuit side apart from the source region, the source region and theIndependent separation region or said independent regionA gate electrode formed on the well region sandwiched by a gate insulating film, and the independent isolation region on the terminal end side of the well regionOr the independent regionTouch orWithin the independent separation region or within the independent regionAnd a first conductivity type drain region formed in the surface layer of.
[0026]
  In the independent separation regionOr in the independent regionA second conductivity type cathode region formed on the high-voltage circuit side and an independent isolation region on the terminal end side of the well regionOr the independent regionTouch orWithin the independent separation region or within the independent regionAnd a first conductivity type anode region formed in the surface layer of.
  In addition, the independent separation regionOr the independent regionA second conductivity type drain region formed on the high voltage circuit side and spaced apart from the well region, and the independent isolation region on the terminal end side of the well regionOr the independent regionIn contact with or in close proximity to1A conductive type base region; a second conductive type source region formed in a surface layer of the base region; and a gate formed on the base region sandwiched between the source region and the well region via a gate insulating film A structure having electrodes.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
  The embodiments described below show a high voltage IC in which the present invention is applied to a high voltage PMOS for level shift down. In the description of the drawings, the same reference numerals are given to the same parts as those in the prior art.
  FIG. 1 is a cross-sectional view of a main part of a high voltage IC according to a first embodiment of the present invention. This figure is a sectional view corresponding to FIG.
[0028]
  p^-An n-well region 12 is formed on the surface layer of the substrate by ion implantation using a resist mask (not shown) and heat treatment. The n well region 12 is formed so as to be connected under the resist mask by increasing the diffusion depth. Ions are implanted into the surface layer of the n-well region 12 using the resist mask, heat-treated, and p.^-Offset regions 13a and 13b are formed. This p^-The offset regions 13a and 13b are formed so as to be separated. A slit 14 is formed between the resist mask ends 32 and 33. An insulating film 31 is formed on the surface.
[0029]
  In this way, the depth of the n-well region 12 becomes shallow as shown in the F part in the figure at 14 slits. That is, the donor amount of the n-well region 12 at the 14 slits can be reduced until the charge balance is achieved. As a result of the charge balance, as shown in FIG. 2, the cavity region E as shown in FIG. 25 is not generated in the depletion layer 43 at the 14 positions of the slit. Since the cavity region E is not generated, it is possible to prevent the breakdown voltage from decreasing. P^-Since the offset regions 13a and 13b are separated, the parasitic leakage current can be suppressed. Also, by forming the slit 14, p⁺Drain region 15 and p⁺The distance L2 of the region 19 can be reduced, and the chip size can be reduced.
[0030]
  Note that FIG. 2 shows only the depletion layer 43 extending in the n-well region 12. At this time, although not shown, p^-All regions of the offset regions 13a and 13b are depleted, and p^-A part of the substrate 11 is also depleted.
  FIG. 3 is a cross-sectional view of a main part of a high voltage IC according to the second embodiment of the present invention. The difference from FIG.^-Offset regions 13a and 13b are connected and p^-This is a point that is an offset region 13. In this case, the parasitic resistance R2 is smaller than that in FIG. 1, but when the connection location is close to the surface, R2 can be increased, so that a parasitic leakage current can be suppressed. Further, by forming the n-well region 12 in the same manner as in FIG. 2, it is possible to balance the charge at the 14 locations of the slits and to prevent the breakdown voltage from decreasing. Further, similarly to FIG. 1, the chip size can be reduced.
[0031]
  FIG. 4 is a cross-sectional view of a main part of a high voltage IC according to a third embodiment of the present invention. The difference from FIG. 1 is that a p-buried region 51 is formed at a position corresponding to the F portion to achieve charge balance. In this case, the same effect as in FIG. 1 can be obtained.
  FIG. 5 is a sectional view showing the principal part of a high voltage IC according to the fourth embodiment of the present invention. The difference from FIG. 3 is that a p-buried region 52 is formed at 14 positions of the slit to achieve charge balance. In this case, the same effect as in FIG. 2 can be obtained.
[0032]
  FIG. 6 is a sectional view showing the principal part of a high voltage IC according to the fifth embodiment of the present invention. The difference from FIG. 1 is that the n-well region 12 is also separated by the I portion at 14 slits. By separating the n-well region 12, parasitic leakage current can be further suppressed. In addition, since the charge balance can be achieved in the same manner as in FIG. 1, it is possible to prevent the breakdown voltage from decreasing.
[0033]
  FIG. 7 is a plan view of the main part of a high voltage IC according to the sixth embodiment of the present invention. The high breakdown voltage PMOS 4 (p) for level down is provided in the high breakdown voltage junction termination region 3 protruding in a semicircular shape.⁺Drain region 28, p⁺This is a case where the source region 29) is formed and the slit 14 is provided in the high breakdown voltage junction termination region 3. The cross-sectional structure of the slit 14 is the same as that of any of FIGS. Also in this case, the effect is the same as the case where it is provided in the straight portion as shown in FIG.
[0034]
  The embodiment described below shows a high voltage IC in which the present invention is applied to a high voltage NMOS for level shift up.
  FIG. 8 shows a high voltage IC according to a seventh embodiment of the present invention. This figure corresponds to portion J in FIG. A plurality of slits 14 are formed at the high voltage junction end portion. Cross-sectional views of the main part of the slit 14 are shown in FIGS.
[0035]
  The case of FIG. 9 will be described. p^-The offset region 13 is divided at 14 slits and the n-well region 2 is shallowed at 14 slits as shown in FIG. 1, thereby increasing the parasitic resistance R3 in the n-well region 12 and maintaining the charge balance. Suppresses the decline. Further, increasing the number of slits 14 increases the parasitic resistance R3, and the high breakdown voltage NMOS n⁺The distance L3 between the drain region and the floating potential reference circuit region 1 can be shortened.
[0036]
  In the case of FIG. 10, p^-The offset region 13 is not divided and connected at 14 slits, and the n-well region 2 is shallowed at 14 slits as shown in FIG. 9, thereby increasing the parasitic resistance R4 in the n-well region 12 and charging. Balance and suppress pressure drop. Further, increasing the number of slits 14 can increase the parasitic resistance R4 and shorten the distance L3.
[0037]
  In the case of FIG. 11, as in the case of FIG.^-The offset region 13 is divided, and the p-buried region 51 is formed in the n-well region 2 at 14 slits, whereby the parasitic resistance R5 in the n-well region 12 is increased, charge balance is achieved, and the breakdown voltage is reduced. Suppress. Further, increasing the number of slits 14 can increase the parasitic resistance R5 and shorten the distance L3.
[0038]
  In the case of FIG. 12, as in the case of FIG.^-The offset region 13 is not divided and is connected at 14 slits, and the n-well region 2 is formed in the n-well region 2 at 14 slits as shown in FIG. In addition, the parasitic resistance R6 is increased, charge balance is achieved, and a decrease in breakdown voltage is suppressed. Further, increasing the number of slits 14 can increase the parasitic resistance R6 and shorten the distance L3.
[0039]
  In FIG. 13, p^-By separating the n-well region 2 in addition to the offset region 13, leakage current can be suppressed, charge balance can be achieved, and the breakdown voltage can be suppressed.
  Further, as shown in FIG. 14, the slit 14 of FIG. 8 is provided not only in the high withstand voltage junction termination structure 3 but also in the n well region 3 sandwiched between the high withstand voltage junction termination structure 3, thereby further increasing the parasitic resistance. be able to. FIG. 15 shows an example of a cross section of the main part.
[0040]
  FIG. 15 shows a case where a slit 14 a is provided in the slit 14 of FIG. 8 having the cross-sectional structure of FIG. 9 and also extending to the n-well region 3 sandwiched between the high voltage junction termination structures 3. This figure is a sectional view of the vicinity of the slit 14a cut along the line KK in FIG. Thus, by forming the slit 14a, the parasitic resistance R3 of FIG. 9 can be made a parasitic resistance R7 having a higher resistance value. Therefore, L3 can be further shortened from FIG. In addition, the region sandwiched by the high voltage junction termination structure 1 is also p.^-An offset region is formed and this p^-By dividing the offset region at the slit 14a, the parasitic resistance can be further increased.
[0041]
  Needless to say, the cross-sectional structure of the slit 14 shown in FIGS. 10 to 12 also has the effect of increasing the parasitic resistance.
  FIG. 16 is a sectional view showing the principal part of a high voltage IC according to the seventh embodiment of the present invention. This figure shows a case of a high breakdown voltage pn diode, which is an example in which a high breakdown voltage pn diode is formed at a location where the level shift down PMOS 4 of FIG. 21 is formed. The high breakdown voltage pn diode is used to transmit a signal of the floating potential circuit to the ground reference circuit when the diode becomes conductive.
[0042]
  p^-An n well region 12 is formed on the surface layer of the substrate 11, and p is formed on the surface layer of the n well region 12.^-An offset region 13a is formed. This p^-P in contact with the offset region 13a⁺An anode region 15a is formed, and p^-P on the surface layer of the offset region 13a.⁺P so as to face the anode region 15a⁺An anode region 17a is formed, and p^-An insulating film 31 is formed on the offset region 13a.
[0043]
  This pn diode is formed in part A of FIG.⁺P in the drain region 15⁺The anode region 15a is p⁺P instead of source region 17^-N in the offset region 13a⁺This is a case where the cathode region 17a is formed. In this case, the same effect can be expected by forming the slits 14 shown in FIGS. Although not shown, the present invention can also be applied to a high breakdown voltage bipolar transistor.
[0044]
【The invention's effect】
  According to the present invention, by forming the slit in the high breakdown voltage junction termination structure, it is possible to suppress a parasitic leakage current without increasing the chip size and to prevent a decrease in breakdown voltage.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of an essential part of a high voltage IC according to a first embodiment of the present invention.
FIG. 2 is a diagram showing the spread of a depletion layer at a slit location.
FIG. 3 is a cross-sectional view of a main part of a high voltage IC according to a second embodiment of the present invention.
FIG. 4 is a cross-sectional view of an essential part of a high voltage IC according to a third embodiment of the present invention.
FIG. 5 is a cross-sectional view of an essential part of a high voltage IC according to a fourth embodiment of the present invention.
FIG. 6 is a cross-sectional view of an essential part of a high voltage IC according to a fifth embodiment of the present invention.
FIG. 7 is a plan view of an essential part of a high voltage IC according to a sixth embodiment of the present invention.
FIG. 8 is a plan view of an essential part of a high voltage IC according to a seventh embodiment of the present invention.
FIG. 9 is a cross-sectional view of the main part of the slit portion (cross-sectional view of the main part taken along the line ZZ in FIG. 8).
FIG. 10 is a cross-sectional view of the main part of the slit portion (cross-sectional view of the main part taken along the line ZZ in FIG. 8).
11 is a cross-sectional view of the main part of the slit (cross-sectional view of the main part taken along the line ZZ in FIG. 8).
12 is a cross-sectional view of the main part of the slit location (cross-sectional view of the main part taken along the line ZZ in FIG. 8).
13 is a cross-sectional view of the main part of the slit (cross-sectional view of the main part taken along the line ZZ in FIG. 8).
FIG. 14 is a plan view of a principal part in which the slit portion of FIG. 8 is extended.
15 is a cross-sectional view of the main part of the slit portion extended in the cross-sectional view of the main part taken along the line KK of FIG.
FIG. 16 is a cross-sectional view of an essential part of a high voltage IC according to a seventh embodiment of the present invention.
FIG. 17 is a circuit configuration diagram illustrating mainly the power portion of the motor control inverter.
18 is a block diagram of an internal configuration unit of a high voltage IC (HVIC) used in FIG.
FIG. 19 is a more detailed connection diagram between GDU1 and IGBT Q1 in FIG.
20 is a configuration diagram in which the same circuit as FIG. 17 is configured using a product called an intelligent power module.
FIG. 21 is a plan view of the main part of a high voltage IC.
FIG. 22 is a view in the vicinity of a conventional high voltage junction termination structure, enlarging part A of FIG.^-Figure where the offset area is not divided
FIG. 23 is another view in the vicinity of the conventional high voltage junction termination structure, enlarging part A of FIG.^-Figure where the offset area is divided
24 is an enlarged view of part B in FIG. 21.
25 is a cross-sectional view of main parts taken along the line XX of FIG.
26 is a cross-sectional view of a principal part taken along the line NN of FIG. 24.
27 is a sectional view different from FIG.
28 is a cross-sectional view of main parts taken along line YY in FIG. 23.
FIG. 29 is a diagram for explaining the donor amount and the acceptor amount at the slit location.
FIG. 30 is a diagram showing a state where a depletion layer does not spread in a slit portion.
[Explanation of symbols]
          1 Gate drive circuit area
          2 Control circuit area
          3 High voltage junction termination structure
          4 High voltage PMOS for level down
          5 High voltage NMOS for level up
        11 p^-substrate
        12 n-well region
        13, 13a, 13b p^-Offset area
        14 Slit
        15, 28 p⁺Drain region
        15a p⁺Anode region
        16, 24 Gate electrode
        17, 29 p⁺Source area
        17a n⁺Cathode region
        18, 19, 20 p⁺region
        21 n⁺Drain region
        22 p-well region
        23 n⁺Source area
        25 pn junction
        26, 27 Parasitic leakage current
        31 Insulating film
        32, 33 Mask edge
        41, 43 Depletion layer
        51, 52 p buried region

Claims (8)

A diffusion region formed on the surface layer of the first conductivity type semiconductor substrate and having a high voltage circuit and a second conductivity type well region substantially surrounding the high voltage circuit and formed on the termination surface layer of the well region; An integrated circuit having an offset region of a first conductivity type and at least one independent isolation region in which a part of the offset region is independently isolated,
An integrated circuit, wherein a diffusion depth of the well region at a portion sandwiched between the offset region and the independent isolation region is shallower than a diffusion depth other than the portion. A diffusion region formed on the surface layer of the first conductivity type semiconductor substrate and having a high voltage circuit and a second conductivity type well region substantially surrounding the high voltage circuit and formed on the termination surface layer of the well region; An integrated circuit having an offset region of a first conductivity type and at least one first conductivity type independent region connected to the offset region;
The offset region and the independent region are formed by diffusion, the surface portions are in contact with each other, and the diffusion depth of the well region under the contacted portion is shallower than the diffusion depth other than the portion under the vicinity Integrated circuit. A diffusion region formed on the surface layer of the first conductivity type semiconductor substrate and having a high voltage circuit and a second conductivity type well region substantially surrounding the high voltage circuit and formed on the termination surface layer of the well region; An integrated circuit having an offset region of a first conductivity type and at least one independent isolation region in which a part of the offset region is independently isolated,
An integrated circuit, wherein a first conductivity type region is formed apart from the offset region in the well region near a portion sandwiched between the offset region and the independent isolation region. A diffusion region formed on the surface layer of the first conductivity type semiconductor substrate and having a high voltage circuit and a second conductivity type well region substantially surrounding the high voltage circuit and formed on the termination surface layer of the well region; An integrated circuit having an offset region of a first conductivity type and at least one first conductivity type independent region connected to the offset region;
The integration is characterized in that the offset region and the independent region are formed by diffusion, the surface portions are in contact with each other, and a first conductivity type region is formed in the well region below the contacted portion apart from the offset region. circuit. A diffusion region formed on the surface layer of the first conductivity type semiconductor substrate and having a high voltage circuit and a second conductivity type well region substantially surrounding the high voltage circuit and formed on the termination surface layer of the well region; An integrated circuit having an offset region of a first conductivity type and at least one independent isolation region in which a part of the offset region is independently isolated,
An integrated circuit, wherein a plurality of well regions are formed apart from each other, and the offset region or the independent isolation region is formed in a surface layer of each of the plurality of well regions. A first conductivity type source region formed on the high voltage circuit side apart from the independent isolation region or the independent region; and the well region sandwiched between the source region and the independent isolation region or the independent region. Formed on the gate electrode formed through the gate insulating film and on the end portion side of the well region, in contact with the independent isolation region or the independent region, or on the surface layer in the independent isolation region or in the independent region integrated circuit according to any one of claims 1 to 5 and having a first conductivity type drain region that. The second conductivity type cathode region formed on the high voltage circuit side in the independent isolation region or in the independent region, and in contact with the independent isolation region or the independent region on the terminal end side of the well region, or integrated circuit according to any one of claims 1 to 5 and having a first conductivity type anode region formed on the surface layer of the independent isolation region or the independent area. A second conductivity type drain region formed on the high voltage circuit side apart from the independent isolation region or the independent region, and the independent isolation region or the independent region in contact with a terminal portion side of the well region, or A first conductive type base region formed in the vicinity, a second conductive type source region formed in a surface layer of the base region, and gate insulation on the base region sandwiched between the source region and the well region integrated circuit according to any one of claims 1 to 5, characterized in that a gate electrode formed through a film.