JP4954482B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device (in particular, a liquid crystal display device) having a circuit formed of a thin film transistor (TFT) using a crystalline semiconductor film formed on a substrate, and a manufacturing method thereof. In particular, a semiconductor device manufactured according to the present invention includes a liquid crystal display device typified by an active matrix liquid crystal display device in which a pixel portion and a driver circuit around the pixel portion are provided on the same substrate, and the display device as a display portion It relates to the electric appliances used for this.

  Currently, a crystalline semiconductor film (typically a polysilicon film) provided on an insulating surface is used as a semiconductor element, and a TFT is used in each integrated circuit, and in particular, as a switching element of a display device. . Further, a TFT using a crystalline semiconductor film having a higher mobility than an amorphous semiconductor film as an active layer (a semiconductor layer including a channel formation region, a source region, and a drain region) has high driving capability, It is also used as an element. Therefore, for example, in an active matrix liquid crystal display device, an image circuit for displaying an image and a drive circuit for controlling the image circuit are formed on a single substrate.

  For example, in an active matrix liquid crystal display device, an integrated circuit such as a pixel circuit that performs image display for each functional block, a shift register circuit based on a CMOS circuit, a level shifter circuit, a buffer circuit, or a sampling circuit is formed on a single substrate. Formed on top. Such a liquid crystal display device has excellent features such as thinness, small size, light weight, and low power consumption. For example, it can be used for a display portion of a personal computer to save space, It has been used in various situations, such as being able to obtain the latest information anytime and anywhere using it as a display unit.

  In a liquid crystal display device, a TFT (also referred to as a pixel TFT) formed in a pixel portion functioning as a switching element and a pixel portion having a storage capacitor are driven by applying a voltage to liquid crystal. The liquid crystal needs to be driven by alternating current, and a method called frame inversion driving is often employed. The required TFT characteristic is that the off-current (Ioff: drain current value that flows when the TFT is turned off) is sufficiently low. However, a TFT using a polysilicon film has a problem that off current tends to be high. Therefore, as a means for solving this problem, a low concentration impurity region (LDD: Lightly Doped Drain) LDD structure (a low region between a channel formation region and a source region or a drain region to which an impurity element is added at a high concentration is provided. A structure in which a concentration impurity region is provided) is known.

  On the other hand, since a high drive voltage is applied to the buffer circuit, it is necessary to increase the breakdown voltage to such an extent that it does not break even when a high voltage is applied, and an on-current value (Ion: TFT It is necessary to ensure a sufficient drain current value during on-operation. A GOLD structure (Gate-drain Over lapped LDD) in which the gate electrode overlaps a part of the LDD region (via the gate insulating film) as a structure effective for preventing deterioration of the on-current value due to hot carriers. It has been known.

  In order to obtain a semiconductor device that satisfies the required performance, it is necessary to make TFTs in each circuit. However, in order to produce LDD structure TFTs and GOLD structure TFTs, the number of masks has to be increased. The increase in the number of masks used has led to an increase in the number of manufacturing processes, complexity, and a decrease in yield. Accordingly, the present invention provides a semiconductor device typified by an active matrix liquid crystal display device that reduces the TFT off-current of the pixel portion and improves the reliability of the TFT of the driver circuit (less deterioration due to hot carriers). It aims to realize without increasing.

  In addition, since the liquid crystal display device has a low effective utilization rate of light, in many cases, display is performed using a front light or a backlight in order to improve visibility. Although the power consumption of the liquid crystal display device itself is low, there is a problem in that the power consumption in the display unit increases because the front light or the backlight is used. Thus, an object is to realize a display device with high visibility without increasing the number of manufacturing steps.

  The present invention is a semiconductor device in which a TFT formed in a pixel portion and a driver circuit formed in the periphery of the pixel portion are provided with an n-channel TFT and a p-channel TFT on the same substrate. The second concentration impurity region of the TFT partially overlaps the gate electrode, and the second concentration impurity region of the p-channel TFT and the TFT formed in the pixel portion does not overlap the gate electrode. This is a featured semiconductor device.

The present invention is also a semiconductor device in which an n-channel TFT and a p-channel TFT are provided on the same substrate in a TFT formed in a pixel portion and a driver circuit formed in the periphery of the pixel portion. The gate electrode of the channel TFT is composed of a first conductive film in contact with a gate insulating film and a second conductive film in contact with the first conductive film, and the channel of the first conductive film The length in the long direction is longer than the length in the channel length direction of the second conductive film, and the second concentration impurity region partially overlaps the first conductive film, and the p-channel TFT and the A gate electrode of the TFT formed in the pixel portion includes the first conductive film in contact with the gate insulating film and the second conductive film in contact with the first conductive film, and the first conductive film The length of the first conductive film in the channel length direction is the second conductive Be the same as the length of the channel length direction, the impurity region of the second density is a semiconductor device which is characterized in that do not overlap with the gate electrode.

  According to the present invention, in a semiconductor device including a driver circuit having an n-channel TFT, a first p-channel TFT, and a second p-channel TFT, the n-channel TFT includes a channel formation region, a source region, A semiconductor layer including a drain region and an impurity region of a second concentration; a gate insulating film on the semiconductor layer; and a gate electrode on the gate insulating film, the gate electrode being in contact with the gate insulating film 1 conductive film and a second conductive film in contact with the first conductive film, and the second concentration impurity region overlaps the first conductive film with the gate insulating film interposed therebetween. The first p-channel TFT includes a semiconductor layer including a channel formation region, a source region, a drain region, and a fifth concentration impurity region, a gate insulating film on the semiconductor layer, and the gate insulation. A gate electrode on the film, and the channel formation region and the gate electrode have substantially the same length in the channel length direction. The second p-channel TFT includes a channel formation region, a source region, and a drain. A semiconductor layer including a region and a fifth concentration impurity region, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film, the gate electrode being in contact with the gate insulating film And a second conductive film in contact with the first conductive film, and the fifth concentration impurity region overlaps the first conductive film with the gate insulating film interposed therebetween. This is a semiconductor device.

  According to the present invention, in a semiconductor device including a driver circuit having an n-channel TFT, a first p-channel TFT, and a second p-channel TFT, the n-channel TFT includes a channel formation region, a source region, A semiconductor layer including a drain region and a second concentration impurity region; a gate insulating film on the semiconductor layer; and a gate electrode on the gate insulating film, the gate electrode being in contact with the gate insulating film 1 conductive film and a second conductive film in contact with the first conductive film, and the second concentration impurity region overlaps the first conductive film with the gate insulating film interposed therebetween. The first p-channel TFT includes a semiconductor layer including a channel formation region, a source region, a drain region, a fifth concentration impurity region, and an offset region, and the second p-channel TFT. The type TFT has a semiconductor layer including a channel formation region, a source region, a drain region and a fifth concentration impurity region, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film, and the gate electrode Consists of a first conductive film in contact with the gate insulating film and a second conductive film in contact with the first conductive film, and the fifth concentration impurity region is interposed through the gate insulating film. The semiconductor device is characterized by overlapping with the first conductive film.

According to another aspect of the present invention, there is provided a semiconductor device including an n-channel TFT, a driving circuit having a first p-channel TFT and a second p-channel TFT, and a pixel portion having a TFT and a storage capacitor. Has a semiconductor layer including a channel formation region, a source region, a drain region and a second concentration impurity region, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film, The first conductive film in contact with the gate insulating film and the second conductive film in contact with the first conductive film, and the impurity region having the second concentration is interposed through the gate insulating film. Overlapping the first conductive film, the first p-channel TFT includes a channel formation region, a source region, a drain region, a fifth concentration impurity region, and an offset region. The second p-channel TFT has a conductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. The second p-channel TFT includes a channel formation region, a source region, a drain region, and an impurity having a fifth concentration. A semiconductor layer including a region; a gate insulating film on the semiconductor layer; and a gate electrode on the gate insulating film, the gate electrode including a first conductive film in contact with the gate insulating film; A second conductive film in contact with the first conductive film, and the impurity region of the fifth concentration overlaps the first conductive film through a gate insulating film, and is formed in the pixel portion. The semiconductor device includes a semiconductor layer including a channel formation region, a source region, a drain region, a second concentration impurity region, and an offset region.

According to the present invention, in a semiconductor device including a driver circuit having an n-channel TFT, a first p-channel TFT, and a second p-channel TFT, the n-channel TFT includes a channel formation region, a source region, A semiconductor layer including a drain region and an impurity region of a second concentration; a gate insulating film on the semiconductor layer; and a gate electrode on the gate insulating film, the gate electrode being in contact with the gate insulating film A first conductive film and a second conductive film in contact with the first conductive film, and the impurity region having the second concentration overlaps the first conductive film with a gate insulating film interposed therebetween ( L _ov region) and has a region (L _off region) which does not overlap, the first p-channel type TFT and the second p-channel type TFT, a channel formation region, a source region, a drain region and the A semiconductor device including a semiconductor layer including an impurity region having a concentration of 5.

  In the above invention, the gate electrode of the n-channel TFT, the p-channel TFT, or the pixel TFT is an element selected from Ta, W, Ti, Mo, Al, and Cu, and an alloy material containing the element as a main component Alternatively, the semiconductor device is made of a compound material.

  In the above invention, the pixel portion has a plurality of protrusions, the pixel electrode electrically connected to the TFT formed in the pixel portion is uneven, and the curvature of the unevenness of the pixel electrode is The semiconductor device is characterized in that the radius is 0.1 to 0.4 μm, and the height of the unevenness of the pixel electrode is 0.3 to 3 μm.

  By using the present invention, TFTs having required characteristics can be manufactured on the same substrate without increasing the number of steps. Since the number of manufacturing steps is not increased, a reduction in manufacturing cost and yield can be suppressed. In addition, a highly reliable semiconductor device can be realized.

  Furthermore, a highly visible semiconductor device can be realized by forming a pixel electrode having unevenness.

(Embodiment 1)
An embodiment of the present invention will be described below with reference to FIGS.

  A base insulating film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 10. In the present embodiment, the two-layer structures 11a and 11b are used as the base insulating film 11, but a single-layer film or a structure in which two or more layers of the insulating films are stacked may be used.

Next, an amorphous semiconductor film is formed on the base insulating film 11 with a thickness of 30 to 60 nm. The material of the amorphous semiconductor film is not limited, but is preferably silicon or silicon germanium (Si _x Ge _1-x ; 0 <x <1, typically x = 0.001 to 0.05) alloy It is good to form with. Next, a crystalline semiconductor film obtained by subjecting the amorphous semiconductor film to a known crystallization treatment (laser crystallization method, thermal crystallization method, thermal crystallization method using a catalyst such as nickel) is obtained. The semiconductor layers 12 to 14 are formed by patterning into a desired shape.

Further, after forming the semiconductor layers 12 to 14, an impurity element imparting p-type conductivity may be added to control the threshold value (Vth) of the n-channel TFT. As an impurity element imparting p-type to a semiconductor, elements belonging to Group 13 of the periodic table such as boron (B), aluminum (Al), and gallium (Ga) are known.

  Next, a gate insulating film 15 that covers the island-shaped semiconductor layers 12 to 14 is formed. The gate insulating film 15 is formed by plasma CVD or sputtering, and is formed of an insulating film containing silicon with a thickness of 40 to 150 nm. Needless to say, this gate insulating film can be formed using an insulating film containing silicon as a single layer or a stacked structure.

  Next, a first conductive film (TaN) 16 a having a thickness of 20 to 100 nm and a second conductive film (W) 16 b having a thickness of 100 to 400 nm are stacked on the gate insulating film 15. The conductive film 16 may be formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used.

  Next, masks 17 to 19 made of resist are formed using a photolithography method, and a first etching process is performed using an ICP (Inductively Coupled Plasma) etching method or the like in order to form electrodes and wirings. I do. First, the W films 20b to 22b are etched under the first etching conditions so that the first conductive film has a tapered shape at the end, and then the W film and the TaN films 20a to 22a are simultaneously formed under the second etching conditions. Etching is performed to form first-shaped conductive layers 20-22. Reference numeral 26 denotes a gate insulating film, and a region not covered with the first shape conductive layers 20 to 22 is also etched and thinned at the same time.

  Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type conductivity is added to the semiconductor layer. The doping process may be performed by ion doping or ion implantation. In this case, the first shape conductive layers 20 to 22 serve as a mask for the impurity element imparting n-type, and the impurity regions 23 to 25 having the first concentration are formed in a self-aligning manner.

  Next, a second etching process is performed as shown in FIG. 1C without removing the resist mask. By performing anisotropic etching under these etching conditions, second shape second conductive films 27b to 29b are formed. Here, the first conductive layer and the gate insulating film are also slightly etched to form second-shaped first conductive films 27a to 29a, and second-shaped conductive layers 27 to 29 (first Conductive films 27a to 29a, second conductive films 27b to 29b) and a gate insulating film 39 are formed.

  Next, a second doping process is performed without removing the resist mask. In this case, an impurity element imparting n-type is doped as a condition of a high acceleration voltage by lowering the dose than in the first doping process, and inside the first concentration impurity region formed in FIG. New impurity regions 33 to 35 and 36 to 38 having new second concentrations are formed in the semiconductor layer. Doping is performed so that the second shape conductive layers 27 to 29 are used as masks against the impurity elements, and the impurity elements are also added to the semiconductor layers under the second shape first conductive films 27a to 29a. To do.

  Thus, the third concentration impurity regions 36 to 38 that overlap with the second shape first conductive films 27a to 29a, and between the first concentration impurity regions 30 to 32 and the third concentration impurity region. The impurity regions 33 to 35 having the second concentration are formed.

Next, after removing the resist mask, a resist mask 40 is newly formed so as to cover the n-channel TFT of the driver circuit portion, and a third etching process is performed as shown in FIG. I do. As a result, the third conductive layers 41 and 42 are formed by etching the first conductive layer of the p-channel TFT and the TFT in the pixel portion. Here, the gate insulating film 43 not covered with the mask 40 is slightly etched and thinned.

  In order to eliminate variation due to the difference in film thickness of the gate insulating film, after removing the resist mask, the gate insulating film is etched as shown in FIG. A region that is not etched remains using the conductive layer as a mask, and gate insulating layers 44 to 46 are formed.

  Next, resist masks 47 and 48 are newly formed, and a third doping process is performed as shown in FIG. By this third doping treatment, an impurity element imparting p-type conductivity is added to the semiconductor layer serving as the active layer of the p-channel TFT, and the third shape conductive layer 41 is used as a mask against the impurity element, thereby self-alignment. Thus, impurity regions 49 to 51 having the fourth concentration are formed.

  In this manner, a TFT as shown in FIG. 2C can be manufactured. The n-channel TFT 71 of the drive circuit 73 has a third concentration impurity region 36 (referred to as a GOLD region in this specification) that overlaps with the second shape conductive layer 27 that forms the gate electrode, outside the gate electrode. It has a second concentration impurity region 33 (also referred to as an LDD region in this specification) to be formed and a first concentration impurity region 30 that functions as a source region or a drain region. Further, the pixel TFT 74 in the pixel portion includes a third concentration impurity region 38 and a second concentration impurity region 35 (both referred to as an LDD region in this specification) formed outside the gate electrode and a source region. Alternatively, the impurity region 32 having the first concentration functioning as a drain region is provided.

(Embodiment 2)
In the present embodiment, a method for forming a convex part and forming a pixel electrode having irregularities in the same process as a process for manufacturing a TFT in a pixel part will be described.

  On one of a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate with an insulating film formed thereon, or a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment. Then, a base insulating film is formed, and a semiconductor layer is formed thereon.

  The protrusion can be manufactured according to the manufacturing process of the pixel TFT 1203 since a highly reproducible one can be obtained by using a photomask. FIGS. 3 to 5 show examples in which convex portions are formed by laminating a semiconductor layer, a gate insulating film, and a conductive film, which are laminated in the same manner as the manufacturing of the pixel TFT 1203.

  There is no particular limitation on the method for forming the protrusions, and a single layer of the above film or a laminate of any combination can also be used. For example, a convex portion formed of a stacked layer of a semiconductor layer and an insulating film or a convex portion formed of a single layer of a conductive film can be formed. That is, a plurality of convex portions can be formed without increasing the number of steps for manufacturing a semiconductor device.

  An interlayer insulating film is formed so as to cover the protrusions thus formed, the pixel TFTs formed in the same process, and the TFTs included in the drive circuit. The curvature of the unevenness of the pixel electrode can be adjusted by the material of the insulating film, and the curvature radius of the unevenness of the pixel electrode is 0.1 to 0.4 μm (preferably 0.2 to 2 μm). In addition, when an insulating film made of an organic resin film is formed, an organic resin film (for example, a material such as polyimide or acrylic resin) having a viscosity of 10 to 1000 cp (preferably 40 to 200 cp) is used, and the influence of the uneven region is sufficiently increased. Using an organic resin material that has irregularities on its surface.

  When the interlayer insulating film having unevenness is formed, a pixel electrode is formed thereon. The surface of the pixel electrode is also affected by the unevenness of the insulating film, and the surface becomes uneven. The height of the unevenness is 0.3 to 3 μm. The unevenness formed on the surface of the pixel electrode can effectively scatter light when incident light is reflected as shown in FIG.

  In the embodiment of the present invention, a convex portion in which a semiconductor layer, a gate insulating film, a first conductive film, and a second conductive film are stacked is shown in accordance with a process for manufacturing a pixel TFT, but is particularly limited. However, any layer, a single layer of a film, or a combination of layers may be used. Without increasing the number of steps, a convex portion having a required height can be formed. Note that the convex portions adjacent to each other are separated by 0.1 μm or more, preferably 1 μm.

Although not particularly limited, it is preferable that the size of the convex portion is random in order to scatter the reflected light. Further, the shape and arrangement of the convex portions may be irregular or regular. Further, the convex portion is not particularly limited as long as it is a region below the pixel electrode that becomes a display region of the pixel portion.
The size of the protrusions when observed from above is in the range of 100-400 ^2, preferably may is 25 to 100 m ^2.

  As described above, a concavo-convex pixel electrode can be manufactured without increasing the number of manufacturing steps.

  An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel portion and TFTs (n-channel TFT and p-channel TFT) of a driver circuit provided around the pixel portion on the same substrate will be described in detail.

  As the substrate 100, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate with an insulating film formed thereon may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.

Next, as illustrated in FIG. 7A, a base insulating film 101 including an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 100. In this embodiment, a two-layer structure is used as the base insulating film 101, but a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer 101a of the base insulating film 101, a silicon oxynitride film 101a formed by using SiH ₄ , NH ₃ , and N ₂ O as a reactive gas is formed to a thickness of 50 to 100 nm. Next, as the second layer 101b of the base insulating film 101, a silicon oxynitride film 101b formed using SiH ₄ and N ₂ O as a reaction gas is stacked to a thickness of 100 to 150 nm.

Next, an amorphous semiconductor film is formed over the base insulating film 101. The amorphous semiconductor film is formed with a thickness of 30 to 60 nm. The material of the amorphous semiconductor film is not limited, but is preferably a silicon or silicon germanium (Si _x Ge _1-x ; 0 <x <1, typically x = 0.001 to 0.05) alloy or the like It is good to form with. In this embodiment, an amorphous silicon film is formed using SiH ₄ gas by plasma CVD.

  In addition, since the base insulating film and the amorphous semiconductor film can be formed by the same film formation method, the base insulating film 101 and the amorphous semiconductor film can be continuously formed.

  Next, a crystalline semiconductor film obtained by performing a known crystallization treatment (laser crystallization method, thermal crystallization method, thermal crystallization method using a catalyst such as nickel) on the amorphous semiconductor film is desired. Patterned into a shape. In this embodiment, after a nickel-containing solution is held on an amorphous silicon film, dehydrogenation (500 ° C., 1 hour) is continued, and thermal crystallization (550 ° C., 4 hours) is performed. A crystalline silicon film is formed by performing laser annealing for improving the formation. Then, a patterning process using a photolithography method is performed on the crystalline silicon film to form the semiconductor layers 102 to 106.

  Further, after forming the semiconductor layers 102 to 106, an impurity element imparting p-type conductivity may be added in order to control the threshold value (Vth) of the n-channel TFT. As an impurity element imparting p-type to a semiconductor, periodic group 13 elements such as boron (B), aluminum (Al), and gallium (Ga) are known. In this embodiment, boron (B) is added.

When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO ₄ laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The practitioner may select the crystallization conditions as appropriate.

  Next, a gate insulating film 107 that covers the island-shaped semiconductor layers 102 to 106 is formed. The gate insulating film 107 is formed by a plasma CVD method or a sputtering method, and is formed of an insulating film containing silicon with a thickness of 40 to 150 nm. Needless to say, this gate insulating film can be formed using an insulating film containing silicon as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Ortho Silicate) and O ₂ are mixed by a plasma CVD method to a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0.5 to It can be formed by discharging at 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. after formation.

  Next, a first conductive film (TaN) 108 with a thickness of 20 to 100 nm and a second conductive film (W) 109 with a thickness of 100 to 400 nm are stacked over the gate insulating film 107. The conductive film for forming the gate electrode may be formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. The first conductive film is formed of a tantalum (Ta) film, the second conductive film is a W film, the first conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed. The first conductive film may be formed of a tantalum nitride (TaN) film, and the second conductive film may be a Cu film.

Next, resist masks 110 to 115 are formed using a photolithography method, and a first etching process is performed to form electrodes and wirings. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, and CF ₄ , Cl ₂ and O ₂ are used as etching gases, and the respective gas flow ratios are 25/25/10 (sccm). Etching is performed by generating 500 W of RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa to generate plasma. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under the first etching conditions to form a first conductive film having a first shape having a taper at the end.

Thereafter, the masks 110 to 115 made of resist are changed to the second etching conditions without removing them, CF ₄ and Cl ₂ are used as etching gases, and the respective gas flow ratios are set to 30/30 (sccm). Etching is performed for about 30 seconds by applying 500 W RF (13.56 MHz) power to the coil-type electrode at a pressure of 1 Pa to generate plasma. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.

  In the first etching process, by making the mask made of resist suitable, a conductive layer having a first shape with a tapered end is formed by the effect of a bias voltage applied to the substrate side. . The angle of this taper portion is 15 to 45 °. Thus, first shape conductive layers 117 to 122 (first conductive layers 117a to 122a and second conductive layers 117b to 122b) are formed by the first etching process. Reference numeral 116 denotes a gate insulating film, and a region that is not covered with the first shape conductive layers 117 to 122 is etched and thinned by about 20 to 50 nm.

Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type conductivity is added to the semiconductor layer (FIG. 7B). The doping process may be performed by ion doping or ion implantation. The conditions of the ion doping method are a dose amount of 1.5 × 10 ¹⁵ / cm ² and an acceleration voltage of 60 to 100 keV. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used. In this case, the conductive layers 117 to 121 serve as a mask for the impurity element imparting n-type, and the first concentration impurity regions 123 to 127 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the first concentration impurity regions 123 to 127 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

Next, a second etching process is performed as shown in FIG. 7C without removing the resist mask. CF ₄ , Cl _2, and O ₂ are used as etching gases, the gas flow ratio is 20/20/20 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa. To generate plasma and perform etching. 20 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. The W film is etched under this third etching condition. Thus, the W film is anisotropically etched under the third etching conditions to form second shape conductive layers 129 to 134.

The etching reaction by the mixed gas of CF ₄ and Cl ₂ with respect to the W film or the TaN film can be estimated from the generated radical or ion species and the vapor pressure of the reaction product. Comparing the vapor pressures of W and TaN fluoride and chloride, WF ₆ which is a fluoride of W is extremely high, and other WCl ₅ , TaF ₅ and TaCl ₅ are similar. Therefore, both the W film and the TaN film are etched with a mixed gas of CF ₄ and Cl ₂ . However, when an appropriate amount of O ₂ is added to this mixed gas, CF ₄ and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. On the other hand, TaN has a relatively small increase in etching rate even when F increases. Since TaN is more easily oxidized than W, the surface of TaN is somewhat oxidized by adding O ₂ . Since the TaN oxide does not react with fluorine or chlorine, the etching rate of the TaN film further decreases. Therefore, it is possible to make a difference in the etching rate between the W film and the TaN film, and the etching rate of the W film can be made larger than that of the TaN film.

Next, a second doping process is performed as shown in FIG. 8A without removing the resist mask. In this case, an impurity element imparting n-type conductivity is doped as a condition of a high acceleration voltage by lowering the dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 keV, and in this embodiment, the acceleration voltage is set to 90 keV. The impurity having the first concentration formed in FIG. 8B is performed at a dose of 1.5 × 10 ¹⁴ atoms / cm ² . A new impurity region is formed in the semiconductor layer inside the region. Doping is performed so that the second shape conductive layers 129 to 133 are used as masks against the impurity element, and the impurity element is also added to the semiconductor layer below the second shape first conductive layers 129 a to 133 a. To do.

  In this manner, the third concentration impurity regions 140 to 144 overlapping the second shape first conductive layers 129a to 133a and the first concentration impurity regions 145 to 149 and the third concentration impurity regions are disposed. The second concentration impurity regions 135 to 139 are formed.

Next, after removing the resist mask, new resist masks 150 and 151 are formed, and a third etching process is performed as shown in FIG. 8B. SF ₆ and Cl ₂ are used as etching gases, the respective gas flow ratios are 50/10 (sccm), and 500 W of RF (13.56 MHz) power is supplied to the coil-type electrode at a pressure of 1.3 Pa. Then, plasma is generated and etching is performed for about 30 seconds. 10 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Thus, the third shape conductive layers 152 to 155 are formed by etching the TaN film of the subsequent p-channel TFT and the TFT of the subsequent pixel portion under the third etching condition.

  Note that in this specification, for example, a later p-channel TFT refers to a TFT that is in the manufacturing process and functions as a p-channel TFT after completion. Applicable to any TFT.

Then, after removing the resist mask, the gate insulating film is etched as shown in FIG. Etching was performed using CHF ₃ as an etching gas, generating a plasma by applying RF power of 35 sccm and a gas flow rate of 800 W. Here, the second shape conductive layers 129 and 131 and the third shape conductive layers 152 to 155 serve as a mask, and the gate insulating film is cut for each TFT (157 to 162).

Next, resist masks 164 to 166 are newly formed, and a third doping process is performed as shown in FIG. By this third doping treatment, fourth concentration impurity regions 167 to 172 in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to the semiconductor layer serving as the active layer of the p-channel TFT are formed. Form. Using the third shape conductive layers 152 and 154 as masks against the impurity element, an impurity element imparting p-type conductivity is added to form a fourth concentration impurity region in a self-aligning manner. In this embodiment, the fourth concentration impurity regions 167 to 172 are formed by an ion doping method using diborane (B ₂ H ₆ ). In the third doping process, the semiconductor layer forming the n-channel TFT is covered with masks 164 to 166 made of resist. Phosphorus is added to the fourth concentration impurity regions 167 to 172 at different concentrations by the first doping treatment and the second doping treatment, but the impurity element imparting p-type in any of the regions. By performing the doping process so that the concentration of the p-type TFT becomes higher, no problem arises because it functions as the source region and the drain region of the p-channel TFT.

  Through the above steps, impurity regions are formed in the respective semiconductor layers. In this example, all impurity regions were formed in a self-aligned manner using the conductive layer as a mask. The third shape conductive layers 129, 130, 152, and 153 overlapping with the semiconductor layer function as gate electrodes. Reference numeral 155 functions as a source wiring, and reference numeral 154 functions as a capacitor wiring serving as one electrode of a storage capacitor.

  Next, the resist masks 164 to 166 are removed, and a first interlayer insulating film 173 covering the entire surface is formed. The first interlayer insulating film 173 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film with a thickness of 150 nm is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 173 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

  Next, as shown in FIG. 9B, a step of activating the impurity element added to each semiconductor layer is performed. This activation process is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere having an oxygen concentration of 100 ppm or less, preferably 0.1 ppm or less. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

  In this embodiment, simultaneously with the activation treatment, nickel used as a catalyst during crystallization is gettered to the regions 145 to 149, 167, and 170 containing phosphorus at a high concentration, and mainly the channel formation region. The nickel concentration in the semiconductor layer is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.

  Next, a second interlayer insulating film 174 made of an organic insulating material is formed on the first interlayer insulating film 173. Next, patterning is performed to form contact holes that reach the source wiring 155 and contact holes that reach the impurity regions 145, 147, 148 a, 167, and 170.

  In the driver circuit 1406, wirings 175 to 180 that are electrically connected to the first concentration impurity region or the fourth concentration impurity region are formed. These wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 to 250 nm and an alloy film (alloy film of Al and Ti) having a thickness of 300 to 500 nm.

  In the pixel portion 1407, a pixel electrode 183, a gate line 182, and a connection electrode 181 are formed (FIG. 9C). With this connection electrode 181, the source line 155 is electrically connected to the pixel TFT 1404. In addition, the gate line 182 is electrically connected to the third shape conductive layer (gate electrode of the pixel TFT) 153. In addition, the pixel electrode 183 is electrically connected to a drain region of the pixel TFT, and is further electrically connected to a semiconductor layer functioning as one electrode forming a storage capacitor. Further, as the pixel electrode 183, it is desirable to use a material having excellent reflectivity, such as a film containing Al or Ag as a main component or a laminated film thereof.

  As described above, the driver circuit 1406 including the n-channel TFT 1401, the p-channel TFT 1402, and the n-channel TFT 1403, and the pixel portion 1407 including the pixel TFT 1404 and the storage capacitor 1405 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

The n-channel TFT 1401 of the driver circuit 1406 is formed outside the channel formation region 184, the third concentration impurity region 140 (GOLD region) overlapping the third shape conductive layer 129 forming the gate electrode, and the gate electrode. It has a second concentration impurity region 135 (LDD region) and a first concentration impurity region 145 functioning as a source region or a drain region. The p-channel TFT 1402 includes a channel formation region 185, fourth concentration impurity regions 168 and 169 formed outside the gate electrode, and a fourth concentration impurity region 167 functioning as a source region or a drain region. Yes. The n-channel TFT 1403 includes a channel formation region 186, a third concentration impurity region 142 (GOLD region) overlapping with the third shape conductive layer 131 forming the gate electrode, and a second region formed outside the gate electrode. An impurity region 137 (LDD region) having a concentration and a first concentration impurity region 147 functioning as a source region or a drain region are provided.

  The pixel TFT 1404 in the pixel portion functions as a channel formation region 187, a third concentration impurity region 143 formed outside the gate electrode, a second concentration impurity region 138 (both LDD regions), and a source region or a drain region. The first concentration impurity region 148a is provided. In addition, an impurity element imparting p-type conductivity is added to each of the semiconductor layers 170 to 172 functioning as one electrode of the storage capacitor 1405 at the same concentration as the impurity region having the fourth concentration. The storage capacitor 1405 is formed of a capacitor wiring 154 and semiconductor layers 170 to 172 using an insulating film (the same film as the gate insulating film) as a dielectric.

  In this embodiment, the structure of the TFT forming each circuit can be optimized according to the circuit specifications required by the pixel portion and the driver circuit, and the operation performance and reliability of the semiconductor device can be improved. Specifically, n-channel TFTs use different LDD or GOLD structures depending on circuit specifications, so that TFT structures that emphasize high-speed operation or hot carrier countermeasures on the same substrate and TFTs that emphasize low off-current operation The structure can be realized.

  For example, in the case of an active matrix liquid crystal display device, the n-channel TFTs 1401 and 1403 are suitable for driving circuits such as a shift register, a frequency dividing circuit, a signal dividing circuit, a level shifter, and a buffer that place importance on high-speed operation. In other words, by forming the GOLD region, it has a structure that emphasizes hot carrier countermeasures.

  The pixel TFT 1404 is an n-channel TFT and has a structure in which low off-current operation is emphasized. Therefore, it is suitable for a sampling circuit in addition to the pixel portion. That is, a low off-current operation is realized by disposing an LDD region and an offset region without disposing a GOLD region that can increase the off-current value. Further, it has been confirmed that the impurity region 148b having the first concentration is very effective in reducing the off-current value.

  A top view of the pixel portion of the active matrix substrate manufactured in this embodiment is shown in FIG. In addition, the same code | symbol is used for the part corresponding to FIGS. A chain line A-A ′ in FIG. 10 corresponds to a cross-sectional view taken along the chain line A-A ′ in FIG. 9. Further, a chain line B-B ′ in FIG. 10 corresponds to a cross-sectional view taken along the chain line B-B ′ in FIG. 9.

  As described above, the active matrix substrate having the pixel structure of this embodiment is characterized in that a part of the gate electrode 153 of the pixel TFT and the gate line 182 are formed in different layers, and the semiconductor layer is shielded by the gate line 182. It is said.

  In the pixel structure of this embodiment, the end of the pixel electrode overlaps with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.

  In addition, it is desirable to increase the whiteness by making the surface of the pixel electrode of this embodiment uneven by a known method such as a sand blasting method or an etching method to prevent specular reflection and scattering the reflected light.

  With the above pixel structure, a pixel electrode having a large area can be arranged, and the aperture ratio can be improved.

  Further, according to the process shown in this embodiment, the number of photomasks necessary for manufacturing the active matrix substrate is six (semiconductor layer pattern mask, first wiring pattern mask (pixel TFT gate electrode 153, capacitor wiring 154, Source line 155), p-channel TFT and pixel portion TFT pattern mask, p-channel TFT source region and drain region pattern mask, contact hole pattern mask, second wiring pattern mask (Including the pixel electrode 183, the connection electrode 181, and the gate line 182)). As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.

  FIG. 11 is a cross-sectional view of an active matrix substrate suitable for a transmissive liquid crystal display device. The processes up to the formation of the second interlayer film are the same as those of the reflection type. A transparent conductive film is formed on the second interlayer film. Then, patterning is performed to form the transparent conductive film layer 191. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used.

  Then, wirings 175 to 180 that are electrically connected to the first concentration impurity region or the fourth concentration impurity region in the driver circuit 1406 are formed. These wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 to 250 nm and an alloy (alloy film of Al and Ti) having a thickness of 300 to 500 nm. In the pixel portion 1407, a pixel electrode 191, a gate line 182, and connection electrodes 192 and 193 are formed. The connection electrodes 192 and 193 are formed so as to overlap the pixel electrode 191. In this manner, an active matrix substrate suitable for a transmissive liquid crystal display device can be manufactured by increasing the number of masks by one.

  Further, the characteristics of the TFT obtained by this example showed good values. Of these, the TFT characteristics (VI characteristics) of the pixel TFT are shown in FIG. Although gate leakage is also shown in the figure, it is sufficiently suppressed. In particular, the pixel TFT structure of the present invention is a structure that suppresses off-current and exhibits excellent mobility. The off current is a drain current that flows when the TFT is in an off state.

  FIG. 37 shows VI characteristic graphs of Samples 1 to 8. Of these, TFT characteristics of Sample 3 are shown in FIG.

By adopting the structure of the present invention, the threshold value (Vth) indicating the voltage value at the rising point in the VI characteristic graph is 0.263 V, which is a very small and good value. It can be said that the smaller this difference is, the more the short channel effect is suppressed. The mobility (μ _FE ), which is a parameter indicating the ease of carrier movement, is excellent at 119.2 (cm ² / Vs). The S value (subthreshold coefficient) indicating the reciprocal of the maximum slope at the rising portion of the IV curve was 0.196 (V / decade). Moreover, the off current when VD = 5V (I _OFF2) is 0.39PA, on current (I _ON2) shows 70Myuei. The on-current is a drain current that flows when the TFT is in an on state. Shift-1 indicates the voltage value at the rise of the IV curve.
As described above, by using the present invention, a semiconductor device having favorable characteristics can be realized.

  FIG. 39 shows a p-channel TFT 2100 and an n-channel TFT 2200 of an inverter circuit manufactured using the present invention. These TFTs are formed on a substrate 2001 on which a base insulating film 2002 is formed.

  The p-channel TFT 2100 includes a semiconductor layer 2003, a gate insulating film 2021, and a gate electrode including a first conductive layer 2005a and a second conductive layer 2005b. In the semiconductor layer 2003, a channel formation region 2012, a source region 2013, a drain region 2014, and an LDD region 2015 between the drain region and the channel formation region are formed.

  In the gate electrode, the end portion where the first conductive film 2005a and the second conductive film 2005b are in contact with each other on the source region side is approximately the same, but the end portion of the first conductive layer 2005a is formed outside on the drain region side. Has been. Such a structure can be realized by forming a resist mask formed in the third etching process of FIG. 8B so as to cover only one side of the gate electrode.

  In the p-channel TFT, after that, a p-type impurity element is added by an ion doping method or the like, and an impurity region is formed in the semiconductor layer 2003. The LDD region 2015 can be formed using the first conductive layer 2005a as a mask. In the ion doping method, it is possible to form both the source region and the drain region and the LDD region by a single doping process by controlling the acceleration voltage. You may form by a doping process.

  On the other hand, the n-channel TFT 2200 includes a semiconductor layer 2004, a gate insulating film 2022, and a gate electrode including a first conductive film 2006a and a second conductive film 2006b. In the semiconductor layer 2004, a channel formation region 2016, a source region 2017, a drain region 2018, and LDD regions 2019 and 2020 are formed.

  Similarly, in the gate electrode of the n-channel TFT 2200, the end portion where the first conductive film 2006a and the second conductive film 2006b are in contact with each other on the source region side is substantially coincident, and the end portion of the first conductive film 2006a is on the drain region side. Is formed on the outside. The LDD region 2019 on the source region side is an LDD that does not overlap with the gate electrode, and the LDD region 2020 on the drain side overlaps with the gate electrode.

  In this way, by forming the LDD overlapping the gate electrode on the drain side in the p-channel TFT and the n-channel TFT, the electric field strength in the vicinity of the drain is relaxed and the TFT deterioration due to the hot carrier effect is prevented. Can do. In particular, when the channel length becomes a submicron size, the effect is also required for the p-channel TFT.

  However, since the LDD region overlapping with the gate electrode increases the parasitic capacitance applied to the gate electrode, it is not always necessary to provide the LDD region on the source side where it is not necessary to relax the electric field.

  According to the present invention, as shown in FIG. 39, the LDD region can be formed only on the drain side. In addition, since the source region, the drain region, and the LDD region can all be formed in a self-aligned manner, it is possible to easily cope with miniaturization of design rules.

  The configuration of the TFT shown in this embodiment can be used particularly effectively for a TFT in which the position of the drain region is determined in advance, such as an inverter circuit. Further, such a TFT structure can be freely incorporated into the process shown in Embodiment 1 only by changing the mask pattern with a resist.

  In the p-channel TFT and the n-channel TFT of the inverter circuit shown in Embodiment 2, when the driving voltage is 10 V or less, degradation due to the hot carrier effect does not appear significantly, so that the LDD region overlapping with the gate electrode Is not necessarily formed. In that case, the p-channel TFT has the same structure as the p-channel TFT 402 shown in FIG. Further, the n-channel TFT has the same structure as the n-channel TFT 404 shown in FIG. 11, and may be formed with a single gate structure.

  In the active matrix substrate described in Embodiment 1, when the channel length is 0.6 μm or less, it is desirable to form an LDD region overlapping with the gate electrode also in the p-channel TFT. In that case, the LDD region can be formed in the same manner as the n-channel TFT 1401 shown in FIG. 11 and a p-type impurity is applied to the impurity element to be added. In addition, the LDD region may be provided on one side on the drain side as shown in the second embodiment when the source and drain directions are determined in advance like a shift register circuit or a buffer circuit.

  In this embodiment, the case where a TFT is manufactured in a process order different from that in Embodiment 1 will be described with reference to FIGS. In addition, since only the process in the middle differs from Example 1 and others are the same, the same code | symbol shall be used about the same process. The impurity element to be added is the same impurity element as in Example 1.

  First, in accordance with the manufacturing process shown in Embodiment 1, the first etching process and the first doping process are performed to form the state shown in FIG.

Thereafter, the resist masks 110 to 115 are not removed but the second etching conditions are changed, CF ₄ and Cl ₂ are used as etching gases, and the respective gas flow ratios are set to 30/30 (SCCM). The plasma is generated by applying 500 W RF (13.56 MHz) power to the coil-type electrode at a pressure of about 30 seconds, and etching is performed for about 30 seconds. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the conductive film (A) TaN film and the conductive film (B) W film are etched to the same extent, and the first conductive films 217a to 223a having the first shape are etched. Then, a first shape gate electrode and wirings 217 to 223 made of the first shape second conductive films 217b to 223b are formed.

  The second doping process is performed without removing the masks 110 to 115 made of resist. An impurity element imparting n-type conductivity (hereinafter referred to as an n-type impurity element) is added to the semiconductor layers 102 to 106. The doping process may be performed by an ion doping method or an ion implantation method. As the n-type impurity element, an element belonging to Group 15 of the periodic table, typically an element such as phosphorus (P) or arsenic (As) is used. In this case, first-concentration impurity regions 224a to 224e are formed in a self-aligning manner using the first shape gate electrode and the capacitor wirings 217 to 221 as a mask (FIG. 12A).

Next, a third etching process is performed with the masks 110 to 115 made of resist intact. CF ₄ , Cl _2, and O ₂ are used as etching gases, the gas flow ratio is 20/20/20 (SCCM), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.0 Pa. To generate plasma and perform etching. On the substrate side (sample stage), 20 W of RF (13.56 MHz) power is applied and etching is performed for about 80 seconds. As a result, second shape gate electrodes and wirings 225 to 231 formed of the second shape first conductive films 225a to 231a and the second shape second conductive films 225b to 231b are formed.

Next, using the resist-made masks 110 to 115 as they are, the second shape conductive layer and the capacitor wirings 225 to 229 are used as masks, and n is also formed below the second shape first conductive film (TaN film). A third doping process is performed so that the type impurity element is added. By this process, the second concentration impurity regions 232a to 232e having an n-type impurity element concentration of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ³ are formed between the impurity region of the first concentration and the channel formation region. It is formed. Further, the n-type impurity element concentration of the first concentration impurity regions 224a to 224e is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (FIG. 12B).

Next, the masks 110 to 115 made of resist are removed, masks 233 and 234 made of resist covering the subsequent n-channel TFT and the subsequent pixel TFT are formed, and a fourth doping process is performed. Using the second shape conductive layers 226 and 227 and the capacitor wiring 229 as a mask, a p-type impurity element is added to the semiconductor layers of the later first p-channel TFT and the later second p-channel TFT, The fourth concentration impurity regions 235a to 235c and the fifth concentration impurity regions 235d to 235f are formed in a self-aligning manner. In the present embodiment, the p-type impurity region is formed by ion doping using diborane (B ₂ H ₆ ). The p-type impurity element concentration of the fourth concentration impurity regions (p ⁺ ) 235a to 235c is 2 × 10 ²⁰ to 2 × 10 ²¹ atoms / cm ³ , and the p-type impurity of the fifth concentration impurity regions 235d to 235f is Element concentration is 2 × 10 ¹⁷ to 2 ×
10 ¹⁹ atoms / cm ³ . Note that an n-type impurity element is added to the semiconductor layer of the p-channel TFT in advance, but the doping process is performed so that the concentration of the p-type impurity element added in the fourth doping process is higher. By doing so, no problem arises because it functions as a source region and a drain region of a later p-channel TFT (FIG. 13A).

Next, the n-channel TFT and the first p-channel TFT of the driver circuit are covered with resist masks 236 and 237, and a fourth etching process is performed. The etching gas is Cl ₂ , the gas flow rate is 80 (SCCM), and 350 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa to generate a plasma. Etching is performed for 30 seconds. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Thus, the third shape conductive layer (the third shape first conductive films 238a to 239a and the third shape second conductive film is formed on the second p-channel TFT of the driver circuit and the pixel TFT of the pixel portion. 238, 239), capacitor wiring 240, and wirings 241, 242 are formed (FIG. 13B). Note that the exposed region where the third shape conductive layer of the gate insulating film is not formed by the above processing has a thickness of about 30 nm for the pixel portion and about 40 nm for the drive circuit.

  Through the above steps, impurity regions are formed in the respective semiconductor layers. Thereafter, the active matrix substrate may be manufactured according to the steps after forming the inorganic interlayer insulating film disclosed in the first embodiment.

  This embodiment can be easily realized by manufacturing a TFT according to the manufacturing process disclosed in Embodiment 1. Further, in this embodiment, only the configuration of the pixel TFT and the control circuit is shown. However, according to the manufacturing process of Embodiment 1, in addition to the signal dividing circuit, the frequency dividing circuit, the D / A converter circuit, the operational amplifier circuit, A gamma correction circuit and a signal processing circuit (also referred to as a logic circuit) such as a memory circuit or a microprocessor circuit can be provided over the same substrate.

  In this embodiment, the case where a TFT is manufactured in a process order different from that in Embodiment 1 will be described with reference to FIGS. In addition, since only the process in the middle differs from Example 1 and others are the same, the same code | symbol shall be used about the same process. The impurity element to be added is the same impurity element as in Example 1.

First, in accordance with the manufacturing process shown in Embodiment 1, the first etching process and the first doping process are performed to form the state shown in FIG. Next, a second etching process is performed. CF ₄ , Cl ₂ and O ₂ are used as etching gases, the respective gas flow ratios are 20/20/20 (SCCM), and 500 W RF (13.56 MHz) is applied to the coil-type electrode at a pressure of 1.0 Pa. Electric power is applied to generate plasma, and etching is performed for about 60 seconds. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias is applied. By the second etching process, second shape conductive layers 301 to 304 and wirings 305 to 307 as shown in FIG. 14A are formed.

Next, an n-type impurity element is added to the semiconductor layer through the second shape first conductive film in a self-aligning manner using the second shape second conductive film as a mask. As a result, the n-type impurity element concentration between the channel formation region and the first concentration impurity regions 308a to 308e is 1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ³ in the second concentration impurity regions 308f to 308f. 308j is formed. At this time, the concentration of the n-type impurity element in the first concentration impurity regions 308a to 308e is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ .

  Next, the resist masks 110 to 116 are removed, and masks 309 and 310 made of resist covering the n-channel TFT and the pixel TFT are newly formed, and a third doping process is performed. By this third doping treatment, a p-type impurity element is added to the semiconductor layer of the p-channel TFT in a self-aligning manner using the second shape conductive layer as a mask, and the fourth concentration impurity regions 311a to 311c and Impurity regions 311d to 311f having a concentration of 5 are formed (FIG. 14B).

Next, the resist masks 309 and 310 are removed, and new resist masks 312 and 313 are formed to cover the n-channel TFT and the second p-channel TFT. The etching gas is Cl ₂ , the gas flow rate is 80 (SCCM), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma. Etching is performed for about 40 seconds. 10 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Thus, in the first p-channel TFT and the pixel TFT, the third shape conductive layer (the first shape conductive films 314a to 315a and the third shape second conductive films 314b to 315b are formed. 314, 315 and wirings 316 to 318 are formed (FIG. 14C).

  By the third etching process, offset regions 311g and 311h are formed in the semiconductor layers of the first p-channel TFT and the pixel TFT. Note that in this specification, an offset region is a semiconductor layer having the same composition as a channel formation region (meaning that the contained impurity element is the same as the channel formation region) and does not overlap with the gate electrode. The offset regions 311g and 311h function as simple resistances and are very effective in reducing the off-current value.

  Thereafter, the active matrix substrate may be manufactured according to the steps after forming the inorganic interlayer insulating film disclosed in the first embodiment.

  This embodiment can be easily realized by manufacturing a TFT according to the manufacturing process disclosed in Embodiment 1. Further, in this embodiment, only the configuration of the pixel TFT and the control circuit is shown. However, according to the manufacturing process of Embodiment 1, in addition to the signal dividing circuit, the frequency dividing circuit, the D / A converter circuit, the operational amplifier circuit, A gamma correction circuit and a signal processing circuit (also referred to as a logic circuit) such as a memory circuit or a microprocessor circuit can be provided over the same substrate.

  In this embodiment, the case where a TFT is manufactured in a process order different from that in Embodiment 1 will be described with reference to FIGS. In addition, since only the process in the middle differs from Example 1 and others are the same, the same code | symbol shall be used about the same process.

First, in accordance with the manufacturing process shown in Example 1, the first etching process and the first doping process are performed to form the state shown in FIG. Next, a second etching process is performed. In the second etching process, CF ₄ , Cl _2, and O ₂ are used as the etching gas, the respective gas flow ratios are set to 20/20/20 (SCCM), and 500 W is applied to the coil-type electrode at a pressure of 1.0 Pa. RF (13.56 MHz) power is applied to generate plasma, and etching is performed for about 80 seconds. 20 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias is applied. Thus, the second shape conductive layer and wiring are formed.

  Next, a second doping process is performed by covering the n-channel TFT and the pixel TFT with resist masks 401 and 402. By this second doping process, a p-type impurity element is added to the semiconductor layer of the p-channel TFT. A p-type impurity element is added through the second shape first conductive film in a self-aligned manner using the second shape second conductive film as a mask, and fourth concentration impurity regions 403a to 403c and Impurity regions 403d-f having the fifth concentration are formed (FIG. 15A).

Next, a third etching process is performed by covering the n-channel TFT and the second p-channel TFT with masks 404 and 405 made of resist. The etching gas is Cl ₂ , the gas flow rate is 80 (SCCM), 500 W RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa, and plasma is generated to generate about 40 Second etching treatment was performed. 20 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias is applied. Thus, third shape conductive layers 406 and 407 and wirings 408 to 410 are formed (FIG. 15B).

  Subsequently, the resist masks 404 and 405 are removed, and a third doping process is performed. In the third doping process, an n-type impurity element is added. Note that since a p-type impurity element is added to the semiconductor layer of the p-channel TFT at a concentration higher than that of the n-type impurity element, there is no problem in functioning as a source region and a drain region of the p-channel TFT. Does not occur (FIG. 15C).

  When the steps so far are completed, the active matrix substrate may be manufactured according to the steps after the step of forming the inorganic interlayer insulating film disclosed in the first embodiment.

  This embodiment can be easily realized by manufacturing a TFT according to the manufacturing process disclosed in Embodiment 1. Further, in this embodiment, only the configuration of the pixel TFT and the control circuit is shown. However, according to the manufacturing process of Embodiment 1, in addition to the signal dividing circuit, the frequency dividing circuit, the D / A converter circuit, the operational amplifier circuit, A gamma correction circuit and a signal processing circuit (also referred to as a logic circuit) such as a memory circuit or a microprocessor circuit can be provided over the same substrate.

  In this embodiment, the case where a TFT is manufactured in a process order different from that in Embodiment 1 will be described with reference to FIGS. In addition, since only the process in the middle differs from Example 1 and others are the same, the same code | symbol shall be used about the same process.

  First, in accordance with the manufacturing process shown in Example 1, the second etching process and the second doping process are performed to form the state shown in FIG.

Next, a resist mask 501 is formed to cover the n-channel TFT, and a third etching process is performed. In the third etching process, Cl ₂ is used as an etching gas, the gas flow rate is 80 (SCCM), and 350 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa. Plasma is generated and etching is performed for about 40 seconds. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Thus, the third shape conductive layer and wirings 502 to 507 are formed (FIG. 16B).

After removing the resist mask, the gate insulating film is etched. Etching is performed by using an etching gas CHF _3, setting the gas flow rate to 35 (SCCM), and applying 800 W of RF (13.56 MHz) power to generate plasma. Here, the n-channel TFT has a second shape gate electrode, and the other has a third shape conductive layer and capacitor wiring as a mask, and the gate insulating film is cut for each TFT, and the gate insulating films 508 to 514. Is formed (FIG. 16C).

  Next, masks 515 and 516 made of resist are newly formed, and a third doping process is performed. By the third doping treatment, a p-type impurity element is added to the semiconductor layer of the p-channel TFT, and the fourth concentration impurity region 517a is formed in a self-aligning manner using the third shape gate electrode and the capacitor wiring as a mask. To 517c and fifth concentration impurity regions 517d to 517f are formed (FIG. 17).

  When the steps so far are completed, the active matrix substrate may be manufactured according to the steps after the step of forming the inorganic interlayer insulating film disclosed in the first embodiment. This embodiment can be easily realized by manufacturing a TFT according to the manufacturing process disclosed in Embodiment 1. Further, in this embodiment, only the configuration of the pixel TFT and the control circuit is shown. However, according to the manufacturing process of Embodiment 1, in addition to the signal dividing circuit, the frequency dividing circuit, the D / A converter circuit, the operational amplifier circuit, A gamma correction circuit and a signal processing circuit (also referred to as a logic circuit) such as a memory circuit or a microprocessor circuit can be provided over the same substrate.

  In this embodiment, the case where a TFT is manufactured in a process order different from that in Embodiment 1 will be described with reference to FIGS. In addition, since only the process in the middle differs from Example 1 and others are the same, the same code | symbol shall be used about the same process.

  First, according to the manufacturing process shown in Embodiment 1, the second etching process and the second doping process are performed, and the process up to the process of forming the second shape conductive layer and the wiring in FIG.

Next, the n-channel TFT is covered with a resist mask 601 and a third etching process is performed. Cl ₂ is used as an etching gas, the gas flow rate is 80 (SCCM), and 350 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma to generate about 40 Etch second. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Thus, conductive layers and wirings 602 to 607 having a third shape are formed (FIG. 18B).

  Next, the resist mask 601 is removed, and new resist masks 608 and 609 are formed to cover the n-channel TFT and the pixel TFT, and a third doping process is performed. A p-type impurity element is added to form fourth concentration p-type impurity regions 610a to 610c and fifth concentration impurity regions 610d to 610f (FIG. 18C).

  When the steps so far are completed, the active matrix substrate may be manufactured according to the steps after the step of forming the inorganic interlayer insulating film disclosed in the first embodiment.

  This embodiment can be easily realized by manufacturing a TFT in accordance with the manufacturing process disclosed in Embodiment 1. Further, in this embodiment, only the configuration of the pixel TFT and the control circuit is shown. However, according to the manufacturing process of Embodiment 1, in addition to the signal dividing circuit, the frequency dividing circuit, the D / A converter circuit, the operational amplifier circuit, A gamma correction circuit and a signal processing circuit (also referred to as a logic circuit) such as a memory circuit or a microprocessor circuit can be provided over the same substrate.

  In this embodiment, the case where a TFT is manufactured in a process order different from that in Embodiment 1 will be described with reference to FIGS. In addition, since only the process in the middle differs from Example 1 and others are the same, the same code | symbol shall be used about the same process.

First, in accordance with the manufacturing process shown in Example 1, the first etching process and the first doping process are performed to form the state shown in FIG. Next, a second etching process is performed. In the second etching process, CF ₄ and Cl ₂ are used as etching gases as the first etching conditions, the flow rate ratio of each gas is 30/30 (SCCM), and the pressure of 1.0 Pa is a coil type. 500 W RF (13.56 MHz) power is applied to the electrode to generate plasma and perform etching for about 30 seconds. 20 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias is applied (FIG. 19B). Subsequently, as the second etching condition, CF ₄ , Cl ₂ and O ₂ are used as etching gases, the flow rate ratio of each gas is 20/20/20 (SCCM), and the coil type is used at a pressure of 1.0 Pa. 500 W RF (13.56 MHz) power is applied to the electrode to generate plasma, and etching is performed for about 60 seconds. 20 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias is applied. Thus, conductive layers and wirings 701 to 707 having the second shape are formed (FIG. 19C).

Next, a second doping process is performed. An n-type impurity element is added, and the second-shaped gate electrode and capacitor wiring are used as a mask, and the n-type impurity element concentration is 1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ³ . Regions 708a to 708e are formed in a self-aligning manner. At this time, the n-type impurity element concentration in the first concentration impurity region is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (FIG. 20A).

In this embodiment, the conductive film is etched in two stages in the second etching process, and the first conductive film recedes in the etching process under the first condition, so that the gate electrode passes through the gate insulating film. An L _ov region that overlaps with the second concentration impurity region and an L _off region 719 that does not overlap with the second concentration impurity region are formed.

Next, a resist mask 709 is formed to cover the n-channel TFT, and a third etching process is performed. In the third etching process, Cl ₂ is used as an etching gas, the gas flow rate is 80 (SCCM), and 350 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa. Plasma is generated and etching is performed for about 40 seconds. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Thus, third shape conductive layers and wirings 710 to 715 are formed (FIG. 20B).

  Next, resist masks 716 and 717 are newly formed to cover the n-channel TFT and the pixel TFT, and a third doping process is performed. By the third doping treatment, a p-type impurity element is added to the semiconductor layer of the p-channel TFT, and the fourth concentration impurity region 718a is self-aligned using the third shape conductive layer and the capacitor wiring as a mask. To 718c and fifth concentration impurity regions 718d to 718f are formed (FIG. 20C).

  When the steps so far are completed, the active matrix substrate may be manufactured according to the steps after the step of forming the inorganic interlayer insulating film disclosed in Embodiment 1.

  This embodiment can be easily realized by manufacturing a TFT in accordance with the manufacturing process disclosed in Embodiment 1. Further, in this embodiment, only the configuration of the pixel TFT and the control circuit is shown. However, according to the manufacturing process of Embodiment 1, in addition to the signal dividing circuit, the frequency dividing circuit, the D / A converter circuit, the operational amplifier circuit, A gamma correction circuit and a signal processing circuit (also referred to as a logic circuit) such as a memory circuit or a microprocessor circuit can be provided over the same substrate.

  In this embodiment, the case where a TFT is manufactured in a process order different from that in Embodiment 1 will be described with reference to FIGS. In addition, since only the process in the middle differs from Example 1 and others are the same, the same code | symbol shall be used about the same process.

  First, in accordance with the manufacturing process shown in Embodiment 1, the second etching process and the second doping process are performed so that the second shape conductive layer and the wiring in FIG. 7C are formed.

Next, resist masks 801 and 802 are formed, covering the subsequent n-channel TFT and the subsequent second p-channel TFT, and performing a third etching process. In the third etching process, Cl ₂ is used as an etching gas, the gas flow rate is 80 (SCCM), and 350 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa. Plasma is generated and etching is performed for about 40 seconds. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Thus, third shape conductive layers and wirings 803 to 807 are formed (FIG. 21B).

  After removing the resist masks 801 and 802, new resist masks 808 and 809 are formed to cover the n-channel TFT and the pixel TFT, and a third doping process is performed. By the third doping treatment, a p-type impurity element is added to the semiconductor layer of the p-channel TFT, and the fourth concentration impurity region 810a is self-aligned using the third shape conductive layer and the capacitor wiring as a mask. To c and fifth concentration impurity regions 810d to 810f are formed (FIG. 21C).

  When the steps so far are completed, the active matrix substrate may be manufactured according to the steps after the step of forming the inorganic interlayer insulating film disclosed in the first embodiment.

  In this embodiment mode, results of measuring characteristics of a TFT manufactured according to the manufacturing method disclosed in this specification are shown.

  First, a graph showing the relationship between the drain current (Id) and the gate voltage (Vg) of a pixel TFT (n-channel TFT) manufactured according to the manufacturing method described in Example 5 (hereinafter referred to as Id-Vg curve). ) Is shown in FIG. In the measurement, the source voltage (Vs) was 0 V, and the drain voltage (Vd) was 1 V or 14 V. The measured values are a channel length (L) of 6 μm and a channel width (W) of 4 μm.

  The off-current (Ioff) at Vd = 14 V was 0.5 pA.

Next, FIG. 41 shows Id-Vg curves of the pixel TFT obtained by the manufacturing method shown in Example 8 and the first p-channel TFT of the driver circuit.
In the measurement, the source voltage (Vs) was 0 V, and the drain voltage (Vd) was 1 V or 14 V. The measured values are as follows: the pixel TFT has a channel length (L) of 6 μm and a channel width (W) of 4 μm, and the first p-channel TFT has a channel length (L) of 7 μm and a channel width (W) of 8 μm.

  The pixel TFT had an off current (Ioff) of 0.3 pA when Vd = 14 V, and the first p-channel TFT had 2 pA. Compared with a p-channel TFT without an offset region, the jump of Ioff when Vg is high was suppressed.

For n-channel TFTs manufactured according to other embodiments, Ioff = 10 to 30 (pA), field effect mobility 130 to 180 (cm ² / Vs), S value 0.19 to 0.26 ( V / dec), p-channel TFT, Ioff = 2 to 10 (pA), field effect mobility 70 to 110 (cm ² / Vs), S value 0.19 to 0.25 (V / dec), pixel Regarding the TFT, good characteristics of Ioff = 2 to 10 (pA), field effect mobility of 70 to 150 (cm ² / Vs), and S value of 0.16 to 0.24 (V / dec) were obtained.

  Next, the result of measuring the reliability will be shown.

Reliability is evaluated by examining the 10-year warranty voltage. The 10-year guaranteed voltage is obtained by plotting the reciprocal of the stress voltage on a semi-logarithmic graph when the lifetime until the maximum value of the mobility of the TFT (μFE _(max) ) fluctuates by 10% is defined as the lifetime. The stress voltage having a lifetime of 10 years is estimated from the linear relationship obtained. Measurement was performed on the TFT (driving circuit) manufactured according to the manufacturing method of Embodiment 1, and as shown in FIG. 42, the 10-year guaranteed voltage was 20 V or more, indicating a very high reliability.

  Next, in order to investigate the 1000-hour lifetime temperature due to on-stress, when Vg = + 20 V (p-channel TFT has the opposite sign) and Vd = 0 V, the time until the TFT characteristic (Shift_1) fluctuates by 0.1 V is set to 1000 / Plotting with respect to T (T: absolute temperature (K)), the temperature (life temperature) fluctuating by 0.1 V in 1000 hours was estimated. As shown in FIG. 43, the lifetime temperature in 1000 hours was 80 ° C. or more for both the n-channel TFT and the p-channel TFT.

  Next, in order to investigate the 1000-hour lifetime temperature due to off-stress, the time until the TFT characteristic (Shift_1) fluctuates by 0.1 V at Vg = 0 V and Vd = + 20 V (p-channel TFT has the opposite sign) is 1000 / T. Plotting against (T: absolute temperature (K)), the temperature (life temperature) fluctuating by 0.1 V in 1000 hours was estimated. As shown in FIG. 44, the lifetime temperature at 1000 hours was 80 ° C. or more for both the n-channel TFT and the p-channel TFT.

Next, in order to investigate the characteristic fluctuation of the n-channel TFT and the characteristic fluctuation of the p-channel TFT due to the transient stress, Vd = + 20V (p-channel TFT is reverse sign), Vg = 2-6V (p-channel TFT is reverse) ), The on-characteristic variation after 20 hours (room temperature) is observed. (Here, the transient stress refers to this stress when the drain voltage is set to a certain value, the gate voltage is set to a certain value, and stress is applied.)
45A and 45B, it was confirmed that the variation in the maximum value of field effect mobility after 20 hours was suppressed to 10% or less for both the n-channel TFT and the p-channel TFT.

  From these results, it was found that according to the manufacturing method disclosed in the present invention, it is possible to manufacture a TFT with high reliability and required performance without increasing the number of steps without increasing the number of manufacturing steps. .

  In this embodiment, a process of manufacturing an active matrix liquid crystal display device from an active matrix substrate manufactured according to any of the processes shown in Embodiments 1 and 5 to 11 will be described with reference to FIGS.

  First, an active matrix substrate as shown in FIG. 9C is obtained using any of the steps of Examples 1 to 8, and then an alignment film 1181 is formed on the active matrix substrate, and a rubbing process is performed. Note that in this embodiment, before forming the alignment film 1181, columnar spacers 1180 for maintaining a gap between the substrates are formed at desired positions by patterning an organic resin film such as an acrylic resin film. Further, in place of the columnar spacers, spherical spacers may be dispersed over the entire surface of the substrate.

  Next, a counter substrate 1182 is prepared. Color layers 1183 and 1184 and a planarization film 1185 are formed over the counter substrate 1182. A second light-shielding portion is formed by partially overlapping the red colored layer 1183 and the blue colored layer 1184. Although not shown in FIG. 22, the first light-shielding portion is formed by partially overlapping the red colored layer and the green colored layer.

  Next, a counter electrode 1186 was formed in the pixel portion, an alignment film 1187 was formed on the entire surface of the counter substrate 1182, and a rubbing process was performed.

  Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are bonded together with a sealant. A filler is mixed in the sealing material, and two substrates are bonded to each other while maintaining a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material 1188 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material 1188, and thus the active matrix liquid crystal display device shown in FIG. 22 is completed.

  By providing a colored layer as disclosed in this embodiment, it is possible to reduce the number of processes by shielding the gap between each pixel with the first light-shielding portion or the second light-shielding portion without forming a black mask. did.

  A block diagram of a semiconductor device manufactured using the present invention is shown in FIG. This embodiment shows a semiconductor device having a source side driver circuit 90, a pixel portion 91, and a gate side driver circuit 92. Note that in this specification, a driving circuit refers to a generic name including a source side driving circuit and a gate side driving circuit.

  The source side driver circuit 90 includes a shift register 90a, a buffer 90b, and a sampling circuit (transfer gate) 90c. The gate side driving circuit 92 includes a shift register 92a, a level shifter 92b, and a buffer 92c. Further, if necessary, a level shifter circuit may be provided between the sampling circuit and the shift register.

  In this embodiment, the pixel unit 91 includes a plurality of pixels, and each of the plurality of pixels includes a TFT element.

  Although not shown, a gate side drive circuit may be further provided on the opposite side of the gate side drive circuit 92 with the pixel portion 91 interposed therebetween.

  In the case of digital driving, as shown in FIG. 24, a latch (A) 93b and a latch (B) 93c may be provided instead of the sampling circuit. The source side driving circuit 93 includes a shift register 93a, a latch (A) 93b, a latch (B) 93c, a D / A converter 93d, and a buffer 93e. The gate side driving circuit 95 includes a shift register 95a, a level shifter 95b, and a buffer 95c. If necessary, a level shifter circuit may be provided between the latch (B) 93c and the D / A converter 93d. Reference numeral 94 denotes a pixel portion.

  In addition, the said structure is realizable by using the manufacturing process shown in Examples 1-8. In this embodiment, only the configuration of the pixel portion and the drive circuit is shown. However, according to the manufacturing process of the present invention, a memory and a microprocessor can be formed.

  In this embodiment, a process for forming a semiconductor film which becomes an active layer of a TFT will be described with reference to FIG. The crystallization means of this example is the technique described in Embodiment 1 of Japanese Patent Laid-Open No. 7-130652.

  First, a base insulating film 1402 made of a silicon nitride oxide film with a thickness of 200 nm and an amorphous semiconductor film (amorphous silicon film in this embodiment) 1403 with a thickness of 200 nm are formed over a substrate (a glass substrate in this embodiment) 1401. To do. In this step, the base insulating film and the amorphous semiconductor film may be formed continuously without being released to the atmosphere.

  Next, an aqueous solution (nickel acetate aqueous solution) containing 10 ppm of catalyst element (nickel in this embodiment) in terms of weight is applied by a spin coating method to form a catalyst element-containing layer 1404 on the entire surface of the amorphous semiconductor film 1403. To do. The catalyst elements that can be used here are iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu) in addition to nickel (Ni). ) And gold (Au) (FIG. 25A).

  In this embodiment, a method of adding nickel by a spin coating method is used. However, a thin film made of a catalytic element (in this embodiment, a nickel film) is deposited on an amorphous semiconductor film by vapor deposition or sputtering. You may take the means to form.

  Next, prior to the crystallization step, a heat treatment step is performed at 400 to 500 ° C. for about 1 hour to desorb hydrogen from the film, and then 4 to 500 to 650 ° C. (preferably 550 to 570 ° C.). Heat treatment is performed for -12 hours (preferably 4-6 hours). In this embodiment, a heat treatment is performed at 550 ° C. for 4 hours to form a crystalline semiconductor film (crystalline silicon film in this embodiment) 1405 (FIG. 25B).

  Note that the crystallinity of the crystalline semiconductor film 1405 may be improved by performing a laser light irradiation step here.

Next, a gettering step for removing nickel used in the crystallization step from the crystalline silicon film is performed. First, a mask insulating film 1406 is formed to a thickness of 150 nm on the surface of the crystalline semiconductor film 1405, and an opening 1407 is formed by patterning. Then, a step of adding an element belonging to Group 15 (phosphorus in this embodiment) to the exposed crystalline semiconductor film is performed. Through this step, a gettering region 1408 containing phosphorus at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm ³ is formed (FIG. 25C).

Next, a heat treatment step of 450 to 650 ° C. (preferably 500 to 550 ° C.) and 4 to 24 hours (preferably 6 to 12 hours) is performed in a nitrogen atmosphere. By this heat treatment process, nickel in the crystalline semiconductor film moves in the direction of the arrow and is captured in the gettering region 1408 by the gettering action of phosphorus. That is, since nickel is removed from the crystalline semiconductor film, the concentration of nickel contained in the crystalline semiconductor film 1409 is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ^3. To do.

The crystalline semiconductor film 1409 formed as described above is a semiconductor film having very good crystallinity by using a catalytic element that promotes crystallization. Further, the catalyst element is removed by a gettering action after crystallization, and the concentration of the catalyst element remaining in the crystalline semiconductor film 1409 (other than the gettering region) is 1 × 10 ¹⁷ atoms / cm ³ or less, preferably It is 1 × 10 ¹⁶ atoms / cm ³ .

  Note that after forming the inorganic interlayer insulating film in the manufacturing process shown in Embodiment 1, in the step of activating the impurity element added to the semiconductor film, phosphorus added to the source region or the drain region as an n-type impurity element is used. The catalytic element can also be gettered using (P).

  The configuration of this example can be freely combined with any of the configurations shown in Embodiment Mode 1 and Examples 1 to 8.

  In this embodiment, a process for forming a semiconductor film to be an active layer of a TFT will be described with reference to FIG. Specifically, the technique described in JP-A-10-247735 (USP 6165824) is used.

  First, a base insulating film 1502 made of a 200 nm-thick silicon nitride oxide film and a 200 nm-thick amorphous semiconductor film (amorphous silicon film in this embodiment) 1503 are formed over a substrate (glass substrate in this embodiment) 1501. To do. In this step, the base insulating film and the amorphous semiconductor film may be formed continuously without being released to the atmosphere.

  Next, a mask insulating film 1504 made of a silicon oxide film is formed to a thickness of 200 nm, and an opening 1505 is formed.

  Next, an aqueous solution (nickel acetate aqueous solution) containing 100 ppm of the catalyst element (nickel in this embodiment) in terms of weight is applied by a spin coating method to form the catalyst element-containing layer 1506. At this time, the catalyst element-containing layer 1506 selectively contacts the amorphous semiconductor film 1503 in the region where the opening 1505 is formed. The catalyst elements that can be used here are iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu) in addition to nickel (Ni). ) And gold (Au) (FIG. 26A).

  In this embodiment, a method of adding nickel by a spin coating method is used. However, a thin film made of a catalytic element (in this embodiment, a nickel film) is deposited on an amorphous semiconductor film by vapor deposition or sputtering. You may take the means to form.

  Next, prior to the crystallization step, a heat treatment step is performed at 400 to 500 ° C. for about 1 hour to desorb hydrogen from the film, and then at 500 to 650 ° C. (preferably 550 to 600 ° C.). Heat treatment is performed for -16 hours (preferably 8-14 hours). In this embodiment, heat treatment is performed at 570 ° C. for 14 hours. As a result, crystallization proceeds in a direction parallel to the substrate (in the direction indicated by the arrow) starting from the opening 1505, and a crystalline semiconductor film in which macroscopic crystal growth directions are aligned (in this embodiment, crystalline silicon film). Film) 1507 is formed (FIG. 26B).

Next, a gettering step for removing nickel used in the crystallization step from the crystalline silicon film is performed. In this embodiment, an element belonging to Group 15 (phosphorus in this embodiment) is added using the mask insulating film 1504 formed earlier as a mask, and 1 × 10 ^{19 is applied} to the crystalline semiconductor film exposed through the opening 1505. A gettering region 1508 containing phosphorus at a concentration of ˜1 × 10 ²⁰ atoms / cm ³ is formed (FIG. 26C).

Next, a heat treatment step of 450 to 650 ° C. (preferably 500 to 550 ° C.) and 4 to 24 hours (preferably 6 to 12 hours) is performed in a nitrogen atmosphere. Through this heat treatment process, nickel in the crystalline semiconductor film moves in the direction of the arrow and is captured in the gettering region 1508 by the gettering action of phosphorus. That is, since nickel is removed from the crystalline semiconductor film, the concentration of nickel contained in the crystalline semiconductor film 1509 is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ^3. (FIG. 26D).

  The crystalline semiconductor film 1509 formed as described above is crystallized by selectively adding a catalyst element (here, nickel) that promotes crystallization to crystallize the crystalline semiconductor film 1509. It is formed with. Specifically, it has a crystal structure in which rod-like or columnar crystals are arranged with a specific direction.

  Note that after forming the inorganic interlayer insulating film in the manufacturing process shown in Embodiment 1, in the step of activating the impurity element added to the semiconductor film, phosphorus added to the source region or the drain region as an n-type impurity element is used. The catalytic element can also be gettered using (P).

  The configuration of this example can be freely combined with any of the configurations shown in Embodiment Mode 1 and Examples 1 to 8.

  A TFT of a drive circuit is provided around the pixel portion on the same substrate, and a concavo-convex region is formed in the pixel portion in the same process as the TFT manufacturing process, and a concavo-convex pixel electrode is formed by the influence of the concavo-convex region. A method for manufacturing the semiconductor device is described.

  In this embodiment, a substrate 2100 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is used. Note that as the substrate 2100, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate with an insulating film formed thereon, or a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.

Next, a base insulating film 2101 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 2100. In this embodiment, as the first layer of the base insulating film 2101, a silicon oxynitride film (composition ratio: Si = 32%, O = 27) is formed by plasma CVD using SiH ₄ , NH ₃ , and N ₂ O as reaction gases. %, N = 24%, H = 17%) 2101a is formed to 10 to 200 nm (preferably 50 to 100 nm). Further, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%) is formed by plasma CVD using SiH ₄ and N ₂ O as reaction gases as a _second base insulating film. , H = 2%) 2101b is laminated to a thickness of 10 to 200 nm (preferably 100 to 150 nm).

  Next, an amorphous semiconductor film is formed over the base insulating film by a known means (such as sputtering, LPCVD, or plasma CVD). Thereafter, a crystalline semiconductor film obtained by performing a known crystallization process (laser crystallization, thermal crystallization method, thermal crystallization method using a catalytic element such as Ni) is patterned into a desired shape. The island-shaped semiconductor layers 2102 to 2105 and the island-shaped semiconductor layers 2301 (see FIG. 3A) that form convex portions in the pixel portion are formed. In this embodiment, in the following steps, the convex portions are formed according to the steps for manufacturing the pixel TFT.

There is no limitation on the material of the crystalline semiconductor film, but it is formed of a silicon or silicon germanium (Si _x Ge _1-x ; 0 <x <1, typically x = 0.001 to 0.05) alloy or the like. Is preferred.

  In this embodiment, a 55 nm amorphous silicon film is formed by plasma CVD, and then the silicon film is irradiated with a laser to form a crystalline silicon film. In the case of performing crystallization treatment by laser treatment, it is desirable to perform crystallization after performing a heat treatment at 400 to 500 ° C. for about 1 hour to reduce the hydrogen content of the semiconductor film to 5 atom% or less prior to the crystallization step. .

In addition, as a crystallization method, a solution containing Ni is applied on an amorphous silicon film, a thermal crystallization process (550 ° C., 4 hours) is performed, and a laser annealing process for further improving the crystallization is performed. Alternatively, a method of forming a crystalline silicon film may be employed. As a laser used at this time, a pulse transmission type or continuous emission type KrF excimer laser, XeCl excimer laser, YAG laser, or YVO ₄ laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser transmitter is linearly collected by an optical system and irradiated onto a semiconductor film. The practitioner may select the crystallization conditions as appropriate.

  Besides crystallization by adding a catalyst element and heating, crystallization may be performed by heating without adding a catalyst element. Further, heating may be performed by an RTA (Rapid Thermal Anneal) method (the crystallization temperature is about 500 to 700 ° C.). If laser annealing is performed after crystallization by the RTA method, the crystallinity of the semiconductor film can be further improved.

  In order to control the threshold value of the TFT in the semiconductor layer, a small amount of impurity element (boron or phosphorus: boron in this embodiment) may be doped.

  Next, a gate insulating film 2106 is formed to cover the semiconductor layers 2102 to 2105 and the island-shaped semiconductor layer 2301 that forms the protrusions. The gate insulating film 2106 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 110 nm is formed by plasma CVD. Needless to say, the gate insulating film is not limited to a silicon oxynitride film, and may be a single layer or a stacked structure containing other silicon.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method, the reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., the high frequency (13.56 MHz), and the power density is 0. It can be formed by discharging at 5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter.

Next, a first conductive film 2107 with a thickness of 20 to 100 nm and a second conductive film 2108 with a thickness of 100 to 400 nm are formed over the gate insulating film 2106. In this embodiment, a TaN film 2107 with a thickness of 30 nm and a W film 2108 with a thickness of 370 nm are formed. The TaN film was formed by sputtering using a Ta target in an atmosphere containing nitrogen. The W film was formed by sputtering using a W target. In addition, the film may be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ).

  In any case, it is necessary to reduce the resistance for use as a gate electrode, and the resistivity of the W film is preferably 20 μΩcm or less. Although the resistivity of the W film can be measured by increasing the crystal grains, if the W film contains a large amount of impurity elements such as oxygen, crystallization is hindered and the resistance is increased. Therefore, in this embodiment, the W film is formed by a sputtering method using a target of high purity W (purity 99.9999%) and with sufficient consideration so that impurities from the gas phase are not mixed during film formation. By forming the film, a resistivity of 9 to 20 μΩcm could be realized.

  In this embodiment, the first conductive film: TaN film 2107 and the second conductive film: W film 2108 are used, but there is no particular limitation, and all are Ta, W, Ti, Mo, Al, Cu. Or an alloy material or compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. The first conductive film 2107 is a Ta film, the second conductive film 2108 is a W film, the first conductive film 2107 is a TaN film, and the second conductive film 2108 is an Al film. A combination of various conductive films such as a combination in which the first conductive film 2107 is a TaN film and the second conductive film 2108 is a Cu film can be considered (FIG. 27A).

Next, resist masks 2109 to 2113 and a mask 2302 for forming convex portions are formed by photolithography, and a first etching process for forming electrodes and capacitor wirings is performed. In this example, an ICP (Inductively Coupled Plasma) etching method is used, CF ₄ , Cl ₂ and O ₂ are used as etching gases, and each gas flow ratio is 25/25/10 (SCCM). In this manner, 500 W of RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied.

Thereafter, instead of removing the resist masks 2109 to 2113, the second etching conditions are changed, and CF ₄ and Cl ₂ are used as etching gases, and the respective gas flow ratios are set to 30/30 (SCCM). The plasma is generated by applying 500 W RF (13.56 MHz) power to the coil-type electrode at a pressure of about 30 seconds, and etching is performed for about 30 seconds. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under this etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Up to this point, the first shape conductive layers 2114 to 2118 and the conductive film 2303 forming the convex portions are formed.

Next, a first doping process is performed without removing the resist masks 2109 to 2113 as they are. In the first doping treatment, an impurity element imparting n-type conductivity to the semiconductor layer (hereinafter referred to as an n-type impurity element) is ion-doped or ion-implanted in a self-aligning manner using the first shape conductive layer as a mask. By the method, it is added to the semiconductor layer. Note that as the n-type impurity element, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. In the impurity region, an impurity region 2120 having a first concentration is formed in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (FIGS. 3B and 27B).

Next, a second etching process is performed without removing the resist masks 2109 to 2113 as they are. CF ₄ , Cl ₂ and O ₂ are used for the etching gas, the gas flow ratio is 20/20/20 (SCCM), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa. The plasma is generated to perform etching. 20 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. Under this second etching condition, the W film is etched. In this manner, second shape conductive layers 2121 to 2125 and a conductive film 2304 for forming convex portions are formed (FIG. 3C).

Next, a second doping process is performed. Using the second shape first conductive film formed by the first doping treatment as a mask, the impurity concentration is 1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / inside the n-type impurity region (channel forming region side). Impurity regions 2126b to 2129b having a second concentration in a concentration range of cm ³ are formed.

Next, after removing the resist masks 2109 to 2113, a new resist mask 2130 is formed, and a third etching process is performed. Using Cl ₂ as an etching gas, each gas flow rate ratio is 80 (SCCM), and 350 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma. Etching is performed for about 40 seconds. 50 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a substantially negative self-bias is applied. In this way, the second shape gate electrode of the later driving circuit p-channel TFT and the later pixel TFT is etched, and the later third shape p-channel TFT and the later pixel TFT gate electrode 2131, 2132, a conductive film 2305 for forming a convex portion is formed (FIGS. 4B and 28B). Note that in this specification, a later pixel TFT refers to a pixel TFT in the middle of a manufacturing process. Any TFT is applicable.

A resist mask 2133 is newly formed to cover the subsequent pixel TFT and the uneven region. The n-channel TFT of the later driver circuit is covered with a mask 2130. Then, a third doping process is performed in which an impurity imparting p-type (hereinafter referred to as a p-type impurity element) is added to the p-channel TFT and the semiconductor layer of the storage capacitor. In this embodiment, a p-type impurity element is added in a self-aligning manner using the third shape conductive layer as a mask to form a fourth concentration impurity region. In this embodiment, the fourth concentration impurity regions 2134 to 2137 are formed by an ion doping method using diborane (B ₂ H ₆ ).

  An n-type impurity element (phosphorus (P) in this embodiment) is added to the fourth concentration impurity region at different concentrations, but the concentration of the p-type impurity element is n in any region. Since impurities are added during the doping process so as to be higher than the concentration of the p-type impurity element, no problem arises because the p-channel TFT functions as a source region and a drain region.

  Through the above steps, an impurity element for imparting each conductivity type is added to each semiconductor layer. Further, all impurity regions were formed in a self-aligned manner using the gate electrode as a mask.

  In addition, what is necessary is just to form the some convex part provided in the pixel part at the same process as the process of forming pixel TFT.

  Next, the resist masks 2130, 2133, and 2134 are removed, and a first interlayer insulating film 2138 that covers the entire surface is formed. In order to obtain an insulating film affected by the uneven region 1207 formed in the pixel portion, the first interlayer insulating film 2138 is an insulating film containing silicon and has a thickness of 200 to 400 nm using a plasma CVD method or a sputtering method. What is necessary is just to form. In this embodiment, a silicon oxynitride film having a thickness of 400 nm is formed by plasma CVD. The material of the insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used in a single layer or a stacked layer.

  Next, a heat treatment step for activating the impurity element added to each semiconductor layer is performed. This heat treatment step for activation is performed by heat treatment using a furnace (furnace annealing method). The heat treatment may be performed at a temperature of 300 to 500 ° C., typically 400 to 450 ° C. in a nitrogen atmosphere with an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. Activation was performed by heat treatment. In addition to the furnace annealing method, a laser annealing method, an RTA method, or a thermal annealing method can be applied.

  When a catalyst element is used for crystallization, it is necessary to reduce the concentration of Ni used as a catalyst in the channel formation region, so that a high concentration of phosphorus (P) is simultaneously formed with the heat treatment for activation. Gettering is performed on the n-type impurity region containing the impurity. The heat treatment temperature at this time may be 300 to 700 ° C., typically 500 to 550 ° C. It is possible to reduce the nickel concentration in the semiconductor layer mainly serving as a channel formation region. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.

  In this embodiment, the heat treatment for activation is performed after the first interlayer insulating film 2138 is formed. However, the first interlayer insulating film 2138 may be formed after the heat treatment, but it is used for the conductive film. In the case where the material is weak against heat, it is preferable to perform a heat treatment step after forming an interlayer insulating film for protecting the conductive film as in this embodiment.

  Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the semiconductor layer. In this example, heat treatment was performed at 410 ° C. for 1 hour in a nitrogen atmosphere containing about 3% hydrogen. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

  When the activation treatment is performed by laser annealing, it is desirable to irradiate a laser such as an excimer laser or a YAG laser after performing the hydrogenation.

  A silicon oxynitride film is formed to a thickness of 50 to 100 nm as the first interlayer insulating film 2138, and the activation process of the impurity element added to the semiconductor film is performed at 300 to 700 ° C. (typically 550 ° C.). After performing the heat treatment for about 4 hours, a silicon nitride film having a thickness of 100 to 300 nm may be formed, and the heat treatment may be performed at 300 to 550 ° C. for 1 to 12 hours in a nitrogen atmosphere containing hydrogen.

  Next, a second interlayer insulating film 2139 is formed on the first interlayer insulating film 2138. In this example, an acrylic resin film having a thickness of 0.8 to 1.2 μm was formed. The influence of the uneven region formed in the pixel portion appears on the surface, and the second interlayer insulating film 2139 having unevenness on the surface is formed. In order to clarify the influence of the convex portion, the interlayer insulating film may be formed without removing the resist mask used for forming the convex portion.

  Next, contact holes reaching the source line and the semiconductor layer (impurity region) of each TFT were formed in the first interlayer insulating film 2138 and the second interlayer insulating film 2139.

  Then, wirings 2140 to 2145 that electrically connect the TFTs are formed. These wirings 2141 to 2145 are formed by patterning a laminated film of a Ti film having a thickness of 50 to 250 nm and an alloy film (alloy film of Al and Ti) having a thickness of 300 to 500. In the pixel portion, a pixel electrode 2144 is formed. As the pixel electrode 2144, it is desirable to use a material having excellent reflectivity such as a film containing Al or Ag as a main component or a film in which these are stacked. Under the influence of a plurality of uneven regions 1207 formed in the pixel portion 1206, uneven pixel electrodes are formed.

  In this embodiment, since the end portion of the pixel electrode 2144 overlaps with the source line through the first interlayer insulating film 2138 and the second interlayer insulating film 2139, the pixel electrode is used without using a black matrix. The gap between them is shielded from light.

  As described above, the driver circuit 1205 including the n-channel TFT 1201 and the p-channel TFT 1202, the pixel TFT 1203, the storage capacitor 1204, and the pixel portion 1206 including the uneven region 1207 are formed over the same substrate. In the present specification, such a substrate is referred to as an active matrix substrate.

  FIG. 30 is a top view of an active matrix substrate manufactured according to this example. In this embodiment, the source line 2125 and the gate electrode are formed in the same layer (gate insulating film 2119) using the same conductive film. In addition, the pixel portion is shown with an uneven region 1207.

According to the steps shown in this embodiment, the number of photomasks necessary for manufacturing an active matrix substrate is six (a semiconductor layer pattern mask, a mask for forming a gate electrode, a mask for etching an unnecessary _LOV region) , A mask for forming a source region and a drain region of a P-channel TFT, a mask for forming a contact hole, a mask for forming a wiring and a pixel electrode). As a result, it is possible to manufacture a reflective active matrix substrate having a concavo-convex region composed of a plurality of convex portions in a pixel portion and having a concavo-convex pixel electrode without complicating the manufacturing process, thereby reducing the manufacturing cost and yield. It can contribute to improvement.

  A reflection type liquid crystal display device in which an electro-optical device manufactured using the present invention and a light source, a reflector, and a light guide plate are combined will be described.

  An LED or a cold cathode tube is used as the light source. The light source is disposed along the side surface of the light guide plate, and a reflector is provided behind the light source. In the present specification, the upper surface of the light guide plate refers to a plane on the side facing the user, and the lower surface of the light guide plate refers to a surface on the opposite side of the upper surface.

  As shown in FIG. 46, when the light emitted from the light source is efficiently incident from the side surface of the light guide plate by the reflector, it is reflected by the prism processing surface provided on the surface, and is incident on and transmitted to the semiconductor device. After being reflected by the reflective film provided on the lower surface of the apparatus, the light transmitted through the electro-optical device and the light guide plate reaches the user's eyes again.

  As a material for the light guide plate, inorganic glass such as quartz or borosilicate glass (refractive index of 1.42 to 1.7, transparency of 80 to 91%) or plastic material (resin material) can be used. Plastics include methacrylic resin, typically polymethyl methacrylate (refractive index 1.49, transmittance 92-93%), polycarbonate (refractive index 1.59, transmittance 88-90%), poly Arylate (refractive index 1.61, transmittance 85%), poly-4-methylbenten-1 (refractive index 1.46, transmittance 90%), AS resin [acrylonitrile styrene polymer] (refractive index 1.57, A material in which a resin such as MS resin [methyl methacrylate / styrene polymer] (refractive index 1.56, transmittance 90%) is mixed can be used.

  A semiconductor device manufactured using any one of Embodiments 1 to 11 can be applied to this embodiment.

  The top view shown in FIG. 47A is a connection for connecting a pixel portion, a drive circuit, an external input terminal 2210 to which an FPC (Flexible Printed Circuit Board: Flexible Printed Circuit) is pasted, and the external input terminal to the input portion of each circuit. An active matrix substrate provided with wirings 2211 and the like and a counter substrate 2151 provided with a color filter or the like are attached to each other with a sealant interposed therebetween.

  Further, an FPC including a base film 2213 and a wiring 2214 is bonded to the external input terminal with an anisotropic conductive resin 2215. Furthermore, the mechanical strength is increased by the reinforcing plate.

  FIG. 47B is a cross-sectional view of the external input terminal 2210 shown in FIG. Reference numeral 2217 denotes a wiring made of a conductive film formed to form the pixel electrode 2144. Since the outer diameter of the conductive particles 2216 is smaller than the pitch of the wiring 2217, if the amount dispersed in the adhesive 2215 is appropriate, it is electrically connected to the corresponding FPC-side wiring without short-circuiting with the adjacent wiring. Can be formed.

  The liquid crystal display panel manufactured as described above can be used as a display portion of various electric appliances.

  In this embodiment, as shown in FIG. 31, the semiconductor device disclosed in this embodiment includes a pixel TFT used for a pixel portion and a TFT used for a driver circuit, which are all one-conductivity type TFTs (here, p-channel TFTs or n-channel TFTs). One of channel type TFTs is indicated.)

  A general driving circuit is designed based on a CMOS circuit in which an n-channel TFT and a p-channel TFT are complementarily combined. In this embodiment, only a one-conductivity TFT (p-channel TFT) is used. Since the drive circuit is formed, the number of masks used when doping impurities for controlling the conductivity type can be reduced by one in the TFT manufacturing process. As a result, the manufacturing process can be shortened and the manufacturing cost can be reduced.

  In addition, in a PMOS circuit, there are an EEMOS circuit formed by an enhancement type TFT and an EDMOS circuit formed by combining an enhancement type and a depletion type.

  Here, FIG. 31A shows an example of an EEMOS circuit, and FIG. 31B shows an example of an EDMOS circuit. In FIG. 31A, reference numerals 1801 and 1802 denote enhancement type p-channel TFTs (hereinafter referred to as E-type PTFTs). In FIG. 31B, 1803 is an E-type PTFT, and 1804 is a depletion-type p-channel TFT (hereinafter referred to as a D-type PTFT).

In FIGS. _{31A and 31B} , V _DH is a power supply line to which a positive voltage is applied (positive power supply line), and V _DL is a power supply line to which a negative voltage is applied (negative power supply line). It is. The negative power source line may be a ground potential power source line (ground power source line).

  As described above, since all the TFTs are p-channel TFTs, the process of forming n-channel TFTs is reduced, so that the manufacturing process of the active matrix display device can be simplified. Accordingly, the yield of the manufacturing process is improved, and the manufacturing cost of the active matrix display device can be reduced.

  Further, although the characteristics required for the TFT differ from circuit to circuit, by using in combination with Examples 1 to 8, it is possible to manufacture TFTs having different structures from circuit to circuit without increasing the number of manufacturing steps.

  The semiconductor device manufactured by applying Examples 1 to 8 adopts a GOLD structure that is effective in preventing deterioration of the on-current value due to hot carriers in order to ensure reliability in the TFT of the drive circuit. ing.

  In the GOLD structure, the present inventors obtain three optimum values for the length in the channel length direction (hereinafter referred to as the length of the Lov region) of the region where the gate electrode and the low concentration impurity region overlap. An Lov length condition was set and a test for reliability was performed.

  In order to investigate the characteristic variation of the n-channel TFT due to the transient stress, the on characteristic variation after 20 hours (room temperature) was measured at Vd = + 20 V and Vg = 2-6. Here, the transient stress refers to this stress when the drain voltage is set to a certain value, the gate voltage is set to a certain value, and stress is applied. The present inventors evaluated the reliability of the TFT. This value is used for.

  FIG. 32 shows the results of measuring transient stress for samples having different Lov lengths. From the results of FIG. 32, it was confirmed that when the Lov length was 1 μm or more, the fluctuation of the maximum field-effect mobility after 20 hours was suppressed to 10% or less.

Subsequently, the time when the current deterioration rate was 10% was plotted against the reciprocal of the drain voltage. The 10-year guaranteed voltage is obtained by plotting the reciprocal of the stress voltage on a semi-logarithmic graph, where the lifetime until the maximum value of the mobility of the TFT (μ _{FE (max)} ) varies by 10% is regarded as the lifetime. This is a value obtained by estimating a stress voltage having a lifetime of 10 years from a linear relationship, and the present inventors use this value when evaluating the reliability of the TFT.

  FIG. 33 shows the result of obtaining the 10-year guaranteed voltage when the length of the Lov region is changed. From the results of FIG. 33, it can be seen that a highly reliable semiconductor device can be realized if the length of the Lov region is 1 μm or more, preferably 1.5 μm.

  A CMOS circuit and a pixel portion formed by implementing the present invention can be used for an active matrix liquid crystal display device. That is, the present invention can be implemented in all electric appliances in which these semiconductor devices (liquid crystal display devices) are incorporated in a display portion.

  Such electric appliances include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.), etc. Is mentioned. Examples of these are shown in FIGS. 34, 35 and 36. FIG.

  FIG. 34A shows a personal computer, which includes a main body 5001, an image input portion 5002, a display portion 5003, a keyboard 5004, and the like. The present invention can be applied to the image input unit 5002, the display unit 5003, and other signal control circuits.

  FIG. 34B shows a video camera, which includes a main body 5101, a display portion 5102, an audio input portion 5103, operation switches 5104, a battery 5105, an image receiving portion 5106, and the like. The present invention can be applied to the display portion 5102 and other signal control circuits.

FIG. 34C shows a mobile computer, which includes a main body 5201, a camera portion 5202, an image receiving portion 5203, an operation switch 5204, a display portion 5205, and the like. The present invention can be applied to the display portion 5205 and other signal control circuits.

  FIG. 34D illustrates a goggle type display including a main body 5301, a display portion 5302, an arm portion 5303, and the like. The present invention can be applied to the display portion 5302 and other signal control circuits.

  FIG. 34E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 5401, a display portion 5402, a speaker portion 5403, a recording medium 5404, an operation switch 5405, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 5402 and other signal control circuits.

  FIG. 34F illustrates a digital camera, which includes a main body 5501, a display portion 5502, an eyepiece portion 5503, operation switches 5504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 2502 and other signal control circuits.

  FIG. 35A illustrates a front type projector, which includes a projection device 5601, a screen 5602, and the like. The present invention can be applied to the liquid crystal display device 5808 constituting a part of the projection device 5601 and other signal control circuits.

  FIG. 35B shows a rear projector, which includes a main body 5701, a projection device 5702, a mirror 5703, a screen 5704, and the like. The present invention can be applied to the liquid crystal display device 5808 constituting a part of the projection device 5702 and other signal control circuits.

  Note that FIG. 35C illustrates an example of the structure of the projection devices 5601 and 5702 in FIGS. 35A and 35B. The projection devices 5601 and 5702 include a light source optical system 5801, mirrors 5802 and 5804 to 5806, a dichroic mirror 5803, a prism 5807, a liquid crystal display device 5808, a phase difference plate 5809, and a projection optical system 5810. Projection optical system 5810 includes an optical system including a projection lens. Although this embodiment showed the example of a three-plate type, it is not specifically limited, For example, a single plate type may be sufficient. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.

  FIG. 35D is a diagram illustrating an example of the structure of the light source optical system 5801 in FIG. In this embodiment, the light source optical system 5801 includes a reflector 5811, a light source 5812, lens arrays 5813 and 5814, a polarization conversion element 5815, and a condenser lens 5816. Note that the light source optical system illustrated in FIG. 35D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.

  However, the projector shown in FIG. 35 shows a case where a transmissive electro-optical device is used, and an application example in a reflective electro-optical device and an EL display device is not shown.

FIG. 36A shows a mobile phone, 3001 is a display panel, and 3002 is an operation panel. The display panel 3001 and the operation panel 3002 are connected at a connection portion 3003. An angle θ between the surface of the connection unit 3003 on which the display unit 3004 of the display panel 3001 is provided and the surface of the operation panel 3002 on which the operation keys 3006 are provided can be arbitrarily changed.
Further, it has an audio output unit 3005, operation keys 3006, a power switch 3007, and an audio input unit 3008. The present invention can be applied to the display portion 3004.

  FIG. 36B illustrates a portable book (electronic book), which includes a main body 3101, display portions 3102 and 3103, a storage medium 3104, operation switches 3105, an antenna 3106, and the like. The present invention can be applied to the display portions 3102 and 3103 and other signal circuits.

  FIG. 36C shows a display, which includes a main body 3201, a support base 3202, a display portion 3203, and the like. The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).

  As described above, the scope of application of the present invention is extremely wide and can be applied to electric appliances in various fields. Moreover, the electric appliance of this embodiment can also be realized using a semiconductor device manufactured by combining any of Examples 1 to 14.

The figure which shows embodiment of this invention. The figure which shows embodiment of this invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. FIG. 6 illustrates a structure of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. FIG. 6 is a diagram showing an upper surface of a semiconductor device of the present invention. FIG. 11 is a cross-sectional view of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. FIG. 11 is a cross-sectional view of a semiconductor device of the present invention. FIG. 6 is a circuit block diagram of an active matrix liquid crystal display device. FIG. 6 is a circuit block diagram of an active matrix liquid crystal display device. FIG. 6 illustrates an example of a method for crystallizing a semiconductor film. FIG. 6 illustrates an example of a method for crystallizing a semiconductor film. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 1 is a top view of a semiconductor device of the present invention. The figure which shows the structure of an EEMOS circuit and an EDMOS circuit. The figure which shows the measurement result of the reliability of TFT produced using this invention. The figure which shows the measurement result of the reliability of TFT produced using this invention. The figure which shows an example of an electric appliance. The figure which shows an example of an electric appliance. The figure which shows an example of an electric appliance. The figure which shows the Id-Vg curve of TFT produced using this invention. The figure which shows the Id-Vg curve of TFT produced using this invention. Sectional drawing of the inverter circuit produced using this invention. The figure which shows the Id-Vg curve of TFT produced using this invention. The figure which shows the Id-Vg curve of TFT produced using this invention. The figure which shows the measurement result of the reliability of TFT produced using this invention. The figure which shows the measurement result of the reliability of TFT produced using this invention. The figure which shows the measurement result of the reliability of TFT produced using this invention. The figure which shows the measurement result of the reliability of TFT produced using this invention. The figure which shows an example of implementation of this invention. The figure which shows an example of implementation of this invention.

Claims (7)

A method for manufacturing a semiconductor device in which a driver circuit portion including a first n-type thin film transistor and a p-type thin film transistor and a pixel portion including a second n-type thin film transistor are formed over the same substrate.
Forming first to third semiconductor layers on the substrate;
Forming a gate insulating film on the first to third semiconductor layers;
Forming a first conductive film on the gate insulating film;
Forming a second conductive film on the first conductive film;
Forming a first resist mask overlying the first to third semiconductor layers on the second conductive film;
Using the first resist mask as a mask, the first and third gate electrodes having a first shape having a tapered portion at an end portion by performing a first etching process on the first and second conductive films. Form the
Using the first resist mask and the first to third gate electrodes as a mask, an n-type impurity element is added to the first to third semiconductor layers, and the first to third gate electrodes are added. Forming a first concentration impurity region that does not overlap with
And a second etching process on the first of the first to the third gate electrode of the shape, to form a first through the third gate electrode of the second shape,
Using the first resist mask and the second conductive film of the first to third gate electrodes as a mask, an n-type impurity element is added to the first to third semiconductor layers, and the first Forming a second concentration impurity region overlapping the first to third gate electrodes between the impurity region having the first concentration and the channel formation region;
Forming a second resist mask overlying the first and third semiconductor layers on the first and third gate electrodes;
A p-type impurity element is added to the first and second concentration impurity regions of the second semiconductor layer using the second resist mask and the second conductive film of the second gate electrode as a mask. And
Removing the second resist mask overlapping the third semiconductor layer;
A third etching process is performed on the second and third gate electrodes having the second shape to form second and third gate electrodes having a third shape. Manufacturing method. A method for manufacturing a semiconductor device in which a driver circuit portion including a first n-type thin film transistor and a p-type thin film transistor and a pixel portion including a second n-type thin film transistor are formed over the same substrate.
Forming first to third semiconductor layers on the substrate;
Forming a gate insulating film on the first to third semiconductor layers;
Forming a first conductive film on the gate insulating film;
Forming a second conductive film on the first conductive film;
Forming a first resist mask overlying the first to third semiconductor layers on the second conductive film;
Using the first resist mask as a mask, the first and third gate electrodes having a first shape having a tapered portion at an end portion by performing a first etching process on the first and second conductive films. Form the
Using the first resist mask and the first to third gate electrodes as a mask, an n-type impurity element is added to the first to third semiconductor layers, and the first to third gate electrodes are added. Forming a first concentration impurity region that does not overlap with
And a second etching process on the first of the first to the third gate electrode of the shape, to form a first through the third gate electrode of the second shape,
Forming a second resist mask overlapping the first and third semiconductor layers;
Using the second resist mask and the second conductive film of the second gate electrode as a mask, the impurity region of the first concentration of the second semiconductor layer and the first of the second gate electrode A p-type impurity element is added to a region overlapping the conductive film of
Performing a third etching process on the second and third gate electrodes of the second shape to form second and third gate electrodes of a third shape;
The first to third semiconductors using the second conductive film of the first gate electrode of the second shape and the second and third gate electrodes of the third shape as a mask A method for manufacturing a semiconductor device, wherein an n-type impurity element is added to the layer. A method for manufacturing a semiconductor device in which a driver circuit portion including a first n-type thin film transistor and a p-type thin film transistor and a pixel portion including a second n-type thin film transistor are formed over the same substrate.
Forming first to third semiconductor layers on the substrate;
Forming a gate insulating film on the first to third semiconductor layers;
Forming a first conductive film on the gate insulating film;
Forming a second conductive film on the first conductive film;
Forming a first resist mask overlying the first to third semiconductor layers on the second conductive film;
Using the first resist mask as a mask, the first and third gate electrodes having a first shape having a tapered portion at an end portion by performing a first etching process on the first and second conductive films. Form the
Using the first resist mask and the first to third gate electrodes as a mask, an n-type impurity element is added to the first to third semiconductor layers, and the first to third gate electrodes are added. Forming a first concentration impurity region that does not overlap with
A second etching process is performed on the first to third gate electrodes of the first shape to form the first to third gate electrodes of a second shape;
Using the first resist mask and the second conductive film of the first to third gate electrodes as a mask, an n-type impurity element is added to the first to third semiconductor layers, and the first Forming a second concentration impurity region overlapping the first to third gate electrodes between the impurity region having the first concentration and the channel formation region;
Forming a second resist mask overlying the first semiconductor layer on the first gate electrode;
Using the second resist mask, the second conductive film of the second gate electrode, and the second conductive film of the third gate electrode as a mask, the first conductive of the second gate electrode A third etching process is performed on the film and the first conductive film of the third gate electrode to remove the second shape end, thereby removing the second shape and the second shape of the third shape. 3 gate electrodes,
Performing a fourth etching process on the gate insulating film to expose the surfaces of the source region and the drain region of the first to third semiconductor layers;
Forming a third resist mask overlying the first and third semiconductor layers on the first and third gate electrodes;
A p-type impurity element is added to the first and second concentration impurity regions of the second semiconductor layer using the third resist mask and the second gate electrode as a mask. Device fabrication method. A method for manufacturing a semiconductor device in which a driver circuit portion including a first n-type thin film transistor and a p-type thin film transistor and a pixel portion including a second n-type thin film transistor are formed over the same substrate.
Forming first to third semiconductor layers on the substrate;
Forming a gate insulating film on the first to third semiconductor layers;
Forming a first conductive film on the gate insulating film;
Forming a second conductive film on the first conductive film;
Forming a first resist mask overlying the first to third semiconductor layers on the second conductive film;
Using the first resist mask as a mask, the first and third gate electrodes having a first shape having a tapered portion at an end portion by performing a first etching process on the first and second conductive films. Form the
Using the first resist mask and the first to third gate electrodes as a mask, an n-type impurity element is added to the first to third semiconductor layers, and the first to third gate electrodes are added. Forming a first concentration impurity region that does not overlap with
A second etching process is performed on the first to third gate electrodes of the first shape to form the first to third gate electrodes of a second shape;
Using the first resist mask and the second conductive film of the first to third gate electrodes as a mask, an n-type impurity element is added to the first to third semiconductor layers, and the first Forming a second concentration impurity region overlapping the first to third gate electrodes between the impurity region having the first concentration and the channel formation region;
Forming a second resist mask overlying the first semiconductor layer on the first gate electrode;
Using the second resist mask, the second conductive film of the second gate electrode, and the second conductive film of the third gate electrode as a mask, the first conductive of the second gate electrode A third etching process is performed on the film and the first conductive film of the third gate electrode to remove the second shape end, thereby removing the second shape and the second shape of the third shape. 3 gate electrodes,
Forming a third resist mask overlying the first and third semiconductor layers on the first and third gate electrodes;
A p-type impurity element is added to the first and second concentration impurity regions of the second semiconductor layer using the third resist mask and the second gate electrode as a mask. Device fabrication method. A method for manufacturing a semiconductor device in which a driver circuit portion including a first n-type thin film transistor and a p-type thin film transistor and a pixel portion including a second n-type thin film transistor are formed over the same substrate.
Forming first to third semiconductor layers on the substrate;
Forming a gate insulating film on the first to third semiconductor layers;
Forming a first conductive film on the gate insulating film;
Forming a second conductive film on the first conductive film;
Forming a first resist mask overlying the first to third semiconductor layers on the second conductive film;
Using the first resist mask as a mask, the first and third gate electrodes having a first shape having a tapered portion at an end portion by performing a first etching process on the first and second conductive films. Form the
Using the first resist mask and the first to third gate electrodes as a mask, an n-type impurity element is added to the first to third semiconductor layers, and the first to third gate electrodes are added. Forming a first concentration impurity region that does not overlap with
A second etching process is performed on the first to third gate electrodes of the first shape to form the first to third gate electrodes of a second shape;
Using the first resist mask and the second conductive film of the first to third gate electrodes as a mask, an n-type impurity element is added to the first to third semiconductor layers, and the first Forming a second concentration impurity region partially overlapping the first to third gate electrodes between the impurity region having the first concentration and the channel formation region;
Forming a second resist mask overlying the first semiconductor layer on the first gate electrode;
Using the second resist mask, the second conductive film of the second gate electrode, and the second conductive film of the third gate electrode as a mask, the first conductive of the second gate electrode A third etching process is performed on the film and the first conductive film of the third gate electrode to remove the second shape end, thereby removing the second shape and the second shape of the third shape. 3 gate electrodes,
Forming a third resist mask overlying the first and third semiconductor layers on the first and third gate electrodes;
A p-type impurity element is added to the first and second concentration impurity regions of the second semiconductor layer using the third resist mask and the second gate electrode as a mask. Device fabrication method. In any one of Claims 1 thru | or 5 ,
A method for manufacturing a semiconductor device, wherein a p-type impurity element is added to the first to third semiconductor layers before forming the gate insulating film. In any one of Claims 1 thru | or 6 ,
The first conductive film and the second conductive film are formed using an element selected from tantalum, tungsten, titanium, molybdenum, aluminum, and copper, and an alloy material or a compound material containing the element as a main component. A method for manufacturing a semiconductor device.

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