JP4956771B2 - Semiconductor device - Google Patents

Description

The present invention relates to semiconductor equipment.

As a conventional technique, there is a field effect transistor using a heterointerface described in “Silicon carbide semiconductor device” of Patent Document 1 below.
In this conventional example, the barrier thickness at the heterointerface is controlled by a voltage applied to the gate electrode, and carriers are passed by a tunnel current when the element is on. This element does not have a channel region like a MOSFET and has a device structure that is not easily affected by high channel resistance.
A power semiconductor switch having a high breakdown voltage and a low on-resistance is provided.

JP 2003-318398 A

In the above-described prior art, in order to obtain reverse characteristics with higher breakdown voltage, it is conceivable that the impurity of the polycrystalline Si layer is of P ⁺ type. In order to keep the on-resistance in a low state, the polycrystalline Si layer near the interface of the gate insulating film is made N ⁺ type, and in order to connect with the source electrode with low resistance, the surface of the polycrystalline Si layer has N ^It was necessary to form a ⁺ type source lead region. When trying to form such a structure, it is necessary to form regions of different conductivity types in the polycrystalline Si layer. However, it is very difficult to have an impurity distribution in the depth direction in a film with a limited thickness. For this reason, it has been impossible to achieve both low on-resistance and high breakdown voltage in a field effect transistor utilizing a heterointerface. An object of the present invention is to provide a semiconductor equipment which enables both low on-resistance and breakdown voltage of the field-effect transistor using a hetero-interface.

In order to solve the above problems, the present invention comprises a first conductivity type semiconductor substrate is formed by contact with one major surface of the semiconductor substrate, a hetero semiconductor region of the first conductivity type band gap different from the semiconductor body and a second conductivity type of the hetero semiconductor region, a gate electrode formed through a gate insulating film adjacent portion to the joint portion between the first conductivity type hetero semiconductor region and the semi-conductor substrate, a first conductivity type a source electrode connected to the hetero semiconductor region of the hetero semiconductor region and the second conductivity type, the semiconductor device which have a a semi conductor substrate and ohmic-connected drain electrodes, on the hetero semiconductor region of the second conductivity type A part of the first conductivity type hetero semiconductor region overlaps, and the first conductivity type hetero semiconductor region is connected to the source electrode and the semiconductor substrate.

According to the present invention, it is possible to provide a semiconductor equipment which enables both low on-resistance and breakdown voltage of the field-effect transistor using a hetero-interface.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.
First embodiment
A first embodiment of the present invention will be described with reference to FIGS.
<Configuration of semiconductor device>
FIG. 1A is a diagram showing a device cross-sectional structure of the field effect transistor in the present embodiment.
This figure shows a cross section in which two unit cells are arranged facing each other. Actually, a plurality of these cells are connected in parallel to form an element, and these cross-sectional structures will be described as representative.

First, the structure of the semiconductor device will be described. High concentration N (i.e., ^{N +)} type SiC substrate (substrate region) 1 of one main surface on a low concentration N (i.e., N ^-) type SiC drain region 2 is formed. The drain region 2 is constituted by an epitaxial layer grown on the SiC substrate 1. There are several polytypes (crystal polymorphs) of SiC, but here, it will be described as representative 4H—SiC. In addition, other 6H-SiC and 3C-SiC may be used. In FIG. 1, the concept of the thickness of the substrate 1 and the drain region 2 is omitted. Actually, the substrate 1 has a thickness of several hundred μm, and the drain region 2 has a thickness of several μm to several ten μm.

A P ⁺ -type second hetero semiconductor region 3 of polycrystalline silicon is formed on one main surface side of the N ⁻ -type SiC drain region 2. SiC and polycrystalline silicon have different band gaps and different electron affinities. A heterojunction is formed at the interface. This is the reason why polycrystalline silicon is used as a hetero semiconductor region. Also, N ^- -type SiC drain region 2 and adjacent to the joint between the second hetero semiconductor region 3 of the P ⁺ -type, the first N ⁺ -type hetero semiconductor regions 4 are formed.

A gate electrode 7 is formed through the gate insulating film 6 in contact with the first hetero semiconductor region 4. The P ⁺ -type second hetero semiconductor region 3 is a P ⁺ -type contact region 1.
3 to the source electrode 8. The N ⁺ type first hetero semiconductor region 4 is also electrically connected to the source electrode 8 through the N ⁺ type source lead region 14 with a low resistance. A drain electrode 10 is ohmically connected to the back surface of the substrate 1 with a low resistance. The gate electrode 7 is insulated and separated from the source electrode 8 by the interlayer insulating film 9. Reference numeral 15 denotes a contact hole provided in the interlayer insulating film 9.

FIG. 1 (b), an enlarged view of the stacked hetero semiconductor region of polycrystalline Si was. A second polycrystalline Si layer 12 is formed on the first polycrystalline Si layer 11. Here, the first polycrystalline Si layer 11 is composed of a P ⁺ -type second hetero semiconductor region 3 and an N ⁺ -type first hetero semiconductor region 4. The second polycrystalline Si layer 12 includes a P + type contact region 13 and an N ⁺ type source lead region 14. The structural feature of the present embodiment is that it consists of a polycrystalline Si layer in which the hetero semiconductor regions are stacked.

The basic on / off operation is the same as that of the conventional example, but in this embodiment, the main heterojunction, in other words, most of the heterojunction is made of P ⁺ type polycrystalline Si. The barrier height is large. Therefore, a high breakdown voltage can be obtained in the reverse characteristics, and at the same time, the region where the current is driven by the electric field from the gate electrode 7 is a heterojunction of N ⁺ -type polycrystalline Si and N ⁻ -type SiC. It will be a thing.

<Method for Manufacturing Semiconductor Device>
Hereinafter, the manufacturing method of the field effect transistor according to the present embodiment will be described with reference to FIGS. Forming a type SiC drain region 2 ^- in FIG. 1 (a), a high concentration N ^{(N +)} type SiC low concentration N that is epitaxially grown on one main surface of the substrate 1 (N).

In FIG. 2B, after the surface of the drain region 2 is cleaned by pretreatment or the like, 1
A first polycrystalline silicon layer 11 is deposited. Here, the polycrystalline silicon layer 11 (FIG. 1).
In the hetero semiconductor region 3), impurities are introduced by means of ion implantation or the like so as to be P ⁺ type. As the impurity species, for example, boron (B) is suitable. Means such as vapor phase diffusion may be used.

In FIG. 2C, a second polycrystalline silicon layer 12 is further laminated thereon.
Here, impurities are also introduced into the second polycrystalline silicon layer 12 by means such as ion implantation so as to be P ⁺ type. In the figure, the polycrystalline silicon layer 12 is P ⁺ over the entire surface.
Although a mold is used, impurities may be introduced by selectively patterning a desired region.

In FIG. 3D, an N ⁺ -type impurity is selectively introduced from the surface of the second polycrystalline Si layer 12 into a desired position using photolithography or the like using ion implantation or the like. An N ⁺ -type impurity region 31 for forming one N ⁺ -type source lead region 14 is formed. As the impurity species, for example, arsenic (As) is suitable.

Here, it should be noted from the structure that diffusion of As, which is an introduced impurity, is suppressed.
That is, the P ⁺ -type region remains at the bottom of the polycrystalline Si layer 11 as the layer. With respect to the impurity distribution in the depth direction, the process flow is temporarily separated from FIGS.
It explains based on.

First, an example of the results of intensive experiments by the inventors will be described with reference to FIG. In FIG. 5, the horizontal axis represents the distance in the depth direction of the polycrystalline Si layer, and the vertical axis represents the amount of As impurities. For example, it is an analysis result by secondary ion mass spectrometry (SIMS) when two polycrystalline Si layers having a thickness of 1 μm are stacked.
In the figure, the case where B is introduced into each layer in advance to form P ⁺ type and then As is ion-implanted from the surface is described as “(1) Background is B ⁺ doped”. The case where As is ion-implanted from a state where nothing is doped is described as “(2) Background is non-doped”. In addition, in consideration of the total process of the field effect transistor, annealing was performed twice at 950 ° C. for 20 minutes in an N ₂ atmosphere, and then RTA (Rapid Thermal Anneal) was performed once at 1000 ° C. for 1 minute. Later.
As can be seen from the figure, As is accumulated at the interface by forming the polycrystalline Si into a laminated structure. (1) When the background is B ⁺ doped, the As distribution is shallow and the surface concentration is high. In the present invention, this phenomenon is applied to the structure of a field effect transistor using a heterojunction.

The concept will be described with reference to FIG. The horizontal axis represents the distance in the depth direction of the polycrystalline Si layer, and the vertical axis represents the amount of impurities of As. The line drawn with a broken line is polycrystalline S
The As distribution 61 is obtained when the i layer is not a laminated structure, and the line drawn with a solid line is the As distribution 62 when polycrystalline Si has a laminated structure.
The As distribution 61 in the case where the polycrystalline Si layer does not have a laminated structure has a surface concentration lower than the other, and is distributed to a deeper position in the polycrystalline Si layer. On the other hand, the As distribution 62 when the polycrystalline Si layer has a laminated structure has a high surface concentration and a shallow distribution. Further, As accumulates at the boundary between the first layer and the second layer. Assuming that the thickness of the stacked polycrystalline Si layer is a and the concentration of the P ⁺ -type impurity at that time is b, the heterointerface between the polycrystalline Si layer and the N ⁻ -type SiC drain region 2 is obtained by stacking. It can be seen that the P ⁺ type region can be left without becoming the N ⁺ type.

FIG. 7 illustrates a mechanism in which impurities such as As accumulate at the interface in the stacked polycrystalline Si layers. A second polycrystalline Si layer 12 is laminated on the first polycrystalline Si layer 11. Here, the grain boundary portion 7 of the first polycrystalline Si layer 11 is formed.
1, the formation position of the grain boundary portion 72 of the second polycrystalline Si layer 12 is shifted.
Thus, it is considered that As accumulates at the interface when the grain boundary portions 71 and 72 having a high impurity diffusion rate are shifted.
As described above, by laminating the polycrystalline Si layer, it is possible to suppress diffusion of As in the depth direction, and to form an N ⁺ type region on the outermost surface side and a P ⁺ type region on the lowermost part. is there.

Returning to the description of the process flow here.
In FIG. 3 (e), the stacked polycrystalline Si layer is etched at the location where the gate electrode 7 (see FIG. 1) is to be formed. The depression of the etched polycrystalline Si layer is referred to as an etching portion 32.

In FIG. 3F, the mask used for etching is used as it is, and impurities such as arsenic are selectively introduced into the side surface of the etching portion 32 by oblique rotation ion implantation or the like.
An N ⁺ type first hetero semiconductor region 4 is formed. Alternatively, it may be formed by introducing impurities by diffusion from the deposition film. Or use another photomask,
Impurities may be introduced from the surface. Thereafter, a gate insulating film 6 made of a silicon oxide film is deposited to a thickness of about several hundred to several thousand.

In FIG. 3G, a polycrystalline silicon layer 33 for forming the gate electrode 7 (FIG. 1) is laminated on the gate insulating film 6. The thickness of the etched portion 3 as a gate electrode
2 is adjusted to be sufficiently embedded.

  In FIG. 4H, the gate electrode 7 is patterned so as to have a desired shape.

In FIG. 4I, an interlayer insulating film 41 is formed so as to cover it.
In FIG. 4J, a contact hole 15 is opened in a part of the interlayer insulating film 41.
A source electrode 8 made of metal or the like is electrically connected to the hetero semiconductor region 3 with a low resistance.
Reference numeral 9 denotes an interlayer insulating film provided with a contact hole 15.
Further, a drain electrode 10 made of metal or the like is formed on the back surface side of the substrate 1 so as to provide a low resistance ohmic connection over the entire surface. As described above, the field effect transistor of this embodiment is completed.

<Operation>
Next, the operation of the field effect transistor manufactured by the manufacturing method of this embodiment will be described with an effect.
When the voltage applied to the gate electrode 7 with respect to the source electrode 8 is not more than a certain threshold voltage, the element is in an off state. When a high voltage equal to or lower than the element breakdown voltage is applied to the drain electrode 10, there is a barrier at the hetero interface between the second hetero semiconductor region 3 or the first hetero semiconductor region 4 and the drain region 2, and therefore the drain electrode 10 and the source A current does not flow between the electrodes 8, and the withstand voltage is maintained. Due to the voltage applied between the drain electrode 10 and the source electrode 8, the depletion layer extends to the N ⁻ -type drain region 2.

When the voltage applied to the gate electrode 7 with respect to the source electrode 8 exceeds a certain threshold voltage, the element is turned on. The thickness of the barrier is reduced at the point where the first hetero semiconductor region 4, the gate insulating film 6, and the N ⁻ -type SiC drain region 2 intersect due to the electric field from the gate electrode 7, and carriers can pass through the tunnel current. A current flows between the drain electrode 10 and the source electrode 8 through the first hetero semiconductor region 4 and the source lead region 14.

As described above, the semiconductor device of the present embodiment has a semiconductor substrate (N ⁺ -type SiC).
A hetero semiconductor region (first hetero semiconductor region 4 and second hetero semiconductor region 3) formed in contact with one main surface of substrate 1 and N ⁻ type SiC drain region 2 and having a band gap different from that of the semiconductor substrate. , Source lead region 14, contact region 1
3), a gate electrode 7 formed via a gate insulating film 6 at a portion adjacent to the junction between the hetero semiconductor region and the semiconductor substrate, and a source electrode 8 connected to the hetero semiconductor region, In the semiconductor device having the drain electrode 10 ohmically connected to the semiconductor substrate, the hetero semiconductor region has a plurality of stacked semiconductor layers (first polycrystalline Si layer 11, second polycrystalline Si layer 12).

By forming the hetero semiconductor region in a stacked structure in this way, impurity regions having different conductivity types can be formed in the depth direction in the hetero semiconductor region, thereby reducing the on-resistance of the field effect transistor using the hetero interface. There is an effect that it is possible to achieve both high breakdown voltage.

The hetero semiconductor region includes a first hetero semiconductor region 4 of a first conductivity type (here, N ⁺ type) and a second hetero semiconductor region 3 of a second conductivity type (here, P ⁺ type), and a gate electrode 7 is formed at a portion adjacent to the junction between the first hetero semiconductor region 4 and the semiconductor substrate of the first conductivity type via the gate insulating film 6, and the second hetero semiconductor region 3 is connected to the source electrode 8. The first hetero semiconductor region 4 is connected to the source electrode 8 through a first conductivity type lead region 14 formed on the second hetero semiconductor region 3.
Connected with. With such a configuration, it is possible to achieve both a low on-resistance and a high breakdown voltage of a field effect transistor using a hetero interface.

Further, the semiconductor substrate is made of any one of SiC, GaN, and diamond (in this case, SiC), and the hetero semiconductor region is made of at least one of single crystal, amorphous, and polycrystalline Si, GaAs, Ge, and SiGe ( Here, polycrystalline S
i). With such a configuration, it is possible to achieve both low on-resistance and high breakdown voltage of a high breakdown voltage field effect transistor using a common semiconductor material and utilizing a hetero interface.

The method of manufacturing a semiconductor device according to the present embodiment includes a step of introducing an impurity of a second conductivity type into at least the lowermost layer of the hetero semiconductor region, and a first conductivity type of at least the uppermost layer of the hetero semiconductor region. And introducing an impurity. With such a configuration, impurity regions having different conductivity types can be formed in the depth direction in the hetero semiconductor region, thereby making it possible to achieve both low on-resistance and high breakdown voltage of a field effect transistor using a hetero interface. Become.

In addition, polycrystalline Si is used to form the hetero semiconductor region on the semiconductor substrate.
Forming a layer (first polycrystalline Si layer 11, second polycrystalline Si layer 12) (FIG. 2C), and at least the lowest layer of the polycrystalline Si layer has a second conductivity type A step of introducing an impurity (FIG. 2C) and a step of introducing an impurity of the first conductivity type into at least the uppermost layer of the polycrystalline Si layer (FIG. 3D), The hetero semiconductor region 4 is formed by a step of introducing an impurity of the first conductivity type in a region adjacent to the gate insulating film 6 (FIG. 3F). With such a configuration, it is possible to form impurity regions of different conductivity types in the polycrystalline Si layer in the depth direction, thereby making it possible to achieve both low on-resistance and high breakdown voltage of field-effect transistors using heterointerfaces. become.

<< Second Embodiment >>
A second embodiment of the present invention will be described with reference to FIGS. 8 and 9.
<Configuration of semiconductor device>
FIG. 8 shows a device cross-sectional structure of the field effect transistor according to the present embodiment.
This figure also corresponds to a cross section in which two unit cells are arranged to face each other as in FIG. Actually, a plurality of these cells are connected in parallel to form an element, and these cross-sectional structures will be described as representative.

First, the structure of the semiconductor device will be described. High concentration N ^{(N +)} type SiC substrate 1 of one main surface on the low concentration N (N ^-) type SiC drain region 2 is formed. The drain region 2 is constituted by an epitaxial layer grown on the SiC substrate 1. There are several polytypes (crystal polymorphs) of SiC, but here, it will be described as representative 4H—SiC. Other 6H—SiC and 3C—SiC may be used. In FIG. 8, the concept of the thickness of the substrate 1 and the drain region 2 is omitted. Actually, the substrate has a thickness of several hundred μm, and the thickness of the drain region 2 is about several μm to several tens of μm.

The configuration in which each region of polycrystalline silicon is formed on one main surface side of the N ⁻ -type SiC drain region 2 is the same as that of the first embodiment. A P ⁺ -type second hetero semiconductor region 3 and an N ⁺ -type first hetero semiconductor region 4 are formed, and a gate electrode 7 is formed in contact with the first hetero semiconductor region 4 via a gate insulating film 6. Has been. The P ⁺ -type second hetero semiconductor region 3 is connected to the source electrode 8 through a P ⁺ -type contact region 13. The first hetero semiconductor region 4 is also electrically connected to the source electrode 8 through the N ⁺ -type source lead region 14 with a low resistance. A drain electrode 10 is ohmically connected to the back surface of the substrate 1 with a low resistance.
The gate electrode 7 is insulated and separated from the source electrode 8 by the interlayer insulating film 9.

FIG. 8B shows an enlarged view of a hetero semiconductor region composed of stacked polycrystalline Si layers. As a unique configuration of the present embodiment, the first layer of polycrystalline Si 21, 2
A layer of polycrystalline Si 22, a third layer of polycrystalline Si 23, and a fourth layer of polycrystalline Si 24 are sequentially stacked. The first polycrystalline Si 21 and the second polycrystalline Si 22 are P ⁺
It comprises a second hetero semiconductor region 3 of the type and a first hetero semiconductor region 4 of the N ⁺ type. The third polycrystalline Si layer 23 and the fourth polycrystalline Si layer 24 are composed of a P ⁺ -type contact region 13 and an N ⁺ -type source lead region 14. The structural feature of the present embodiment is that it consists of a polycrystalline Si layer in which hetero semiconductor regions are laminated in multiple layers.

  The basic on / off operation is the same as in the first embodiment.

<Method for Manufacturing Semiconductor Device>
Hereinafter, a characteristic part of the method for manufacturing a field effect transistor according to the present embodiment will be extracted and described with reference to FIGS.

Forming a type SiC drain region 2 ^- In FIG. 9 (a), a high concentration N ^{(N +)} type SiC low concentration N that is epitaxially grown on one main surface of the substrate 1 (N).

In FIG. 9B, after the surface of the drain region 2 is cleaned by pretreatment or the like, the polycrystalline silicon layer 21 is deposited. Here, impurities are introduced using means such as ion implantation so as to be P ⁺ -type. As the impurity species, for example, boron (B) is suitable. Means such as vapor phase diffusion may be used.

In FIG. 9C, a polycrystalline silicon layer 22 is further laminated thereon. Here, impurities are introduced into the second polycrystalline silicon layer 22 by means of ion implantation or the like so as to be P ⁺ type. In the figure, the entire surface is a P ⁺ type, but impurities may be introduced by selectively patterning a desired region.

Similarly, in FIG. 9D, the third polycrystalline Si layer 23 and the fourth polycrystalline Si layer are formed.
Layer 24 is laminated continuously. As for the introduction of impurities for forming the P ⁺ type, it is sufficient that at least the lowermost layer is the P ⁺ type and the contact region (13 in FIG. 8) is the P ⁺ type and the layers are connected with low resistance. It is easily conceivable that boron is ion-implanted each time the layers are stacked, but the number of ion implantations may be reduced to reduce the number of steps. After the uppermost polycrystalline Si layer 24 as the uppermost layer is laminated, an N ⁺ type impurity is selectively introduced into the desired position using photolithography or the like using ion implantation or the like, as shown in FIG. An N ⁺ type impurity region 91 for forming the N ⁺ type source lead region 14 is formed. As an impurity species, for example, arsenic (As)
Etc. are suitable.

Here, it should be noted in terms of structure that the diffusion of As, which is an introduced impurity, is further suppressed as compared with the first embodiment by the multi-layer stacking, so that the first polycrystalline Si layer 21 is formed.
This means that the P ⁺ type region remains at the bottom.

As described above, it is possible to further suppress the diffusion of As in the depth direction by laminating the polycrystalline Si layer, and to surely form the N ⁺ type region on the outermost surface side and the P ⁺ type region on the lowermost side. Is possible.
Since other process flows are the same as those described in the first embodiment, the description thereof is omitted.

In the present embodiment, the polycrystalline Si layer has a multi-layered structure, so that impurity regions having different conductivity types can be formed in the polycrystalline Si layer in the depth direction, thereby using a field effect type utilizing a heterointerface. There is an effect that both low on-resistance and high breakdown voltage of the transistor can be achieved.

Note that the N ⁺ -type impurity region is not formed in the second polycrystalline Si layer 22 in FIG. 8A, whereas the surface of the second polycrystalline Si layer 22 in FIG. N ^{+ in} region
Although the type impurity region 91 is formed, it suffices that the lowermost hetero interface is P ⁺ type, and either configuration may be adopted.

<< Third embodiment >>
A third embodiment of the present invention will be described with reference to FIG.
FIG. 10A is a diagram showing a device cross-sectional structure of a field effect transistor according to the present invention, which is basically the same as FIG. 1A described in the first embodiment.
The difference will be described with reference to FIG. 10B in which the hetero semiconductor region is enlarged.

Although the second polycrystalline Si layer 12 is formed on the first polycrystalline Si layer 11, what is characteristic of this embodiment is that the end of the first polycrystalline Si layer 11 is That is, the second polycrystalline Si layer 12 is formed so as to cover the portion. The first polycrystalline Si layer 11 is a P ⁺ -type second hetero semiconductor region 3. Second layer of polycrystalline S
The i layer 12 is an N ⁺ type first hetero semiconductor region 4 that is continuous with the P ⁺ type contact region 13 and the N ⁺ type source lead region 14. In this embodiment,
An interface exists between the P ⁺ -type second hetero semiconductor region 3 and the N ⁺ -type first hetero semiconductor region 4. Because of this interface, the lateral diffusion of impurities such as As from the first hetero semiconductor region 4 to the second hetero semiconductor region 3 is suppressed. Then, the first hetero semiconductor region 4 can be formed in a very narrow region about the thickness of the polycrystalline Si layer, and it is possible to form a field effect transistor that is advantageous in further increasing the breakdown voltage while realizing a low on-resistance. There is a unique effect.

The embodiment described above is described in order to facilitate understanding of the present invention, and is not described in order to limit the present invention. Therefore,
Each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

(A) is device structure sectional drawing in 1st embodiment of this invention, (b) is device structure sectional drawing which expanded the laminated polycrystal Si layer part in (a). It is a flowchart which shows the manufacturing process in 1st embodiment of this invention. It is a flowchart which shows the manufacturing process in 1st embodiment of this invention. It is a flowchart which shows the manufacturing process in 1st embodiment of this invention. It is a figure which shows the experimental result of the impurity distribution in the laminated polycrystalline Si layer. It is device structure sectional drawing explaining the impurity distribution model of As in this invention. It is a figure explaining the impurity distribution concept of As in this invention. (A) is device structure sectional drawing in 2nd embodiment of this invention, (b) is device structure sectional drawing which expanded the laminated polycrystal Si layer part in (a). It is a flowchart which shows a part of manufacturing process in 2nd embodiment of this invention. (A) is device structure sectional drawing in 3rd embodiment of this invention, (b) is device structure sectional drawing which expanded the laminated polycrystal Si layer part in (a).

Explanation of symbols

1 ^... N + SiC substrate 2 ^... N - SiC drain region 3 ... second hetero semiconductor regions 4 ... hetero semiconductor region 6 ... gate insulating film 7 ... gate electrode 8 ... source electrode 9 ... interlayer insulating film 10 ... drain electrode first to DESCRIPTION OF SYMBOLS 11 ... First polycrystalline Si layer 12 ... Second polycrystalline Si layer 13 ... Contact region 14 ... Source extraction region 15 ... Contact hole 21 ... First polycrystalline Si layer 22 ... Second multiple poly Crystal Si layer 23... Third polycrystalline Si layer 24... Fourth polycrystalline Si layer 31... N ⁺ -type impurity region 32. Etching portion 33 ... Polycrystalline Si layer 61. Distribution 62 ... Impurity distribution 71 in the case of a stacked structure 71 ... Grain boundary portion of first-layer polycrystalline Si 72 ... Grain boundary portion 91 of second-layer polycrystalline Si ... N ⁺ type impurity region

Claims (3)

A first conductivity type semiconductor substrate;
A first conductivity type hetero semiconductor region and a second conductivity type hetero semiconductor region formed in contact with one main surface of the semiconductor substrate and having a band gap different from that of the semiconductor substrate;
A gate electrode formed through a gate insulating film in a portion adjacent to the junction between the first conductive type hetero semiconductor region and the semiconductor substrate;
A source electrode connected to the first conductive type hetero semiconductor region and the second conductive type hetero semiconductor region;
A semiconductor device having a drain electrode ohmically connected to the semiconductor substrate,
A portion of the first conductivity type hetero semiconductor region is superimposed on the second conductivity type hetero semiconductor region,
The semiconductor device according to claim 1, wherein the first conductivity type hetero semiconductor region is connected to the source electrode and the semiconductor substrate . Before SL hetero semiconductor region of the first conductivity type to the hetero semiconductor region and the second conductivity type, the semiconductor device according to claim 1, wherein the each of a plurality of layers. The semiconductor substrate is made of SiC, GaN, or diamond;
Hetero semiconductor region and the hetero semiconductor region to the the second conductivity type of said first conductivity type, a single-crystal Si, amorphous Si, Tayui crystal S i, and characterized by comprising GaAs, Ge, at least one of SiGe The semiconductor device according to claim 1 or 2.

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