JP4962682B2 - Light emission drive circuit and display device - Google Patents

Description

  The present invention relates to a light emission drive circuit and a display device, and more particularly, to a light emission drive for performing light emission operation at a predetermined luminance gradation by supplying a light emission drive current corresponding to display data to a current control type light emitting element. The present invention relates to a display device including a circuit and a display panel configured by two-dimensionally arranging a plurality of display pixels each including a light emission driving circuit and the light emitting element.

  In recent years, a display device replacing a display device using a conventional cathode ray tube (CRT) as a monitor or display of a personal computer or video equipment has been widely used. In particular, liquid crystal display devices (LCD) are rapidly spreading because they can be made thinner and lighter, save space, reduce power consumption, and the like than conventional display devices. In addition, a relatively small liquid crystal display device is widely applied as a display device such as a mobile phone, a digital camera, and a personal digital assistant (PDA), which have been widely used in recent years.

  As a next-generation display device (display) following such a liquid crystal display device, an electric current (such as an organic electroluminescence element (hereinafter abbreviated as “organic EL element”) or a light emitting diode (LED) ( A full-fledged light-emitting element type display having a display panel in which display pixels each having a current-controlled light-emitting element that emits light at a predetermined luminance gradation in accordance with the current value of the light-emission driving current) are two-dimensionally arranged. It is expected to be put to practical use and spread.

  In particular, a light-emitting element type display using an active matrix driving method has a higher display response speed than a liquid crystal display device described above, and has no viewing angle dependency, and has high brightness, high contrast, and display image quality. In addition to high definition, it does not require a backlight like a liquid crystal display device, so it has the extremely advantageous feature that it can be made thinner and lighter and consume less power. .

  In such a light emitting element type display, various drive control mechanisms and drive control methods for controlling light emission of the above-described current control type light emitting element have been proposed. For example, Patent Document 1 and Patent Document 2 disclose, for each display pixel constituting a display panel, a drive circuit (hereinafter referred to as a plurality of switching means for controlling light emission of the light emitting element in addition to the light emitting element). And “light emission drive circuit”).

Here, a configuration example of the light emitting element type display and the display pixel (light emission drive circuit) in the prior art will be briefly described. Here, a circuit configuration in the case where an organic EL element is applied as the light emitting element is shown.
FIG. 11 is a schematic configuration diagram showing a main part of a light emitting element type display of an active matrix driving method in the prior art, and FIG. It is an equivalent circuit diagram showing a configuration example of the element.

  As shown in FIG. 11, the active matrix driving type light emitting element type display (organic EL display device) in the prior art is roughly arranged in a plurality of scanning lines (selection lines) SLp and data lines arranged in the row and column directions. (Signal line) In the vicinity of each intersection of DLp, a display panel 110P in which a plurality of display pixels EMp are arranged in a matrix, a scanning driver (scanning line driving circuit) 120P connected to each scanning line SLp, and each data line A data driver (data line driving circuit) 130P connected to the DLp, and a grayscale signal (a grayscale signal voltage Vpix or a grayscale signal current described later) corresponding to display data of a specific row in the data driver 130P. Ipix) is generated and supplied to the display pixel EMp in each column of the specific row via each data line DLp. It is.

  Here, in the display pixel EMp described in Patent Document 1 and the like, as shown in FIG. 12A, the gate terminal is connected to the scanning line SLp, and the drain terminal and the source terminal are connected to the data line DLp and the contact N111, respectively. A light emitting drive circuit DP1 including a thin film transistor (TFT) Tr111, a thin film transistor Tr112 having a gate terminal (G) connected to the contact N111 and a drain terminal (D) applied with a predetermined power supply voltage Vdd, and An organic EL element (current control type light emitting element) in which the anode terminal is connected to the source terminal (S) of the thin film transistor Tr112 of the light emission driving circuit DP1 and the ground potential Vgnd lower than the power supply voltage Vdd is applied to the cathode terminal. It is configured with an OEL.

  In FIG. 12A, CP1 is a parasitic capacitance (holding capacitance) formed between the gate and the source of the thin film transistor Tr112 or a capacitor connected between the gate and the source. The thin film transistors Tr111 and Tr112 are both n-channel field effect transistors.

  In the display device including the display panel 110P including the display pixel EMp having such a configuration, first, the scanning signal voltage Ssel of the on level (selection level; high level) is applied from the scanning driver 120P to the scanning line SLp of each row. Are sequentially applied, the thin film transistor Tr111 of the display pixel EMp (light emission drive circuit DP1) for each row is turned on, and the display pixel EMp is set to the selected state.

  In synchronization with this selection timing, the data driver 130P applies a gradation signal voltage Vpix having a voltage value corresponding to the display data to the data line DLp of each column, whereby each display pixel EMp (light emission drive circuit DP1). A potential corresponding to the gradation signal voltage Vpix is applied to the contact N111 (that is, the gate terminal of the thin film transistor Tr112) through the thin film transistor Tr111.

  As a result, the thin film transistor Tr112 is turned on in a conductive state corresponding to the potential of the contact N111 (that is, a conductive state corresponding to the gradation signal voltage Vpix), and grounded from the power supply voltage Vdd via the thin film transistor Tr112 and the organic EL element OEL. A predetermined light emission drive current flows through the potential Vgnd, and the organic EL element OEL emits light with a luminance gradation corresponding to display data (gradation signal voltage Vpix).

  Next, by applying a scanning signal voltage Ssel of an off level (non-selection level; low level) from the scanning driver 120P to the scanning line SLp, the thin film transistor Tr111 of the display pixel EMp for each row is turned off, and the display pixel EMp Is set to a non-selected state, and the data line DLp and the light emission drive circuit DP1 are electrically disconnected. At this time, a predetermined potential difference is generated between the gate and the source of the thin film transistor Tr112 based on the voltage applied to the gate terminal (contact N111) of the thin film transistor Tr112 and held in the parasitic capacitance CP1, and the thin film transistor Tr112 is turned on. continue.

  Therefore, similarly to the light emission operation in the selected state, a predetermined light emission drive current flows from the power supply voltage Vdd to the organic EL element OEL via the thin film transistor Tr112, and the light emission operation is continued. This light emission operation is controlled so as to continue, for example, for one frame period until the gradation signal voltage Vpix corresponding to the next display data is applied (written) to the display pixel EMp of each row.

  Such a drive control method adjusts the voltage value of the voltage (grayscale signal voltage Vpix) applied to each display pixel EMp (specifically, the gate terminal of the thin film transistor Tr112 of the light emission drive circuit DP1). This is called a voltage gradation designation method (or voltage designation method) because the light emission operation is performed at a predetermined luminance gradation by controlling the current value of the light emission drive current flowing through the EL element OEL.

  On the other hand, as shown in FIG. 12B, the display pixel described in Patent Document 2 and the like is near each intersection of a pair of scanning lines SLp1 and SLp2 and a data line DLp arranged in parallel to each other. The thin film transistor Tr121 has a gate terminal connected to the scan line SLp1, a drain terminal and a source terminal connected to the data line DLp and the contact N121, a gate terminal connected to the scan line SLp2, a source terminal and a drain terminal connected to the contact N121 and a contact N122, respectively. Are connected to the contact N122, the drain terminal is connected to the contact N121, the source terminal is applied with a predetermined power supply voltage Vdd, and the gate terminal is connected to the contact N122. , Thin film transistor with source voltage Vdd applied to source terminal An organic EL device in which an anode terminal is connected to the drain terminal of the thin film transistor Tr124 of the light emission drive circuit DP2 and a ground potential Vgnd lower than the power supply voltage Vdd is applied to the cathode terminal. The device has an element OEL.

  In FIG. 12B, CP2 is a parasitic capacitance (holding capacitance) formed between the gate and source of the thin film transistors Tr123 and Tr124, or a capacitor connected between the gate and source. The thin film transistor Tr121 is formed of an n-channel field effect transistor, and the thin film transistors Tr122 to Tr124 are formed of p-channel field effect transistors.

  In the display device including the display panel 110P including the display pixel EMp having such a configuration, first, the scanning driver 120P applies the high level scanning signal voltage Ssel1 to the scanning line SLp1 of each row and the low level to the scanning line SLp2. By applying each level scanning signal voltage Ssel2, the thin film transistors Tr121, Tr122, and Tr123 of the display pixel EMp (light emission drive circuit DP2) for each row are turned on, and the display pixel EMp is set to the selected state. In synchronization with this selection timing, the grayscale signal current Ipix having a (negative polarity) current value corresponding to the display data is supplied to the data line DLp of each column by the data driver 130P, whereby each display is started from the power supply voltage Vdd. The gradation signal current Ipix flows to the data driver 130P through the thin film transistors Tr123 and Tr121 of the pixel EMp (light emission drive circuit DP2).

  At this time, since the gate and drain of the thin film transistor Tr123 are electrically short-circuited by the thin film transistor Tr122, the thin film transistor Tr123 is turned on in the saturation region. As a result, the current level of the gradation signal current Ipix is converted to a voltage level by the thin film transistor Tr123, and a predetermined voltage is generated between the gate and the source (writing operation).

  The thin film transistor Tr124 is turned on according to the voltage generated between the gate and the source of the thin film transistor Tr123, and a predetermined light emission drive current flows from the power supply voltage Vdd to the ground potential Vgnd via the thin film transistor Tr124 and the organic EL element OEL. The element OEL emits light with a luminance gradation corresponding to display data (gradation signal current Ipix) (light emission operation).

  Next, when a high level scanning signal voltage Ssel2 is applied to the scanning line SLp2, the thin film transistor Tr122 is turned off, so that the voltage generated between the gate and the source of the thin film transistor Tr123 is held by the parasitic capacitance CP2, and then the scanning line When a low level scanning signal voltage Ssel1 is applied to SLp1, the thin film transistor Tr121 is turned off, thereby electrically disconnecting the data line DLp and the light emission drive circuit DP2.

  Thus, the thin film transistor Tr124 is continuously turned on by the potential difference based on the voltage held in the parasitic capacitance CP2, and a predetermined light emission drive current flows from the power supply voltage Vdd to the organic EL element OEL via the thin film transistor Tr124. The light emission operation is continued. This light emission operation is controlled so as to continue, for example, for one frame period until the gradation signal current Ipix corresponding to the next display data is written to each display pixel EMp.

  Such a drive control method is performed according to the current value of the current (grayscale signal current Ipix) supplied to each display pixel EMp (specifically, between the source and drain of the thin film transistor Tr123 of the light emission drive circuit DP2). By adjusting the voltage held in the capacitor (holding capacitor) CP2, the current value of the light emission drive current flowing through the organic EL element OEL is controlled to perform the light emission operation at a predetermined luminance gradation. This is called a key designation method (or current designation method).

  Note that each circuit configuration of the display pixel EMp shown in FIG. 12 is merely an example of a light emission drive circuit corresponding to a drive control method of a voltage gradation designation method and a current gradation designation method, and the light emission drive circuit. Various devices have been devised with respect to the number of switching elements (thin film transistors) constituting the above and the channel polarity thereof. A specific example of the circuit configuration other than the display pixel (light emission drive circuit) described above is also shown in the embodiments of the invention described later.

JP-A-8-330600 (Page 3, FIG. 4) JP 2001-147659 A (pages 7 to 8, FIG. 1)

  However, in the various light emission drive circuits (FIGS. 12A and 12B) applied to the display pixels as described above, the light emission drive transistors (thin film transistors Tr112 and Tr124) for supplying the light emission drive current are all used. ) Are connected in series to the organic EL element OEL, and the source terminal or drain terminal of the pixel selection transistor (thin film transistor Tr111, Tr122) is connected to the gate terminal (contact N111, N122) of the light emission driving transistor. It has a configuration.

  That is, since the light emission drive current in each display pixel is controlled based on the gate potential of the light emission drive transistor, in the light emission drive circuit having the above-described circuit configuration, the pixel selection transistor is substantially set. Depends on the drain potential. Here, as described above, the pixel selection transistors (thin film transistors Tr111 and Tr122) are transistors having a switching function that is turned on and off when each display pixel is selected, and as shown below, With the switching operation, the voltage (gate potential Vg) applied to the gate terminals of the light emission driving transistors (thin film transistors Tr112 and Tr124) varies.

FIG. 13 is an equivalent circuit showing a simulation model for verifying the variation in the gate potential of the light emission drive transistor in the display pixel (light emission drive circuit) shown in the prior art.
That is, when the circuit configuration of the display pixel (light emission drive circuit) shown in FIG. 12A is verified using a simplified simulation model (equivalent circuit) as shown in FIG. Transistor C111 is the gate-source capacitance of Tr111, Csum is the sum of the parasitic capacitance of the thin film transistor (light emission drive transistor) Tr112 and the junction capacitance in the organic EL element OEL, and the scanning signal voltage Ssel applied to the gate terminal of the thin film transistor Tr111. Assuming that the selection level (on level) is Ssel (H) and the non-selection level (off level) is Ssel (L), the variation (variation potential) ΔVg of the gate potential Vg of the thin film transistor Tr112 is expressed by the following equation. .
ΔVg = Cgs (Ssel (H) −Ssel (L)) / (Cgs + Csum) (11)

  As a result, the gate potential Vg of the thin film transistor Tr112 varies greatly depending on the voltage range (Ssel (H) −Ssel (L)) of the scanning signal voltage Ssel applied when the display pixel is selected and not selected and the capacitance Cgs. Accordingly, the fluctuation potential ΔVg is generated, so that the light emission drive current flowing through the organic EL element OEL changes, and the light emission operation can be performed with the luminance gradation corresponding to the display data (gradation signal). Therefore, there is a problem in that the display quality of image information (display gradation characteristics) is deteriorated.

  Therefore, in view of the above-described problems, the present invention suppresses fluctuations in the light emission drive current with respect to changes in the gate potential of the light emission drive transistor due to the selection and non-selection operations of the display pixels, and is suitable for display data. An object of the present invention is to provide a light emission driving circuit capable of causing a light emitting element to emit light with luminance gradation, and a display device capable of displaying image information with appropriate image quality while suppressing deterioration of display gradation characteristics. And

According to a first aspect of the present invention, there is provided a light emission drive circuit for supplying a light emission drive current having a predetermined current value to a current control type light emitting element to emit light at a predetermined luminance.
The light emission drive circuit includes at least a first switching element that is a field effect transistor that has a current path connected in series to the light emission element and that flows the light emission drive current having a predetermined current value.
The first switching element includes at least a semiconductor layer in which a channel region constituting the current path is formed, a source electrode and a drain electrode extending to face a surface of the channel region , the semiconductor layer, and the source And an insulating film layer provided between the drain electrode, and an extension dimension in the current path direction that overlaps the insulating film layer at a relatively low applied voltage of the source and drain electrodes. The applied voltage is formed to be longer than the extension dimension in the current path direction that overlaps the insulating film layer on the relatively higher side.

Here, the first switching element is formed of a field effect transistor, and at least a source electrode and a drain electrode extending in a direction of the current path in a direction opposite to the surface of the channel region constituting the current path are extended. The dimensions are different from each other.
Particularly, in the light emission drive circuit according to the present invention, the field effect transistor is formed such that the extension dimension of the source electrode is longer than the extension dimension of the drain electrode.

The light emission driving circuit further includes a second switching element connected to a control terminal of the first switching element,
A voltage component based on a luminance designation signal for designating a current value of the light emission drive current by the second switching element may be inserted into the first switching element at a predetermined timing.

The first of the drain electrode and the source electrode of the switching element, which may be the power supply voltage is applied towards the applied voltage is relatively high, or,
The light emission drive circuit, a second switching element connected to a control terminal of the first switching element, if further comprising, among the drain electrode and the source electrode of said first switching element, wherein A power supply voltage that changes in potential according to the conduction state of the second switching element may be applied to a relatively high applied voltage .
The light emitting element is preferably an organic electroluminescence element.

The invention described in claim 6
In a display device that displays on a display panel having a plurality of display pixels arranged in the vicinity of intersections of a plurality of scanning lines and a plurality of signal lines arranged so as to be orthogonal to each other,
Each of the display pixels includes a current-controlled light emitting element, and a light emission driving circuit that supplies a light emission driving current to the light emitting element,
The light emission drive circuit generates at least a light emission drive current having a predetermined current value based on a captured gradation signal, and supplies the light emission drive current to the light emitting element. Writing control means for controlling the timing of causing the light emission control means to take in a signal,
At least the light emission control means includes a field effect transistor,
The field effect transistor includes at least a semiconductor layer in which a channel region constituting a current path connected in series to the light emitting element is formed, and a source electrode and a drain electrode extending to face the surface of the channel region And an insulating film layer provided between the semiconductor layer and the source and drain electrodes, and overlaps the insulating film layer at a relatively lower applied voltage of the source and drain electrodes. The extension dimension in the current path direction is formed so as to be longer than the extension dimension in the current path direction that overlaps the insulating film layer on the side where the applied voltage is relatively high.

The field effect transistor is formed so that the extension dimension of the source electrode on the side directly connected to the light emitting element is longer than the extension dimension of the drain electrode.
Wherein one of the drain electrode and the source electrode of the field effect transistor may be a power supply voltage towards the applied voltage is relatively high is applied, or,
Among the drain electrode and the source electrode of the field effect transistor, towards the applied voltage is relatively high, in response to said conductive state of the write control means, even if the power supply voltage potential change is applied Good.

The display device is at least
A selection signal is applied to the scanning line, and the writing control means provided in the display pixel connected to the scanning line is in a selection state in which the gradation signal can be written to the display pixel. Scanning drive means for setting;
Signal driving means for generating the gradation signal corresponding to the display pixel set in the selected state and supplying the gradation signal to the display pixel;
May be provided.

The signal driving means may apply a signal voltage having a voltage value corresponding to display data to the signal line as the gradation signal, or
The signal driving unit may cause a signal current having a current value corresponding to display data to flow through the signal line as the gradation signal.

  The light emission drive circuit according to the present invention supplies a light emission drive current for causing a light emission operation at a desired luminance gradation to a current control type light emitting element such as an organic EL element or a light emitting diode. In the circuit, an element structure of a first switching element (for example, a field effect transistor) that constitutes a light emission control unit that supplies at least the light emission driving current to the light emitting element constitutes a current path of the first switching element. The channel region has a configuration (asymmetric structure) formed asymmetrically with respect to a center line perpendicular to the current path direction of the channel region.

  In particular, the extension dimension of the source electrode directly connected to the light emitting element on the channel region (channel portion) is longer than the extension dimension of the drain electrode connected to the power supply voltage. Compared with a symmetrical structure in which the extending dimensions of the source electrode and the drain electrode are the same, fluctuations in the light emission driving current with respect to changes in the gate potential (control terminal potential) can be suppressed, so that the gradation signal ( A light emission driving current having an appropriate current value corresponding to the luminance designation signal) is allowed to flow through the light emitting element so that the light emission operation can be performed with an appropriate luminance gradation.

In the display device according to the present invention, the extension dimension in the current path direction of the source electrode and the drain electrode extending opposite to the channel region surface constituting the current path of the field effect transistor of the light emission control unit is made different. As a result, it is possible to suppress fluctuations in the light emission drive current with respect to changes in the potential of the control terminal of the field effect transistor.
Accordingly, each display pixel constituting the display panel can be operated to emit light with an appropriate luminance gradation according to display data, so that a display device having favorable display gradation characteristics can be realized.

Hereinafter, embodiments of a light emitting drive circuit according to the present invention and a display device including a display panel in which display pixels including the light emission drive circuit are two-dimensionally arranged will be described in detail.
<Overall configuration of display device>
First, the overall configuration of a display device according to the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an example of the overall configuration of a display device according to the present invention.

  As shown in FIG. 1, the display device 100 according to the present invention is roughly in the vicinity of each intersection of a plurality of scanning lines SL and a plurality of data lines (signal lines) DL respectively arranged in a row direction and a column direction. , A display panel 110 in which a plurality of display pixels EM each including a current control type light emitting element are arranged, and each scanning line SL of the display panel 110 is connected to each scanning line SL. The scanning signal voltage is sequentially applied to each scanning line SL at a predetermined timing. By applying (selection signal) Vsel, the display pixel EM for each row is connected to a scanning driver (scanning driving means) 120 for setting (scanning) the selected state (scanning), and each data line DL of the display panel 110 to display data. A data driver (signal driving means) 130 that generates a gradation signal (luminance designation signal) Dpx based on the data and supplies it to each data line DL, and at least the scanning driver 12 And a system controller 140 that generates and outputs a scanning control signal and a data control signal for controlling the operation state of the data driver 130, and a display composed of a digital signal based on a video signal supplied from the outside of the display device 100. Data (display signal) is generated and supplied to the data driver 130, and a timing signal (system clock or the like) for displaying predetermined image information on the display panel 110 is extracted based on the display data, or And a display signal generation circuit 150 that generates and supplies the system controller 140 with the display signal generation circuit 150.

(Display panel)
The display pixels EM arranged in a matrix form (n rows × m columns; n and m are arbitrary positive integers) on the display panel 110 have scanning signal voltages Vsel applied from the scanning driver 120 to the scanning lines SL, and Based on the gradation signal Dpx (specifically, gradation signal voltage Vpix or gradation signal current Ipix) supplied from the signal driver 130 to the data line DL, the gradation signal Dpx is written to the display pixel EM. Light emission drive circuit for controlling the operation and light emission operation of the light emitting element at the luminance gradation based on the gradation signal Dpx, and light emission at the luminance gradation corresponding to the current value of the light emission drive current supplied from the light emission drive circuit And a current control type light emitting element such as an operating organic EL element OEL or a light emitting diode.

  Here, the light emission driving circuit is set to a selected state or a non-selected state based on the scanning signal voltage Vsel, and takes in the gradation signal Dpx corresponding to the display data in the selected state and holds it as a voltage level. A light emission driving current corresponding to the held voltage level is supplied to the light emitting element to continuously emit light at a predetermined luminance gradation. A specific example of a display pixel (light emission drive circuit) applicable to the present invention will be described later.

(Scanning driver 120)
The scanning driver 120 sequentially applies a scanning signal voltage Vsel of a selection level (for example, high level) to each scanning line SL based on a scanning control signal supplied from the system controller 140, thereby displaying the display pixel EM for each row. Is set to the selected state, and the gradation signal Dpx based on the display data supplied from the data driver 130 via each data line DL is controlled to be written in each display pixel EM (light emission drive circuit).

  Here, the scanning driver 120 includes, for example, a plurality of stages of shift blocks including a shift register and a buffer corresponding to each scanning line SL, and a scanning control signal (scanning start signal, Based on the scan clock signal, etc., the shift register sequentially shifts the scan start signal as a shift signal to the next stage and converts the shift signal in each stage to a predetermined voltage level (high level) through a buffer. A known configuration that sequentially outputs each scanning line SL as the scanning signal voltage Vsel can be applied.

(Data driver 130)
Based on the data control signals (output enable signal, data latch signal, sampling start signal, shift clock signal, etc.) supplied from the system controller 140, the data driver 130 determines the display data supplied from the display signal generation circuit 150 as predetermined. The analog signal voltage or analog signal current corresponding to the display data is generated and supplied to each data line DL as the gradation signal Dpx (gradation signal voltage Vdata or gradation signal current Ipix). Control to do.

(System controller 140)
The system controller 140 generates and outputs a scanning control signal and a data control signal to at least the scanning driver 120 and the data driver 130 based on a timing signal supplied from a display signal generation circuit 150 described later. Each driver is operated at a predetermined timing to generate a scanning signal voltage Vsel and a gradation signal Dpx, which are applied to each scanning line SL and data line DL to be applied to each display pixel (light emitting drive circuit and light emitting element) EM. Control is performed to cause the display panel 110 to display image information based on a predetermined video signal by continuously executing the light emission operation.

(Display signal generation circuit 150)
For example, the display signal generation circuit 150 extracts a luminance gradation signal component from a video signal supplied from the outside of the display device 100, and converts the luminance gradation signal component into a digital signal for each row of the display panel 110. Is supplied to the data driver 130 as display data. Here, when the video signal includes a timing signal component that defines the display timing of image information, such as a television broadcast signal (composite video signal), the display signal generation circuit 150 is configured as shown in FIG. In addition to the function of extracting the luminance gradation signal component, it may have a function of extracting a timing signal component and supplying it to the system controller 140. In this case, the system controller 140 generates a scanning control signal and a data control signal to be individually supplied to the scanning driver 120 and the data driver based on the timing signal supplied from the display signal generation circuit 150.

  When the video signal supplied from the outside of the display device 100 is formed by a digital signal and the timing signal is supplied separately from the video signal, the video signal (digital signal) is used as display data as it is. The display signal generation circuit 150 may be omitted by supplying the timing signal directly to the system controller 140 while supplying the data driver 130.

<Display pixel>
Next, display pixels (light emission drive circuits) arranged in a display panel applied to the display device according to the above-described embodiment will be described in detail with reference to the drawings.
Here, the display pixel applied to the display device according to the present invention may include a light emission driving circuit corresponding to the voltage gradation designation type driving control method as shown in the above-described related art. In addition, a light emission driving circuit corresponding to the current gradation designation method may be provided. In each embodiment of the display pixel (light emission drive circuit) shown below, the display pixel including the light emission drive circuit corresponding to each type of drive control method is merely a representative circuit configuration, The present invention is not limited to this. In short, a light emission driving transistor (current path of a thin film transistor) for allowing a light emission driving current to flow through the light emitting element (organic EL element OEL) is connected in series to the light emitting element, and further, the gate potential of the light emission driving transistor. However, as long as it has a circuit configuration that changes according to the on / off operation of the pixel selection transistor (thin film transistor), it may have another circuit configuration.

  FIG. 2 is a circuit configuration diagram showing a first embodiment of a display pixel provided with a light emission driving circuit according to the present invention, and FIG. 3 is a light emission driving transistor applied to the light emission driving circuit according to this embodiment. It is a cross-sectional block diagram which shows an example of this element structure. Here, a case where the present invention is applied to a light emission drive circuit (see FIG. 12A) corresponding to the voltage gradation designation type drive control method described in the prior art will be described. 3A is a plan view of the light emission driving transistor from above, and FIG. 3B is a cross-sectional view of the light emission driving transistor cut in the thickness direction, and FIG. () Is a schematic diagram showing a channel potential at the position of FIG. 3B of the semiconductor layer 13 of the light emission driving transistor.

  As shown in FIG. 2, the display pixel EMA according to the present embodiment has a gate terminal in the vicinity of each intersection of the scanning line SL and the data line DL arranged so as to be orthogonal to the display panel 110 described above. An n-channel thin film transistor (second switching element, write control means) Tr11 having a source terminal and a drain terminal connected to the data line DL and a contact N11, a scanning terminal SL, a gate terminal to the contact N11, and a drain terminal (Drain electrode) D emission drive circuit DCA including n-channel thin film transistor (first switching element, light emission control means) Tr12, each of which has a drain electrode D connected to a power supply line VL (a high potential power supply voltage Vdd). , And the anode terminal to the source terminal (source electrode) S of the thin film transistor Tr12 of the light emission drive circuit DCA Is connected, the cathode terminal is configured with an organic EL element (light emitting element) OEL connected to the ground potential Vgnd.

  Note that, similarly to the equation (11) shown in the above-described prior art, Cgs represents the gate-source capacitance of the thin film transistor Tr11 which is a pixel selection transistor, and Csum is the thin film transistor Tr12 which is a light emission driving transistor. The total sum of the parasitic capacitance and the junction capacitance in the organic EL element OEL is shown.

  In the light emission drive circuit DCA according to the present embodiment, each of the thin film transistor Tr11 and the thin film transistor Tr12 is configured by an n-channel field effect transistor. For example, amorphous silicon is used as a semiconductor layer in which a channel region is formed. The existing amorphous silicon TFT can be applied. In this case, compared to polysilicon TFTs and single crystal silicon TFTs, an amorphous silicon manufacturing technology that has already been established is applied, and a thin film transistor with stable operating characteristics (small variation in device characteristics) is achieved with a simple manufacturing process. Can be manufactured.

  In the light emission drive circuit according to the present embodiment, in particular, the channel portion (interface region between the block layer and the semiconductor layer described later; channel region) and the drain electrode of the thin film transistor Tr12 which is a light emission drive transistor in the circuit configuration described above. The planar overlap dimension and the planar overlap dimension of the channel part and the source electrode are configured to be different from each other.

  Specifically, as shown in FIGS. 3A and 3B, the thin film transistor Tr12 includes a gate electrode 11 formed on the substrate SUB, a gate insulating film 11 covering the gate electrode 11, and a gate insulating film 12. A semiconductor layer 13 made of amorphous silicon or the like formed on the island, and a block layer 14 made of an insulating film such as silicon nitride or silicon oxide provided on the semiconductor layer 13 so as to protect the channel of the semiconductor layer 13; Impurity layers 15 and 16 formed on the left and right sides of the block layer 14, respectively, and a source electrode 17 and a drain electrode 18 formed on the impurity layers 15 and 16, respectively.

  In the thin film transistor Tr12 having such a configuration, the extension dimension XLs of the source electrode 17 on the block layer 14 that protects the channel is relatively longer than the extension dimension XLd of the drain electrode 18 on the block layer 14. Thus, the channel portion (block layer 14) is configured to have an asymmetric element structure with respect to the center in the channel length direction (center line Lcnt perpendicular to the left-right direction in the figure).

<Element characteristics of light emission driving transistor>
Next, element characteristics of the thin film transistor having the element structure as described above will be described.
FIG. 4 is a schematic configuration diagram showing an element structure used for verifying element characteristics of a light emission driving transistor applied to the light emission driving circuit according to the present embodiment.

  First, an element structure used for verifying element characteristics in a thin film transistor applied as a light emission driving transistor will be described. 4 schematically shows a planar overlap of the channel portion (block layer 14) with the source electrode 17 and the drain electrode 18 in the element structure shown in FIG.

  Specifically, as shown in FIG. 4A, in the channel portion having a channel length of 7 μm and a channel width of 600 μm, the source electrode on the channel portion (block layer 14) in the channel length direction (left-right direction in the drawing) The extension dimension XLs of 17 is 2 μm, the extension dimension XLd of the drain electrode 18 on the channel part is 2 μm, and the center of the channel part (block layer 14) in the channel length direction (perpendicular to the horizontal direction in the figure) A configuration in which the source electrode 17 and the drain electrode 18 are symmetrically formed with the same extension dimension at the same position with respect to the center line Lcnt) is defined as a first element structure of the thin film transistor.

  Further, as shown in FIG. 4B, in the channel portion having the same dimensions as the configuration shown in FIG. 4A, the extension dimension XLs of the source electrode on the channel portion in the channel length direction is set to 3 μm. The extension dimension XLd of the drain electrode on the channel part is set to 1 μm, the source electrode 17 is set longer than the drain electrode 18, and the center of the channel part in the channel length direction (center line Lcnt in the drawing) A structure in which the source electrode 17 and the drain electrode 18 are formed to be asymmetric is a second element structure of the thin film transistor.

  Further, as shown in FIG. 4C, in the channel portion having the same dimensions as the configuration shown in FIG. 4A, the extension dimension XLs of the source electrode on the channel portion in the channel length direction is set to 1 μm. The extension dimension XLd of the drain electrode on the channel part is set to 3 μm, the source electrode 17 is set shorter than the drain electrode 18, and the center of the channel part in the channel length direction (refer to the center line Lcnt in the figure) A configuration in which the source electrode 17 and the drain electrode 18 are formed to be asymmetric is a third element structure of a thin film transistor.

  Here, the extension dimension Lms in the channel length direction of the source electrode 17 immediately above each semiconductor layer 13 in FIGS. 4A to 4C is constant, and FIGS. 4A to 4C. The extension dimension Lmd in the channel length direction of the drain electrode 18 immediately above each semiconductor layer 13 is constant. Further, the extension dimension Lus in the channel length direction of the portion of the source electrode 17 in FIGS. 4A to 4C that does not overlap with the semiconductor layer 13 is constant, and FIGS. The extension dimension Lud in the channel length direction of the portion not overlapping the semiconductor layer 13 in each drain electrode 18 of c) is constant.

At this time, as shown in FIG. 3C, the semiconductor layer 13 is gradually changed from the voltage Vs to the voltage Vd from the source electrode 17 to the drain electrode 18 by the voltage Vs of the source electrode 17 and the voltage Vd of the drain electrode 18. An increasing channel voltage is formed.
Here, the length in the channel length direction of the overlapping portion 17TS that overlaps the semiconductor layer 13 in the source electrode 17 is the sum of the extending dimension Lms and the extending dimension XLs, and the overlapping portion 18TD that overlaps the semiconductor layer 13 in the drain electrode 18. The length in the channel length direction is the sum of the extension dimension Lmd and the extension dimension XLd.

  Accordingly, an electric field is generated above the semiconductor layer 13 on the side of the source electrode 17 due to the potential of the overlapping portion 17TS of the semiconductor layer 13 in the source electrode 17, so that the drain-source current Ids is reduced because it is closer to the source potential Vs. Try to let them. In addition, since an electric field is generated above the semiconductor layer 13 on the drain electrode 18 side due to the potential of the overlapping portion 18TD of the drain electrode 18, the drain-source current Ids is increased because the electric field is closer to the drain potential Vd. .

  At this time, since the overlapping portion 17TS of the source electrode 17 is longer than the overlapping portion 18TD of the drain electrode 18 when viewed from the channel length direction, the channel potential is controlled by the voltage Vs of the source electrode 17 rather than the voltage Vd of the drain electrode 18. Thus, since the drain-source current Ids is small, even if the variation potential ΔVg of the gate potential Vg of the thin film transistor is generated, the variation current ΔIds of the drain-source current Ids is small and the influence is small.

(Fluctuation of gate voltage of light emission driving transistor)
FIG. 5 is a simulation result showing the relationship (voltage-current characteristics) between the drain-source voltage and the drain-source current under the first condition in the thin film transistor having various element structures shown in FIG. 6 is a simulation result showing the relationship (voltage-current characteristics) between the drain-source voltage and the drain-source current under the second condition in the thin film transistor having various element structures shown in FIG. is there.

  In each of the thin film transistors having the first to third element structures described above, the gate voltage Vg (contact point) of the light emission driving transistor (that corresponds to the thin film transistor Tr12 shown in FIG. 2) represented by the formula (11) in the prior art. The influence of the variation ΔVg of the potential of N11 is verified.

  In the light emission driving circuit DCA having the circuit configuration shown in FIG. 2, in the selected state where the scanning signal Vsel of the selection level is applied from the scanning driver 120 via the scanning line SL, from the data driver 130 via the data line DL. When the gradation signal voltage (luminance designation signal) Vpix corresponding to the display data is applied, the contact N11 (that is, the gate terminal of the thin film transistor Tr12) to which the source terminal of the thin film transistor Tr11, which is a pixel selection transistor, is connected. Is applied with a potential (≈Vpix) corresponding to the gradation signal voltage Vpix.

Here, it is assumed that the gradation signal voltage Vpix and the high-potential power supply voltage Vdd connected to the drain terminal of the thin film transistor Tr12 are constant, and in the selected state, the gate potential Vg (≈Vpix) of the thin film transistor Tr12 is If the voltage fluctuation ΔVg occurs in the gate potential Vg in the non-selected state when 9 V and the power supply voltage Vdd are set to 20 V, the above equation (11)
ΔVg = Cgs (Vsel (H) −Vsel (L)) / (Cgs + Csum)
Therefore, ΔVg = 0.5V. Here, the gate-source capacitance Cgs of the thin film transistor Tr11 is set to 0.1 pF, the sum Csum of the parasitic capacitance of the thin film transistor Tr12 and the junction capacitance of the organic EL element OEL is set to 5 pF, and the scanning signal voltage Vsel (H) at the time of selection is set. The scanning signal voltage Vsel (L) at the time of 15V and non-selection was set to -10V.

As a result, the gate potential Vg of the thin film transistor Tr12 in the non-selected state changes by the voltage fluctuation ΔVg = 0.5V with respect to 9V in the selected state, and becomes substantially 8.5V.
Regarding the relationship (voltage-current characteristics) between the drain-source voltage Vds and the drain-source current Ids of the thin film transistor Tr12 in this case (first verification condition), the above-described element structures (FIG. 4A to FIG. When the relationship with c)) is verified, as shown in FIG. 5A, the extension of the source electrode 17 and the drain electrode 18 on the channel portion shown in FIG. In the voltage-current characteristic curve at the time of selection (gate potential Vg = 9V) when the dimensions are the same and symmetrical, when the drain-source voltage Vds (that is, the voltage between the power supply voltage Vdd and the ground potential Vgnd) is 20V, The drain-source current Ids is approximately 6.5 μA, and the drain-source current Ids is approximately 4.6 μA in the non-selection (gate potential Vg = 8.5 V) voltage-current characteristic curve. Results were obtained. That is, it has been found that the current value of the drain-source current Ids changes by about 1.9 μA.

  In contrast, the asymmetric structure (see FIG. 3 and FIG. 4B) is set such that the extension dimension of the source electrode 17 on the channel portion is longer than the extension dimension of the drain electrode 18. In the second element structure, as shown in FIG. 5B, in the voltage-current characteristic curve at the time of selection (gate potential Vg = 9 V), the drain-source voltage Vds (power supply voltage Vdd and ground potential Vgnd). When the voltage between the drain and the source is 20 V, the drain-source current Ids is approximately 5.4 μA, and in the voltage-current characteristic curve when not selected (gate potential Vg = 8.5 V), the drain-source current Ids Gave a result of approximately 3.8 μA. That is, it was found that the current value of the drain-source current Ids is suppressed to a change (fluctuation) of about 1.6 μA.

  On the other hand, as shown in FIG. 4C, the asymmetric structure (third element structure) is set such that the extension dimension of the source electrode 17 on the channel portion is shorter than the extension dimension of the drain electrode 18. As shown in FIG. 5C, the drain-source voltage Vds (the voltage between the power supply voltage Vdd and the ground potential Vgnd) is 20 V in the voltage-current characteristic curve at the time of selection (gate potential Vg = 9 V). In this case, the drain-source current Ids is approximately 8.7 μA, and the drain-source current Ids is approximately 6.2 μA in the voltage-current characteristic curve when not selected (gate potential Vg = 8.5 V). The result was obtained. That is, it has been found that the current value of the drain-source current Ids changes substantially by 2.5 μA.

  Next, in the light emission drive circuit DCA shown in FIG. 2, it is assumed that the drain-source current Ids of the thin film transistor Tr12 is constant and the high-potential power supply voltage Vdd connected to the source terminal 17 is constant when selected. In this case, when the drain-source current Ids of the thin film transistor Tr12 is set to 6.1 μA and the power supply voltage Vdd is set to 20 V in the selected state, the gate potential Vg of the thin film transistor Tr12 is set to the drain-source current Ids and the power supply voltage Vdd. In the non-selected state, the drain-source current Ids changes according to the voltage fluctuation ΔVg of the gate potential Vg.

  Here, as in the case described above, the gate-source capacitance Cgs of the thin film transistor Tr11 is 0.1 pF, the sum Csum of the parasitic capacitance of the thin film transistor Tr12 and the junction capacitance of the organic EL element OEL is 5 pF, and the scanning signal voltage when selected Assuming that Vsel (H) is 15V and the scanning signal voltage Vsel (L) at the time of non-selection is −10V, the gate potential Vg of the thin film transistor Tr12 in the non-selected state is the voltage in the selected state from the above equation (11). The voltage fluctuation ΔVg = 0.5V.

  In this case (second verification condition), regarding the relationship (voltage-current characteristics) between the drain-source voltage Vds and the drain-source current Ids of the thin film transistor Tr12 (FIG. 4A to FIG. When the relationship with c)) is verified, as shown in FIG. 6A, the extension dimensions of the source electrode 17 and the drain electrode 18 on the channel portion shown in FIG. In the structure (first element structure), the drain-source voltage Vds (the voltage between the power supply voltage Vdd and the ground potential Vgnd) is 20 V in the voltage-current characteristic curve at the time of selection (gate potential Vg = 8.9 V). In this case, the drain-source current Ids is approximately 6.1 μA, and the drain-source current Ids is approximately 4.3 μA in the voltage-current characteristic curve when not selected (gate potential Vg = 8.4 V). Results were obtained. That is, it has been found that the current value of the drain-source current Ids changes by approximately 1.8 μA.

  In contrast, the asymmetric structure (see FIG. 3 and FIG. 4B) is set such that the extension dimension of the source electrode 17 on the channel portion is longer than the extension dimension of the drain electrode 18. In the second element structure, as shown in FIG. 6B, the drain-source voltage Vds (power supply voltage Vdd and ground) in the voltage-current characteristic curve at the time of selection (gate potential Vg = 9.2 V). When the voltage between the potential Vgnd is 20 V, the drain-source current Ids is approximately 6.0 μA, and in the voltage-current characteristic curve when not selected (gate potential Vg = 8.7 V), As a result, the current Ids was approximately 4.3 μA. That is, it has been found that the drain-source current Ids changes by approximately 1.7 μA, and the change (fluctuation) is suppressed as compared with the first element structure.

  On the other hand, as shown in FIG. 4C, the asymmetric structure (third element structure) is set such that the extension dimension of the source electrode 17 on the channel portion is shorter than the extension dimension of the drain electrode 18. As shown in FIG. 6C, in the voltage-current characteristic curve when selected (gate potential Vg = 8.5 V), the drain-source voltage Vds (the voltage between the power supply voltage Vdd and the ground potential Vgnd) is In the case of 20 V, the drain-source current Ids is approximately 6.1 μA, and in the voltage-current characteristic curve when not selected (gate potential Vg = 8.0 V), the drain-source current Ids is approximately 4. A result of 2 μA was obtained. That is, it has been found that the current value of the drain-source current Ids changes (fluctuates) by about 1.9 μA.

  Thus, the planar overlap (extension dimensions XLs and XLd in the channel length direction) of the source electrode 17 and the drain electrode 18 with respect to the channel portion (channel region formed at the interface between the semiconductor layer 13 and the block layer 14) is slightly increased. Is shifted (shifted) to the variation ΔVg of the gate potential Vg of the light emission driving transistor (thin film transistor Tr12) accompanying the on / off operation of the pixel selection transistor (thin film transistor Tr11) at the time of selection and non-selection. The fluctuation of the current value of the light emission drive current (drain-source current Ids) can be suppressed.

  In particular, the source electrode (power supply voltage connection side) extended dimension with respect to the channel portion is lengthened, and the drain electrode (light emitting element connection side) extension dimension is relatively shortened to verify the source electrode. Compared to a symmetrical structure in which the extension dimensions of the drain electrode and the drain electrode are the same, and an asymmetric structure in which the extension dimension of the source electrode is shortened relative to the channel part and the extension dimension of the drain electrode is relatively increased. Thus, fluctuations in the light emission drive current can be suppressed. Therefore, a light emission driving current having an appropriate current value corresponding to arbitrary display data can be supplied to the light emitting element (organic EL element OEL) to perform a light emitting operation with an appropriate luminance gradation. A display device having characteristics can be realized.

(Response of light emitting drive transistor, writing characteristics)
Next, the response and write characteristics of the thin film transistor having the above-described element structure are verified. Here, the description will be made while comparing the thin film transistors having the first to third element structures shown in FIG.

  As shown in FIGS. 5A to 5C, in the voltage-current characteristics of the thin film transistor serving as the light emission driving transistor, in the thin film transistor having the second element structure, the drain-source with respect to the drain-source voltage Vds. It turns out that the rising tendency of the inter-current Ids is relatively steep and the tendency is equal to or higher than that of other element structures (first and third element structures). (Characteristic curves within dotted ellipses in each figure). This means that the writing rate of the thin film transistor itself (that is, the arrival rate at which a predetermined voltage is reached within a certain time; response, writing characteristics) is good.

  As described above, by applying the thin film transistor having the second element structure to the light emission driving transistor, even when the selection time is set short, the drain-source voltage Vds corresponds to a predetermined potential corresponding to the gate potential Vg. Since it easily reaches the voltage value, a light emission driving current having an appropriate current value corresponding to the display data can be passed through the light emitting element (organic EL element OEL) to perform a light emitting operation with an appropriate luminance gradation.

  Therefore, the thin film transistor having an asymmetric structure in which the extension dimension of the source electrode (power supply voltage connection side) is set longer than the channel portion and the extension dimension of the drain electrode (light emitting element connection side) is set relatively short is emitted. By applying the transistor as a light emission driving transistor of the driving circuit, fluctuations in the current value of the drain-source current (light emission driving current) with respect to the voltage fluctuation ΔVg of the gate potential Vg of the transistor can be suppressed. Between the state where the pixel selection transistor is set to the selected state (the state where the pixel selection transistor is turned on) and the state where the pixel selection transistor is set to the non-selected state (the state where the pixel selection transistor is turned off). Even when the voltage applied to the gate terminal (gate potential) fluctuates, the light source supplied to the light emitting element (organic EL element) It is possible to suppress a change in the current value of the optical drive current and to perform a light emission operation with an appropriate luminance gradation according to display data, and to realize a favorable display gradation characteristic.

  In particular, in a thin film transistor in which the extension dimension of the source electrode is increased with respect to the channel portion and the extension dimension of the drain electrode is set relatively short, the writing rate (when a predetermined gate voltage is applied, a certain time The rate at which the drain-source voltage reaches a desired potential is improved, and the selected voltage can sufficiently reach the specified voltage corresponding to the display data (grayscale signal voltage). For example, the number of scanning lines Even when the display panel has a higher resolution or a larger screen, the display gradation characteristics can be improved.

<Another configuration example of light emission driving circuit>
Next, another circuit configuration of the light emission drive circuit to which the technical idea of the present invention can be applied will be specifically described.
FIG. 7 is a circuit configuration diagram showing another embodiment (second and third embodiments) of the light emission drive circuit according to the present invention. Here, about the structure equivalent to 1st Embodiment mentioned above, the same or equivalent code | symbol is attached | subjected and the description is simplified.

  In the above-described embodiment, the light emission drive circuit having a circuit configuration corresponding to the drive control method of the voltage gradation designation method has been described. However, the present invention is not limited to this, and for example, as shown in the related art The present invention may be applied to a light emission drive circuit (see FIG. 12B) corresponding to a drive control method of a current gradation designation method, or may be applied to a drive control method of a voltage gradation specification method or a current gradation specification method. A corresponding circuit configuration may be provided.

As a second embodiment of the light emission drive circuit corresponding to the drive control method of the voltage gradation designation method, for example, as shown in FIG. 7A, the display pixel EMB is orthogonal to the display panel 110 described above. A gate terminal is connected to the scanning line SL, and a source terminal and a drain terminal are connected to the data line DL and one electrode side of the capacitor C21 in the vicinity of each intersection of the scanning line SL and the data line DL. The thin film transistor (second switching element) Tr21 and the gate terminal are connected to the contact N21 connected to the other electrode side of the capacitor C21, and the source terminal and drain terminal are higher than the power supply line VL (ground potential Vgnd). Power supply voltage Vdd) and a thin film transistor (first switching element) Tr22 connected to the contact N22, and a gate It is applied the control signal AZ to the child, with each thin film transistors connected Tr23 to the drain and source terminals contact N21 and the contact point N22, ⁽ⁱⁿ the figure, numeral reference) inverted signal AZ * of the control signal AZ to the gate terminal is applied A light emission driving circuit DCB including a thin film transistor (first switching element) Tr24 whose source terminal is connected to the contact N22; and an anode terminal connected to a drain terminal of the thin film transistor Tr24 of the light emission driving circuit DCB, and a cathode It has an organic EL element OEL whose terminal is connected to the ground potential Vgnd.

In FIG. 7A, C22 is a parasitic capacitance (holding capacitance) formed between the gate and source of the thin film transistor Tr22 that is a light emission driving transistor, or a capacitor connected between the gate and source. . In the light emission driving circuit DCB according to the present embodiment, the thin film transistors Tr21 to Tr24 are all configured by p-channel field effect transistors. The thin film transistors Tr23 and Tr24 control the light emission operation by controlling the supply state of the light emission drive current to the organic EL element OEL based on the control signals AZ and AZ ^* , respectively, and the gate potential (contact N21) of the thin film transistor Tr22. Is controlled at a predetermined voltage.

  Also in the display pixel EMB (light emission drive circuit DCB) having such a circuit configuration, light emission drive transistors (thin film transistors Tr22 and Tr24) for causing a light emission drive current to flow through the light emitting elements (organic EL elements OEL) are included in the light emitting elements. In addition, a circuit configuration in which the gate potential of the light emission driving transistor (thin film transistor Tr22) (the potential of the contact N21) is changed in accordance with the on / off operation of the pixel selection transistor (thin film transistor Tr21) is connected in series. As in the first embodiment described above, at least one element structure of the thin film transistors Tr22 and Tr24 is provided, and the extension dimension of the source electrode (power supply voltage connection side) is drained with respect to the channel portion. The asymmetric structure is set longer than the extension dimension of the electrode (light emitting element connection side). Thus, light emission is performed with respect to the variation ΔVg of the gate potential Vg of the light emission driving transistor (thin film transistor Tr22) accompanying the on / off operation of the pixel selection transistor (thin film transistor Tr21) when the display pixel is selected and not selected. By suppressing fluctuations in the current value of the drive current, a light emission drive current having an appropriate current value according to display data is passed through the light emitting element (organic EL element OEL), and a light emission operation is performed with an appropriate luminance gradation. it can.

  Further, as a third embodiment, for example, as shown in FIG. 7B, the gradation signal current Ipix is connected to the light emission drive circuit corresponding to the drive control method of the current gradation designation method. An example applied to the data driver 130 that causes the gradation signal current Ipix to flow through the light emission driving circuit by drawing in will be described below. The mirror circuit EMC in the data driver 130 has a gate in the vicinity of each intersection of the mirror selection line MSL and the data line MDL that outputs the gradation signal voltage Vpix arranged so as to be orthogonal to the display panel 110 described above. A transistor (second switching element) Tr31 having a terminal connected to the mirror selection line MSL, a source terminal and a drain terminal connected to the contact N31 and the contact N32, a gate terminal to the mirror selection line MSL, and a source terminal and a drain terminal The transistor Tr32 connected to the contact N32 and the mirror data line MDL that outputs the gradation signal voltage Vpix, the gate terminal is connected to the contact N31, the source terminal is connected to the ground potential Vgnd, and the drain terminal is connected to the data line DL. The light emitting drive of the current gradation designation method shown in FIG. A transistor (first switching element) Tr33 connected to the circuit DCD and the like, a transistor Tr34 having a gate terminal connected to the contact N31, a drain terminal and a source terminal connected to the contact N32 and the ground potential Vgnd, The data driver 130 includes as many mirror circuits EMC as the number of connected data lines DL.

  In FIG. 7B, C31 is a parasitic capacitance (retention capacitance) formed between the gate and source of the transistors Tr33 and Tr34, and is also a capacitor connected between the gate and source. In the light emission drive circuit DCC according to the present embodiment, the transistors Tr31 to Tr34 are all configured by n-channel field effect transistors.

  Further, the transistors Tr31 and Tr32 output the gradation signal voltage Vpix supplied from the mirror data line MDL to the contact N31 and the contact N32 according to the selection signal output to the mirror selection line MSL. The transistor Tr33 and the transistor Tr34 constituting the mirror circuit flow the grayscale signal current Ipix from the data line DL in the direction of the arrow according to the grayscale signal voltage Vpix.

  Similarly to the first embodiment described above, in the mirror circuit EMC (light emission drive circuit DCC) having such a circuit configuration, the element structure of the transistor Tr33 for flowing the gradation signal current Ipix having a predetermined current value is also provided. When the mirror circuit is selected by adopting an asymmetric structure in which the extension dimension of the source electrode (ground potential connection side) is set longer than the extension dimension of the drain electrode (data line DL connection side) with respect to the channel portion. Further, the fluctuation of the current value of the gradation signal current Ipix is suppressed with respect to the fluctuation ΔVg of the gate potential Vg (grayscale signal voltage Vpix) of the transistor Tr33 due to the on / off operation of the transistor Tr31 when not selected. A light emission drive current having an appropriate current value according to the display data can be passed through the light emitting element (organic EL element OEL).

  In the first to third embodiments described above, a light emission driving circuit having a circuit configuration corresponding to the voltage gradation designation method and the current gradation designation method drive control method shown in the prior art (FIG. 12A). ), (B)), and the light emission driving circuit (FIG. 7 (a)) and mirror circuit (FIG. 7 (b)) having the applied (improved) circuit configuration, the technical idea of the present invention is applied. I explained the case.

  Here, in the light emission driving circuit corresponding to the voltage gradation designation method, the element characteristics (channel resistance and the like) of the pixel selection transistor and the thin film transistor serving as the light emission driving transistor are affected by the external environment (ambient temperature and the like) and the usage time. When there is variation or fluctuation (deterioration) depending on the light emission, the light emission drive current supplied to the light emitting element (organic EL element OEL) fluctuates, and the desired light emission characteristics can be stably obtained over a long period of time. It may be difficult to realize (display with a predetermined luminance gradation).

  In addition, when each display pixel is miniaturized in order to increase the definition of the display panel, variation in element characteristics (source-drain current, etc.) of each thin film transistor included in the light emission driving circuit is increased. In some cases, the tone control cannot be performed, and the light emission characteristics of each display pixel vary, resulting in deterioration of display image quality.

On the other hand, in the data driver 130 corresponding to the current gradation designation method described above, the current / voltage conversion transistor Tr33 and the transistor that convert the current level of the gradation signal current Ipix supplied from each display pixel into a voltage level. By providing these transistors 34 and connecting these transistors in a current mirror circuit, the current value of the light emission drive current supplied to the organic EL element OEL can be set. Therefore, each thin film transistor in the voltage gradation designating system as described above This has the advantage that the influence of variations and fluctuations in the element characteristics can be suppressed.
The current control type display device 100 that is operated using the data driver 130 that allows the above-described gradation signal current Ipix to flow will be specifically described below.

<Another configuration example of the light emission driving circuit>
Next, still another circuit configuration of the light emission drive circuit to which the technical idea of the present invention can be applied will be specifically described.
FIG. 8 is a circuit configuration diagram showing still another embodiment (fourth embodiment) of the light emission drive circuit according to the present invention. Here, about the structure equivalent to each embodiment mentioned above, the same or equivalent code | symbol is attached | subjected and the description is simplified. FIG. 9 is a timing chart showing the basic operation of the display pixel to which the light emission drive circuit according to this embodiment is applied. FIG. 10 is a conceptual diagram showing an operation state of the light emission drive circuit according to the present embodiment. FIG. 9 shows a drive control operation in the display pixels in the j-th column and the i-th row and the (i + 1) -th row of the display panel. Here, i and j are arbitrary positive integers for specifying the display pixels of the display panel (1 ≦ i ≦ n, 1 ≦ j ≦ m).

  As shown in FIG. 8, the display pixel EMD according to the present embodiment includes, for example, a gate near each intersection of the scanning line SL and the data line DL disposed so as to be orthogonal to the display panel 110 described above. A thin film transistor (second switching element) Tr41 having a terminal connected to the scan line SL, a source terminal and a drain terminal connected to the contact N41 and the power supply line VL (power supply voltage Vsc), and a gate terminal connected to the scan line SL And a thin film transistor Tr42 whose drain terminal is connected to the data line DL and the contact N42, a thin film transistor whose gate terminal is connected to the contact N41, and whose source terminal and drain terminal are connected to the contact N42 and the power supply line VL (power supply voltage Vsc). First switching element) Tr43 is connected between contact N41 and contact N42. A light emission driving circuit DCD having a connected capacitor C41, and an organic EL element OEL having an anode terminal connected to a contact N42 of the light emission driving circuit DCD and a cathode terminal connected to a ground potential. Has been.

Note that the capacitor C41 may be a parasitic capacitance formed between the gate and the source of the thin film transistor Tr43. A capacitor 40 is formed between the gate and source of the thin film transistor (second switching element) Tr41. Here, the fluctuation potential ΔVg of the gate potential Vg of the light emission driving transistor Tr43 is expressed by the following equation (12).
ΔVg = C40 (Vsel (H) −Vsel (L)) / (C40 + C41) (12)

  In addition, the thin film transistors Tr41 to Tr43 applied to the light emission drive circuit DCD according to the present embodiment are not particularly limited. However, by configuring all of the thin film transistors Tr41 to Tr43 with n channel thin film transistors, an n channel type can be obtained. Thus, a field effect transistor including a semiconductor layer made of amorphous silicon can be favorably applied. In this case, a simple amorphous silicon manufacturing technique can be applied to manufacture a light emission drive circuit with stable operating characteristics relatively easily.

  In the light emission driving circuit DCD having the circuit configuration as described above, at least the thin film transistor Tr43 has an element structure peculiar to the present invention, and the extension dimension of the source electrode (power supply line connection side) with respect to the channel portion is set. It is configured to have an asymmetric structure set longer than the extension dimension of the drain electrode (light emitting element connection side).

  The drive control method (light emission drive control) of the light emitting element (organic EL element OEL) in the light emission drive circuit DCD having such a configuration is, for example, as shown in FIG. 9, with one scan period Tsc as one cycle. In the scanning period Tsc, a writing operation period (selection period) Tse for selecting the display pixel EMD connected to the scanning line SL and writing the gradation signal current Ipix corresponding to the display data and holding it as a voltage component; A light emission operation for generating a light emission drive current according to the display data based on the voltage component written and held in the write operation period Tse and supplying the light emission drive current to the organic EL element OEL to emit light at a predetermined luminance gradation. It is executed by setting so as to include a period (non-selection period) Tnse (Tsc ≧ Tse + Tnse). Here, the writing operation period Tse set for each scanning line SL of each row is set so that there is no time overlap.

(Write operation period)
That is, in the writing operation period Tse of the display pixel EM, as shown in FIG. 9, first, the high-level scanning signal Vsel is applied from the scanning driver 120 to the specific scanning line SL to display the row. The pixel EMD is set to the selected state, and the low-level power supply voltage Vsc is applied to the power supply line VL of the display pixel EMD in the row. In synchronization with this timing, a negative gradation signal current (−Ipix) having a current value based on display data corresponding to each display pixel in the row is supplied from the data driver 130 to each data line DL. (That is, it is pulled out toward the data driver 130 via the data line DL).

  Thereby, the thin film transistors Tr41 and Tr42 constituting the light emission drive circuit DCD are turned on, and the low-level power supply voltage Vsc is applied to the contact N41 (that is, the gate terminal of the thin film transistor Tr43 and one end side of the capacitor C41). The data driver 130 performs an operation of drawing a negative gradation signal current (−Ipix) through the data line DL, so that the voltage level lower than the low-level power supply voltage Vsc becomes the contact N42 (that is, the thin film transistor). Applied to the source terminal of the Tr 43 and the other end of the capacitor C 41.

  As described above, a potential difference is generated between the contacts N41 and N42 (between the gate and the source of the thin film transistor Tr43), so that the thin film transistor Tr43 is turned on, and as shown in FIG. 10A, the thin film transistor Tr43, A write current (designated current) Ia corresponding to the current value of the gradation signal current Ipix flows through the data driver 130 via the contact N42, the thin film transistor Tr42, and the data line DL.

  At this time, the capacitor C41 accumulates charges corresponding to the potential difference generated between the contacts N41 and N42 (between the gate and source of the thin film transistor Tr43) and holds (charges) as a voltage component. Further, the power supply line VL is applied with a power supply voltage Vsc having a voltage level equal to or lower than the ground potential, and further, the write current Ia is controlled to flow in the direction of the data line DL, so that the anode of the organic EL element OEL Since the potential applied to the terminal (contact N12) is lower than the potential of the cathode terminal (ground potential) and a reverse bias voltage is applied to the organic EL element OEL, a light emission driving current is applied to the organic EL element OEL. Does not flow and the light emission operation is not performed.

(Light emission operation period)
Next, in the light emission operation period Tnse after the end of the write operation period Tse, as shown in FIG. 9, the low level scan signal Vsel is applied to the scan line SL in which the write operation is performed from the scan driver 120. As a result, the display pixel EM is set to a non-selected state, and a high-level power supply voltage Vsc is applied to the power supply line VL of the display pixel EMD in the row. In synchronization with this timing, the operation of drawing the gradation current Ipix by the data driver 130 (the supply operation of the negative polarity gradation signal current Ipix) is stopped.

  Thereby, the thin film transistors Tr41 and Tr42 constituting the light emission drive circuit DCD are turned off, and the application of the power supply voltage Vsc to the contact N41 (that is, the gate terminal of the thin film transistor Tr43 and one end side of the capacitor C41) is cut off. Since the application of the voltage level due to the drawing operation of the gradation signal current Ipix by the data driver 130 to the contact N42 (that is, the source terminal of the thin film transistor Tr43 and the other end of the capacitor C41) is cut off, the capacitor C41 The charge accumulated during the writing operation period is held.

  In this way, the capacitor C41 holds the charging voltage during the writing operation, whereby the potential difference between the contacts N41 and N42 (between the gate and the source of the thin film transistor Tr43) is held, and the thin film transistor Tr43 is turned on. To maintain. Further, since the power supply voltage Vsc having a voltage level higher than the ground potential is applied to the power supply line VL, the potential applied to the anode terminal (contact N42) of the organic EL element OEL is the potential of the cathode terminal (ground potential). ).

  Accordingly, as shown in FIG. 10B, a predetermined light emission drive current (output current) Ib flows in the forward bias direction from the power supply line VL to the organic EL element OEL via the thin film transistor Tr43 and the contact N42, and the organic EL element. OEL emits light. Here, the potential difference (charging voltage) based on the electric charge accumulated by the capacitor C41 corresponds to the potential difference when the write current Ia corresponding to the gradation signal current Ipix is caused to flow in the thin film transistor Tr43, and is supplied to the organic EL element OEL. The light emission drive current Ib has a current value equivalent to the write current Ia (Ib≈Ia).

  Thereby, in the non-selection period Tnse after the writing operation period Tse, the voltage component corresponding to the display data (gradation signal current Ipix) written in the writing operation period Tse is passed through the thin film transistor Tr43. The light emission drive current Ib is continuously supplied, and the organic EL element OEL continues the operation of emitting light at the luminance gradation corresponding to the display data.

Then, by sequentially repeating the above-described series of operations for all the scanning lines SL constituting the display panel 110, display data for one screen of the display panel is written, light is emitted at a predetermined luminance gradation, Desired image information is displayed.
Here, in the light emission drive circuit DCD according to the present embodiment, as described above (see FIG. 9), the power supply voltage Vsc whose potential changes according to the selection or non-selection state of the display pixel EMD is applied to the power supply line VL. Although necessary, the power supply voltage Vsc is applied to the power supply line VL at a timing synchronized with the scan signal Vsel output from the scan driver 120. Therefore, the scan driver 120 uses the scan signal Vsel ( Alternatively, a configuration in which a shift output signal for generating a scanning signal) is inverted, amplified to a predetermined signal level, and applied to each power supply line VL as a power supply voltage Vsc is applied. For example, in addition to the configuration of the display device 100 shown in FIG. 1, a plurality of power supply lines VL arranged in parallel with the scanning lines SL of the display panel 110. A power supply driver connected to the power supply driver and having a predetermined voltage value from the power supply driver at a timing synchronized with the scanning signal Vsel output from the scanning driver 120 based on the power supply control signal supplied from the system controller 140 described above; A configuration in which the power supply voltage Vsc is applied to the power supply line VL of the row (the display pixel EMB set to the selected state) to which the scanning signal Vsel is applied by the scanning driver 120 may be applied. .

(Saturation characteristics of light emission drive transistor)
Next, the saturation characteristic of the light emission drive transistor (thin film transistor Tr43) in the light emission drive circuit according to the fourth embodiment described above will be verified. Here, the saturation characteristics of the thin film transistors having the first to third element structures shown in FIGS. 3 and 4 will be described with reference to the simulation results shown in FIGS.

  In the light emission drive circuit according to the present embodiment, as shown in FIG. 9, the voltage level of the power supply voltage Vsc serving as a current supply source for the light emitting elements is selected (write operation period Tse) and non-selected ( The light emission operation period Tnse) is set and controlled. Here, since the power supply voltage Vsc in this embodiment corresponds to the power supply voltage Vdd shown in the first to third embodiments described above, the thin film transistor having each element structure shown in FIGS. From the voltage-current characteristic curve (simulation result) in FIG. 5, the characteristic that the change in the drain-source current Ids is less with respect to the change in the power supply voltage Vsc, that is, the change in the drain-source voltage Vds of the thin film transistor, It can be concluded that the device structure has good operating characteristics.

  From such a viewpoint, the voltage-current characteristic curves shown in FIGS. 5A to 5C are compared and verified. As a device structure of the thin film transistor, the extension dimension of the source electrode with respect to the channel portion is determined as the drain electrode. When the asymmetric structure (second element structure) set to be longer is applied (FIG. 5B), the extension structure of the source electrode and the drain electrode with respect to the channel portion is set to be the same (first structure). 5A), or an asymmetric structure (third element structure; FIG. 5C) in which the extension dimension of the source electrode is set shorter than that of the drain electrode with respect to the channel portion. Since the drain-source current Ids tends to saturate from a relatively low voltage region, the emission drive current (drain-source current Ids) due to the change in the power supply voltage Vsc (drain-source voltage Vds). Dynamic is suppressed, the light emission drive current having an appropriate current value corresponding to display data is found to be capable of flowing through the light emitting element (organic EL element OEL).

  Here, as shown in FIG. 3C, the length in the channel length direction of the overlapping portion 17 TS of the light emission driving transistor Tr 43 overlapping the semiconductor layer 13 in the source electrode 17 is overlapped with the semiconductor layer 13 in the drain electrode 18. Since the length of the portion 18TD is longer than the length in the channel length direction, the influence on the electric field generated in the semiconductor layer 13 is that the source potential Vs acting to reduce the drain-source current Ids has a larger drain-source current Ids. Since the drain-source current Ids is smaller than the drain potential Vd acting to increase, and as a result, the drain-source current Ids is reduced even if the fluctuation potential ΔVg of the gate potential Vg of the thin film transistor occurs. The fluctuation current ΔIds is small and the influence is small.

  Therefore, in the light emission drive circuit including the three thin film transistors shown in this embodiment, the element structure of the light emission drive transistor is an asymmetric structure in which the extension dimension of the source electrode is set longer than the drain electrode with respect to the channel portion. By applying this, as in the first to third embodiments described above, light emission occurs with respect to the variation ΔVg of the gate potential Vg of the light emission driving transistor (thin film transistor Tr43) when the display pixel is selected and not selected. By suppressing fluctuations in the current value of the drive current, a light emission drive current having an appropriate current value according to display data is passed through the light emitting element (organic EL element OEL), and a light emission operation is performed with an appropriate luminance gradation. Therefore, a display device having good display gradation characteristics can be realized.

  In addition, since the writing rate of the thin film transistor serving as the light emission driving transistor is improved, the voltage corresponding to the display data can be reached in a relatively short time in the selected state, and the display panel has a high resolution or a large screen. Even in such a case, good display gradation characteristics can be realized.

  Further, since the voltage-current characteristic shows a saturation tendency from a relatively low voltage region, the power supply voltage Vsc at the time of selection and non-selection changes by the drive control method specific to the light emission drive circuit according to the present embodiment. However, the fluctuation of the light emission drive current is suppressed, and the light emission drive current having an appropriate current value corresponding to the display data is supplied to the light emitting element (organic EL element OEL), so that the light emission operation can be performed with an appropriate luminance gradation. it can.

  In addition, according to the light emission drive circuit composed of the three thin film transistors shown in the present embodiment, as described above, the functions of both current / voltage conversion and light emission drive can be realized by a single thin film transistor. Therefore, the number of thin film transistors constituting each display pixel (light emission drive circuit) can be reduced to improve the light emission luminance and the manufacturing yield, and the variation in element characteristics occurring between the thin film transistors can be suppressed to achieve an appropriate level. Display gradation can be realized. Further, a gradation signal current (write current) having an equivalent current value is displayed on a display pixel (light emission drive) with respect to a light emission drive current (output current) for emitting light at a luminance gradation corresponding to display data. Circuit), the current value of the gradation signal current can be suppressed even in the higher luminance gradation compared to the light emission driving circuit to which the current mirror circuit configuration is applied, and the consumption of the display device is reduced. Electric power can also be suppressed.

It is a block diagram which shows an example of the whole structure of the display apparatus which concerns on this invention. 1 is a circuit configuration diagram showing a first embodiment of a display pixel including a light emission driving circuit according to the present invention. It is a cross-sectional block diagram which shows an example of the element structure of the light emission drive transistor applied to the light emission drive circuit which concerns on this embodiment. It is a schematic block diagram which shows the element structure used for verification of the element characteristic of the light emission drive transistor applied to the light emission drive circuit which concerns on this embodiment. It is a simulation result which shows the relationship between the drain-source voltage and drain-source current in 1st verification conditions in the thin-film transistor which has various element structures. It is a simulation result which shows the relationship between the drain-source voltage and drain-source current in 2nd verification conditions in the thin-film transistor which has various element structures. It is a circuit block diagram which shows other embodiment (2nd and 3rd embodiment) of the light emission drive circuit based on this invention. It is a circuit block diagram which shows other embodiment (4th Embodiment) of the light emission drive circuit which concerns on this invention. 3 is a timing chart showing the basic operation of a display pixel to which the light emission drive circuit according to the present embodiment is applied. It is a conceptual diagram which shows the operation state of the light emission drive circuit which concerns on this embodiment. It is a schematic block diagram which shows the principal part of the light emitting element type display of an active matrix drive system in a prior art. It is an equivalent circuit diagram which shows the structural example of the display pixel (light emission drive circuit and light emitting element) applicable to the light emitting element type display in a prior art. It is an equivalent circuit which shows the simulation model for verifying the fluctuation | variation of the gate potential of the light emission drive transistor in the display pixel (light emission drive circuit) shown to the prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Gate electrode 13 Semiconductor layer 14 Block layer 17 Source electrode 18 Drain electrode EMA-EMD Display pixel DCA-DCD Light emission drive circuit Tr11-Tr43 Thin-film transistor C11-C41 Capacitor OEL Organic EL element SL Scan line DL Data line

Claims (11)

In a light emission drive circuit for supplying a light emission drive current having a predetermined current value to a current control type light emitting element and performing a light emission operation at a predetermined luminance,
The light emission drive circuit includes at least a first switching element that is a field effect transistor that has a current path connected in series to the light emission element and that flows the light emission drive current having a predetermined current value.
The first switching element includes at least a semiconductor layer in which a channel region constituting the current path is formed, a source electrode and a drain electrode extending to face a surface of the channel region , the semiconductor layer, and the source And an insulating film layer provided between the drain electrode, and an extension dimension in the current path direction that overlaps the insulating film layer at a relatively low applied voltage of the source and drain electrodes. The light emission driving circuit is formed so as to be longer than an extension dimension in the current path direction overlapping with the insulating film layer at a relatively higher applied voltage. The light emission drive circuit further includes a second switching element connected to a control terminal of the first switching element,
The voltage component based on a luminance designation signal for designating a current value of the light emission drive current by the second switching element is taken into the first switching element at a predetermined timing. Light emission drive circuit.   3. The light emission drive circuit according to claim 2, wherein a power supply voltage is applied to the drain electrode and the source electrode of the first switching element which has a relatively higher applied voltage. 4. The light emission drive circuit further includes a second switching element connected to a control terminal of the first switching element,
Of the drain electrode and the source electrode of the first switching element, a power supply voltage that changes in potential according to the conduction state of the second switching element is applied to the relatively higher applied voltage. The light emission drive circuit according to claim 1, wherein:   The light-emitting drive circuit according to claim 1, wherein the light-emitting element is an organic electroluminescence element. In a display device that displays on a display panel having a plurality of display pixels arranged in the vicinity of intersections of a plurality of scanning lines and a plurality of signal lines arranged so as to be orthogonal to each other,
Each of the display pixels includes a current-controlled light emitting element, and a light emission driving circuit that supplies a light emission driving current to the light emitting element,
The light emission drive circuit generates at least a light emission drive current having a predetermined current value based on a captured gradation signal, and supplies the light emission drive current to the light emitting element. Writing control means for controlling the timing of causing the light emission control means to take in a signal,
At least the light emission control means includes a field effect transistor,
The field effect transistor includes at least a semiconductor layer in which a channel region constituting a current path connected in series to the light emitting element is formed, and a source electrode and a drain electrode extending to face the surface of the channel region And an insulating film layer provided between the semiconductor layer and the source and drain electrodes, and overlaps the insulating film layer at a relatively lower applied voltage of the source and drain electrodes. display device extending dimension of current path direction, the applied voltage is characterized in that it is formed to be longer than the extending dimension of the current path direction overlapping with the insulating film layer definitive towards relatively high.   The display device according to claim 6, wherein a power supply voltage is applied to a relatively higher one of the drain electrode and the source electrode of the field effect transistor.   A power supply voltage that changes in potential according to the conduction state of the write control means is applied to the relatively higher applied voltage of the drain electrode and the source electrode of the field effect transistor. The display device according to claim 6. The display device is at least
A selection signal is applied to the scanning line, and the writing control means provided in the display pixel connected to the scanning line is in a selection state in which the gradation signal can be written to the display pixel. Scanning drive means for setting;
Signal driving means for generating the gradation signal corresponding to the display pixel set in the selected state and supplying the gradation signal to the display pixel;
The display device according to claim 6, further comprising:   The display device according to claim 9, wherein the signal driving unit applies a signal voltage having a voltage value corresponding to display data to the signal line as the gradation signal. The display device according to claim 9, wherein the signal driving unit causes a signal current having a current value corresponding to display data to flow through the signal line as the gradation signal.

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