JP4963196B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a failure location analysis circuit for analyzing failure information of a semiconductor memory device.

  In a large scale integrated circuit (LSI) having a semiconductor storage device such as a RAM (Random Access Memory), for example, as disclosed in Patent Document 1, a configuration having means for specifying a failure location of a RAM is provided. As is known, in Patent Document 1, for example, as shown in FIG. 1, one failure location specifying means (failure location analysis circuit) is provided for one RAM.

  More specifically, in Patent Document 1, a scan register (FIGS. 5 to 8) having a data comparison function is provided so as to correspond to the data output of the RAM on a one-to-one basis, and data is output serially therefrom. A scan path having a comparison function configured as described above is disclosed.

  After executing the RAM test by using the scan path comparison function, serially scan out the pass or fail information for each data output, so that the failure position information, that is, the fail bit in the data output, Information about whether information is included can be acquired.

  The acquired failure position information is analyzed and encoded by the failure position specifying means.

JP 2002-1224098 A (FIGS. 5 to 8)

  As shown in Patent Document 1, the conventional LSI has a configuration in which one failure location analysis circuit is provided for one RAM, and thus there is a problem that the LSI is increased in size.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor integrated circuit device that prevents an increase in size due to the provision of a failure location analysis circuit.

  According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a plurality of storage units each having a semiconductor storage device having a redundancy function; and a test for diagnosis of whether the operations of the plurality of storage units are good or bad. A self-diagnosis circuit that outputs a signal and a one-to-one correspondence with the plurality of storage units, and each self-diagnosis circuit outputs an output value of each of the plurality of storage units based on the test signal A plurality of comparison circuits that compare expected values with memory cell block units, determine whether the operation is good or bad by matching and mismatching with the expected values, and output as bit data, and the plurality of comparison circuits A plurality of parallel / serial conversion circuits provided in a one-to-one relationship, each of which receives the comparison results from the plurality of comparison circuits in parallel, converts the results into serial output data, and outputs the serial output data; An OR circuit that receives the serial output data output from each of the parallel / serial conversion circuits, performs an OR operation, and a failure location analysis circuit that identifies the location of the failed memory cell block based on the operation output of the OR circuit; It has.

  According to the semiconductor integrated circuit device of the first aspect of the present invention, the serial output data output from each of the plurality of parallel / serial conversion circuits is received by the OR circuit, the OR operation is performed, and based on the operation output, Since the location of the failed memory cell block is specified by the failure location analysis circuit, the semiconductor integrated circuit device can be downsized as compared with the configuration in which one failure location analysis circuit is provided for one storage unit. Further, since serial output data respectively output from a plurality of parallel / serial conversion circuits is received by the OR circuit and OR operation is performed, when it is assumed that there is only one storage unit in which a failure exists, the OR circuit Functions as an automatic selector that automatically selects only the information of the storage unit where the fault exists and inputs it to the fault location analysis circuit, eliminating the need for a configuration for selecting serial output data and simplifying the device configuration be able to.

<A. Embodiment 1>
A semiconductor integrated circuit device according to a first embodiment of the present invention will be described with reference to FIGS.

<A-1. Device configuration>
FIG. 1 is a block diagram showing the overall configuration of the LSI 100 according to the first embodiment.
As shown in FIG. 1, in the LSI 100, n storage units RM1 to RMn composed of a RAM having a redundancy function and self-diagnosis (self-test) on the quality of storage and read operations in these storage units are performed. And a self-diagnosis circuit BIST for control.

  The storage units RM1 to RMn are configured to exchange data with the logic circuit UL, and address signals UA1 to UAn, data input signals UDI1 to UDIn, and write enable signals UWE1 to UWn output from the logic circuit UL. Are provided to the storage units RM1 to RMn via selector circuits SL1 to SLn, respectively.

  The selector circuits SL1 to SLn are circuits that switch signals supplied to the storage units RM1 to RMn depending on whether the LSI 100 is in the normal operation mode or in the self-diagnosis mode. A test address signal TA, a test data input signal TDI, and a test write enable signal TWE are commonly supplied as test signals from the BIST.

  In the selector circuits SL1 to SLn, when the LSI 100 is in the normal operation mode, the address signals UA1 to UAn, the data input signals UDI1 to UDIn, and the write enable signals UWE1 to UWn are selected and given to the storage units RM1 to RMn, respectively. When in the diagnostic mode, the test address signal TA, the test data input signal TDI, and the test write enable signal TWE are selected and applied to the storage units RM1 to RMn in common.

  The respective data outputs DO1 to DOn of the storage units RM1 to RMn are given to the logic circuit UL and to the scan path circuits SC1 to SCn having a comparison function.

  The storage units RM1 to RMn are connected to fuses for relieving the RAM having a faulty part, and the fuses FU1 are configured by collecting the fuses.

  As the fuse, it is conceivable to use a fuse that is blown by irradiating laser light from the outside, or a non-volatile memory such as a flash memory, in addition to a fuse that is blown by an overcurrent. It can also be applied to fuses.

  Scan campus circuits SC1 to SCn are provided in a one-to-one correspondence with storage units RM1 to RMn, and have comparison circuits CM1 to CMn and parallel / serial conversion circuits PS1 to PSn, respectively.

  The comparison circuits CM1 to CMn are circuits that receive the data outputs DO1 to DOn of the storage units RM1 to RMn, respectively, and compare with the expected value EXP output from the self-diagnosis circuit BIST, and the output data of the storage units RM1 to RMn Outputs the corresponding multi-bit comparison results. For example, in the output bits of the RAM, “1” is output for a failed bit and “0” is output for a normal bit.

  The expected value EXP may be given as single-bit data or may be given as multiple-bit data.

  In the case of a single bit, it goes without saying that the same expected value is obtained for all the bits of the data outputs DO1 to DOn of the storage units RM1 to RMn. Can be supplied. In the case of a plurality of bits, generally, the expected value EXP is assumed to be m bits, and each bit is grouped and assigned in a one-to-many or one-to-one group with respect to all bits of the data output of the storage units DO1 to DOn. As a specific example, assuming that m = 2, two bits of the expected value EXP [0] of the even-numbered bits and the expected value EXP [1] of the odd-numbered bits of the data output of each storage unit DO1 to DOn are expected values EXP. It is possible to use as.

  Note that the comparison operation in the comparison circuits CM1 to CMn is controlled by a comparison enable signal CMP output from the self-diagnosis circuit BIST.

  The parallel / serial conversion circuits PS1 to PSn are circuits that take in parallel a plurality of bits of comparison results output from the comparison circuits CM1 to CMn, convert them into serial data SO1 to SOn, and output them. It is desirable that the parallel / serial conversion circuit has a function of fetching the comparison result in parallel a plurality of times and storing failure flag information corresponding to each bit.

  The serial data SO1 to SOn are supplied to the selector circuit SSL, and the serial data supplied to the input terminal selected by the selection signal (not shown) is supplied to the failure position analysis circuit ENC. Note that the selection signal given to the selector circuit SSL may be given from the outside of the LSI 100 via an input pin, may be outputted from the self-diagnostic circuit BIST, or is used for analysis not shown. The configuration may be given from the controller.

  The failure location analysis circuit ENC is a device that receives serial data selected from the serial data SO1 to SOn and outputs failure location information FAIL_POSI and a fail flag FAIL_FLAG.

  The failure position information FAIL_POSI and the fail flag FAIL_FLAG are given to the failure information output logic circuit OL, converted into a desired signal format, and output as a failure position detection result FA_RESULT.

  The failure information output logic circuit OL may be constituted by, for example, a parallel / serial conversion circuit, which converts the failure position information FAIL_POSI and the fail flag FAIL_FLAG into serial data and outputs them.

  The failure position detection result FA_RESULT output from the failure information output logic circuit OL can be read by an LSI test device or the like and used as information for cutting the fuse in the fuse circuit FU1 connected to the storage unit having the failure location.

  Specifically, based on the failure position detection result FA_RESULT, the fuse connected to the corresponding storage unit is cut, and a memory cell block including the failed cell in the corresponding storage unit is prepared in advance as a redundant memory cell. By replacing with a block, it can be used as a normal storage unit.

  When the fuse circuit FU1 is configured by an electrically programmable fuse, the output data of the failure information output logic circuit OL can be processed by a circuit in the LSI 100 to cut the fuse.

Next, the configuration of the part related to the invention will be further described with reference to FIG.
In FIG. 2, the storage units RM1 and RM2 are taken as an example for the sake of convenience, and an example of the serial data SO1 and SO2 output from these will be described.

  As shown in FIG. 2, each of the storage units RM1 and RM2 is composed of a RAM having 8-bit data outputs XDO (0) to XDO (7), and the scan path circuits SC1 and SC2 having a comparison function are also 8 It corresponds to bit data. In FIG. 2, the scan path circuits SC1 and SC2 collectively show a comparison circuit and a parallel / serial conversion circuit for convenience.

  Scan campus circuits SC1 and SC2 receive common expected value EXP, comparison enable signal CMP, and shift control signal SFT.

  The shift control signal SFT may be provided from the outside of the LSI 100 via an input pin, may be output from the self-diagnosis circuit BIST, or is provided from an analysis-dedicated controller (not shown). It may be a configuration.

  Scan campus circuits SC1 and SC2 have a shift function, a comparison function, and a hold function, and one of these functions is activated by a combination of a shift control signal and a comparison enable signal. For example, a shift function is activated by a combination of SFT = 1 and CMP = 0, a comparison function is activated by a combination of SFT = 0 and CMP = 1, and a hold function is activated by a combination of SFT = 0 and CMP = 0. .

  When comparison is performed, an expected value EXP is given. As described above, this expected value may be single-bit data common to all data outputs, or may be appropriately grouped multiple-bit data. May be given.

  For example, the expected value corresponding to the even-numbered bits (XDO (0), XDO (2), XDO (4), XDO (6)) of the data output of the storage unit is given to the EXP (0) terminal as “0”. The expected value corresponding to the odd-numbered bits (XDO (1), XDO (3), XDO (5), XDO (7)) can be set to “1” and given to the EXP (1) terminal.

  For example, when a circuit (memory cell, sense amplifier, write driver, etc.) corresponding to the data output XDO (4) of the storage unit RM2 has a failure, after executing a test using the comparison function of the scan path circuit SC2, The data (failure information) in the scan path circuit SC2 is “00001000” as shown in FIG. This failure information is serially shifted out of the output terminal by the shift function of the scan path circuit SC2, and serial data SO2 is obtained.

  On the other hand, there is no failure in the circuit corresponding to any data output in the storage unit RM1, and the expected value EXP matches the data output in the scan path circuit SC1, so the serial data SO1 becomes “00000000”.

  Note that the scan path circuits SC1 and SC2 are configured to receive serial input signals SI1 and SI2, respectively. In order to prevent malfunction when there is no failure, the serial input signals SI1 and SI2 are “ Shifting in 0 ".

  The serial input signals SI1 and SI2 may be configured to be supplied from the outside of the LSI 100 via input pins, may be configured to be output from the self-diagnosis circuit BIST, or are supplied from an analysis-dedicated controller (not shown). It may be a configuration.

  Serial data SO1 and SO2 are supplied to selector circuit SSL, and serial data selected by a selection signal (not shown) is supplied to failure position analysis circuit ENC as selection output SLSO of selector circuit SSL. Here, for example, if serial data given to the selector circuit SSL is output to the failure position analysis circuit ENC in a predetermined order, the serial data SO2 having failure information is used as the selection output SLSO. The failure information is encoded into the failure position information by being given to the position analysis circuit ENC.

  The failure location analysis circuit ENC includes an OR circuit 1, a flip-flop 2, and a location information counter 3.

  The OR circuit 1 receives the output of the selector circuit SSL and also receives the Q output of the flip-flop 2. The output of the OR circuit 1 is given to the D input of the flip-flop 2 and also to the hold input of the position information counter 3. Given.

  Further, the reset signal RESET is given to the reset input of the flip-flop 2 and the reset information of the position information counter 3, and the clock signal CK is given to the clock input of the flip-flop 2 and the clock input of the position information counter 3. It has a configuration that can be. The clock signal CK is also applied to the scan path circuits SC1 and SC2.

  Here, the Q output of the flip-flop 2 is output from the failure position analysis circuit ENC as a fail flag FAIL_FLAG, and the 3-bit outputs Q (0), Q (1), Q (2) of the position information counter 3 are: The failure position information FAIL_POSI is output from the failure position analysis circuit ENC.

<A-2. Device operation>
Next, the operation of the failure position analysis circuit ENC will be described using the timing chart shown in FIG.

  First, prior to the analysis operation, the reset signal RESET is set to “1” (high potential H) to initialize the flip-flop 2 and the position information counter 3 to “0” (low potential L).

  Next, the reset signal RESET is transitioned to “0” to cancel the reset state, the shift control signal SFT to be applied to the scan path circuits SC1 and SC2 is set to “1”, and the clock signal CK is applied. The shift-out starts from SC1 and SC2, and the count-up of the position information counter 3 starts.

  In the example of FIG. 3, the serial data SO2 output from the scan path circuit SC2 is selected in the selector circuit SSL, and the serial data SO2 is supplied to the failure position analysis circuit ENC. When the count reaches 4 (a value indicating the failure position of the storage unit RM2), the signal applied to the hold input HOLD becomes "1". Thereafter, even if the clock signal CK is given, the count of the position information counter 3 is not increased and the count 4 is held. Fault location information FAIL_POSI is created based on the held count and is output from the fault location analysis circuit ENC.

  In the example of FIG. 3, the data output XDO (4) of the storage unit RM2 becomes “1” to indicate a failure, and therefore the output of the failure position information FAIL_POSI is “100”.

  Further, the fail flag FAIL_FLAG becomes “1” with a delay of one pulse of the clock signal CK after the signal given to the hold input HOLD becomes “1”.

  Such an operation is repeated for all the storage units. For example, when the selector circuit SSL selects and outputs serial data from a plurality of scan path circuits in order, the plurality of storage units have a failure. In addition, the failure location can be analyzed, and the storage unit can be relieved.

<A-3. Effect>
As described above, according to the LSI 100 according to the first embodiment, the serial data output from the scan path circuits SC1 to SCn provided to correspond one-to-one to the plurality of storage units RM1 to RMn. Since SO1 to SOn are received by the selector circuit SSL and the data selected from them is given to the failure location analysis circuit ENC to obtain failure location information FAIL_POSI, one failure location analysis circuit for one storage unit The size can be reduced as compared with the conventional LSI which has been configured to be provided.

<A-4. Modification>
A modification of the first embodiment described above will be described with reference to FIGS.
FIG. 4 is a block diagram showing the overall configuration of the LSI 100A according to the modification. The same components as those of the LSI 100 shown in FIG.

  As shown in FIG. 4, in the LSI 100A, by using the OR circuit OR1 instead of the selector circuit SSL in the LSI 100, the serial data SO1 to SOn output from the scan path circuits SC1 to SCn are ORed. The configuration is given to the failure location analysis circuit ENC.

  In addition, fuses for relieving a RAM having a failure location are commonly connected to the storage units RM1 to RMn, and the fuse circuit FU2 is configured by the one fuse.

  In the LSI 100A shown in FIG. 4, the serial data SO1 to SOn output from the scan path circuits SC1 to SCn are ORed. Therefore, if any one of the storage units RM1 to RMn has a failure, the OR circuit Since the output of OR1 is equal to the serial data sent from the scan path circuit corresponding to the storage unit, if it is sent as it is to the fault location analysis circuit ENC, the fault location can be analyzed.

  Adopting such a configuration is suitable for analysis in the case where fuses for relieving a storage unit having a faulty part are commonly connected to the storage units RM1 to RMn.

  That is, in the configuration in which fuses are commonly connected to the storage units RM1 to RMn, the number of allowable failure storage units is one, and if there are failures in two or more storage units, the LSI This is because it is not necessary to consider the case where a failure exists in two or more storage units because the device itself is treated as a defective product.

  Accordingly, the OR circuit OR1 functions as an automatic selector that automatically selects only the information of the storage unit in which a failure exists and inputs the information to the failure position analysis circuit ENC.

  Note that when a fuse for relieving a storage unit having a faulty part is connected to all the storage units in common, a relief method using the fuse will be described later.

  5 shows the configuration of the main part related to the invention of the LSI 100A. The same components as those of the LSI 100 shown in FIG. 2 are denoted by the same reference numerals, and redundant description is omitted.

  In FIG. 5, storage units RM1 and RM2 are taken as an example for the sake of convenience, and serial data SO1 and SO2 output from these are given to OR circuit OR1, and the result of performing the OR operation is the operation output of OR circuit OR1. It becomes ORSO. In this case, the operation output ORSO is “00001000”. Since “0” is shifted in as the serial input signals SI1 and SI2, “0” is continuously output after “00001000”. This calculation output ORSO (the synthesized fault information) is given to the fault position analysis circuit ENC, whereby the fault information is coded into the fault position information.

  In the example of FIG. 5, the data output XDO (4) of the storage unit RM2 is “1” to indicate a failure, so that the output of the failure position information FAIL_POSI is “100”.

  According to the LSI 100A described above, the OR circuit OR1 receives the serial data SO1 to SOn output from the scan path circuits SC1 to SCn provided in a one-to-one correspondence with the plurality of storage units RM1 to RMn. Since the OR operation is performed and given to the failure location analysis circuit ENC to obtain the failure location information FAIL_POSI, the conventional LSI that has been configured to provide one failure location analysis circuit for one storage unit is used. The size can be reduced compared to the above.

  Further, the test time can be shortened because the data to be given to the failure position analysis circuit ENC is determined by performing only one OR operation on all the serial data SO1 to SOn.

  In addition, since the fuse for relieving the storage unit having the failure location is connected to all the storage units, the number of fuses can be reduced, and a small area, low cost LSI can be realized. realizable.

<B. Second Embodiment>
<B-1. Device configuration>
FIG. 6 is a diagram showing portions related to the invention in the LSI 200 of the semiconductor integrated circuit device according to the second embodiment of the present invention. Note that the same components as those of the LSI 100A described with reference to FIG.

  As shown in FIG. 6, in the LSI 200, the storage unit RM2 is composed of a RAM having 7-bit data outputs XDO (0) to XDO (6), and the scan path circuit SC2 having a comparison function is also 7-bit data. It corresponds to.

  In scan path circuits SC 1 and SC 2, expected values EXP 1 and EXP 2, comparison enable signals CMP 1 and CMP 2, and shift control signals SFT 1 and SFT 2 are respectively used in order to perform comparison operation, serial shift operation, and hold operation independently. , Each is configured to receive independently. However, when it is not necessary to control these independently, they can be connected in common.

  Note that the overall configuration of the LSI 200 is basically the same as the overall configuration of the LSI 100A shown in FIG. 4, and an expected value and a comparison enable signal are sent from the self-diagnosis circuit BIST to each of the storage units RM1 to RMn. The only difference is that they are given separately.

  Also in the LSI 200 shown in FIG. 6, as in the LSI 100A shown in FIG. 4, the serial data SO1 and SO2 output from the scan path circuits SC1 and SC2 are ORed, so that the output of the OR circuit OR1 is stored in the storage unit RM2. If it is equal to the serial data sent from the scan path circuit SC2 corresponding to, and sent as it is to the fault location analysis circuit ENC, the fault location can be analyzed.

  This example shows a case where a circuit (memory cell, sense amplifier, write driver, etc.) corresponding to the data output XDO (4) of the storage unit RM2 has a failure, and a test using the comparison function of the scan path circuit SC2. After execution of the data, the data (failure information) in the scan path circuit SC2 becomes “0000100” as shown in FIG. This failure information is serially shifted out of the output terminal by the shift function of the scan path circuit SC2, and serial data SO2 is obtained.

  On the other hand, there is no failure in the circuit corresponding to any data output in the storage unit RM1, and the expected value EXP matches the data output in the scan path circuit SC1, so the serial data SO1 becomes “00000000”.

  When the shift control signals SFT1 and SFT2 are simultaneously set to “1” and the scan path circuits SC1 and SC2 are simultaneously serial-shifted, “00001000” is shifted out to the operation output ORSO. Since “0” is shifted in as the serial input signals SI1 and SI2, “0” is continuously output after “0000100”.

  This calculation output ORSO (the synthesized fault information) is given to the fault position analysis circuit ENC, whereby the fault information is coded into the fault position information.

  In the example of FIG. 6, since the data output XDO (4) of the storage unit RM2 becomes “1” to indicate a failure, the output of the failure position information FAIL_POSI is “100”.

  When a failure occurs in a plurality of storage units, failure location analysis (coding) is performed according to the failure location first detected at the time of shift-out.

<B-2. Effect>
According to the LSI 200 described above, the OR circuit OR1 receives the serial data SO1 to SOn output from the scan path circuits SC1 to SCn provided in a one-to-one correspondence with the plurality of storage units RM1 to RMn. Since the OR operation is performed and given to the failure location analysis circuit ENC to obtain the failure location information FAIL_POSI, the conventional LSI that has been configured to provide one failure location analysis circuit for one storage unit is used. The size can be reduced compared to the above.

  In addition, since the expected value, the comparison enable signal, and the shift control signal are configured to be separately provided to each of the plurality of storage units, even when the number of output bits of the storage unit varies depending on the storage unit, The failure location analysis circuit ENC can be shared.

<C. Embodiment 3>
<C-1. Device configuration>
FIG. 7 is a diagram showing portions related to the invention in the LSI 300 of the third embodiment of the semiconductor integrated circuit device according to the present invention. Note that the same components as those of the LSI 100A described with reference to FIG.

  As shown in FIG. 6, in the LSI 300, the storage unit RM2 is composed of a RAM having 7-bit data outputs XDO (0) to XDO (6), and the scan path circuit SC2 having a comparison function is also 7-bit data. It corresponds to.

  In scan path circuits SC 1 and SC 2, expected values EXP 1 and EXP 2, comparison enable signals CMP 1 and CMP 2, and shift control signals SFT 1 and SFT 2 are respectively used in order to perform comparison operation, serial shift operation, and hold operation independently. , Each is configured to receive independently. However, the expected values EXP1 and EXP2 and the comparison enable signals CMP1 and CMP2 can be used in common connection when it is not necessary to control them independently.

  Note that the overall configuration of the LSI 300 is basically the same as the overall configuration of the LSI 100A shown in FIG. 4, and an expected value and a comparison enable signal are sent from the self-diagnosis circuit BIST to each of the storage units RM1 to RMn. The only difference is that they are given separately.

  In LSI 300, scan path circuits SC1 and SC2 connected to storage units RM1 and RM2 respectively include AND circuits AN1 and AN2 controlled by shift control signals SFT1 and SFT2 at serial output terminal units, respectively.

  In other words, in scan path circuit SC1, a serial output terminal for outputting 8-bit data received from storage unit RM1 is connected to one input of AND circuit AN1, and a shift control signal is applied to the other input of AND circuit AN1. SFT1 is provided.

  The output of the AND circuit AN1 is given to the OR circuit OR1 as serial data ESO1 from the scan path circuit SC1.

  The scan path circuit SC1 also has a configuration capable of outputting serial data SO1 before AND operation to the outside.

  In scan path circuit SC2, a serial output terminal for outputting 7-bit data received from storage unit RM2 is connected to one input of AND circuit AN2, and a shift control signal is applied to the other input of AND circuit AN2. SFT2 is provided.

  The output of the AND circuit AN2 is provided to the OR circuit OR1 as serial data ESO2 from the scan path circuit SC2.

  The scan path circuit SC2 has a configuration capable of outputting serial data SO2 before AND operation to the outside.

  The LSI 300 having such a configuration has the following characteristics as compared with the LSI 200 shown in FIG.

  That is, in LSI 200, when a failure is found in data output XDO (0) in one of storage units RM1 and RM2, the first bit output of operation output ORSO of OR circuit OR1 is “1”. End up.

  For example, FIG. 7 shows a case where there is a failure in the circuit corresponding to the data output XDO (0) of the storage unit RM1, and after the execution of the test using the comparison function of the scan path circuit SC1, the scan path The data (failure information) in the circuit SC1 is “10000000”. In addition, the storage unit RM2 shows a case where the circuit corresponding to the data output XDO (4) has a failure, and after executing the test using the comparison function of the scan path circuit SC2, it is stored in the scan path circuit SC2. The data (failure information) of “0000100” is “0000100”.

  In such a case, in the LSI 200, the operation output ORSO of the OR circuit OR1 becomes “10001000”, and there is a possibility that the failure position analysis in the failure position analysis circuit ENC cannot be performed accurately.

  However, in LSI 300, such a problem can be solved by adjusting shift control signals SFT1 and SFT2 applied to AND circuits AN1 and AN2.

  That is, in the LSI 300 shown in FIG. 7, when “0” is given as the shift control signal SFT1 to the other input of the AND circuit AN1 of the scan path circuit SC1, the output of the AND circuit AN1 depends on the data in the scan path circuit SC1. Only “0” is output.

  On the other hand, when “1” is given as the shift control signal SFT2 to the other input of the AND circuit AN2 of the scan path circuit SC2, the output of the AND circuit AN2 becomes a value reflecting the data in the scan path circuit SC2.

  Therefore, if the data of the scan path circuit SC2 is shifted out in this state, the output of the OR circuit OR1 becomes equal to the serial data ESO2 sent from the scan path circuit SC2 corresponding to the storage unit RM2, and this is used as it is for failure location analysis. If it is sent to the circuit ENC, the failure location of the storage unit RM2 can be analyzed.

  In order to analyze the failure position of the storage unit RM1, “1” is given as the shift control signal SFT1 to the other input of the AND circuit AN1 of the scan path circuit SC1, while the AND circuit AN2 of the scan path circuit SC2 If the data of the scan path circuit SC1 is shifted out by giving “0” as the shift control signal SFT2 to the other input, the output of the OR circuit OR1 is the serial data sent from the scan path circuit SC1 corresponding to the storage unit RM1. If it becomes equal to ESO1 and is sent as it is to the failure location analysis circuit ENC, the failure location of the storage unit RM1 can be analyzed.

  As shown in FIG. 7, when a plurality of storage units have failures, as described above, the scan path circuit connected to any one of the storage units is given “1” as the shift control signal, By applying “0” as a shift control signal to the scan path circuit connected to the storage unit, the failure location of the one storage unit is analyzed. When the failure position is confirmed, the fuse is repaired. Thereafter, after performing self-diagnosis again, one storage unit is selected from the other storage units, and “1” is given as a shift control signal to the scan path circuit connected thereto, and the other storage units are connected. “0” is given to the scan path circuit as a shift control signal. By repeating such an operation for all the storage units, the failure location can be analyzed even when a plurality of storage units have a failure, and the storage unit can be relieved.

<C-2. Effect>
According to the LSI 300 described above, the OR circuit OR1 receives the serial data SO1 to SOn output from the scan path circuits SC1 to SCn provided to correspond to the plurality of storage units RM1 to RMn on a one-to-one basis. Since the OR operation is performed and given to the failure location analysis circuit ENC to obtain the failure location information FAIL_POSI, the conventional LSI that has been configured to provide one failure location analysis circuit for one storage unit is used. The size can be reduced compared to the above.

  Further, since the scan path circuits SC1 and SC2 connected to the storage units RM1 and RM2 respectively include AND circuits AN1 and AN2 controlled by the shift control signals SFT1 and SFT2 in the serial output terminal unit, respectively, the shift control signal By adjusting SFT1 and SFT2, the failure location can be analyzed even when there are failures in a plurality of storage units, and the storage unit can be relieved.

<D. Embodiment 4>
<D-1. Device configuration>
FIG. 8 is a diagram showing portions related to the invention in the LSI 400 according to the fourth embodiment of the semiconductor integrated circuit device of the invention. Note that the same components as those of the LSI 100A described with reference to FIG.

  As shown in FIG. 8, in the LSI 400, the storage unit RM2 is composed of a RAM having 7-bit data outputs XDO (0) to XDO (6), and the scan path circuit SC2 having a comparison function is also 7-bit data. It corresponds to.

  In scan path circuits SC 1 and SC 2, expected values EXP 1 and EXP 2, comparison enable signals CMP 1 and CMP 2, and shift control signals SFT 1 and SFT 2 are respectively used in order to perform comparison operation, serial shift operation, and hold operation independently. , Each is configured to receive independently. However, if it is not necessary to perform independent control, they can be connected in common.

  In LSI 400, scan path circuits SC1 and SC2 connected to storage units RM1 and RM2, respectively, have AND circuits AN1 and AN2 in their serial output terminal units.

  In other words, in scan path circuit SC1, a serial output terminal unit for outputting 8-bit data received from storage unit RM1 is connected to one input of AND circuit AN1, and the other input of AND circuit AN1 is connected to a scan path circuit. An enable signal EN1 generated based on the serial shift operation of SC1 is provided.

  The output of the AND circuit AN1 is given to the OR circuit OR1 as serial data ESO1 from the scan path circuit SC1.

  The scan path circuit SC1 also has a configuration capable of outputting serial data SO1 before AND operation to the outside.

  In scan path circuit SC2, a serial output terminal for outputting 7-bit data received from storage unit RM2 is connected to one input of AND circuit AN2, and the other input of AND circuit AN2 is connected to a scan path circuit. The enable signal EN2 generated based on the serial shift operation of SC2 is provided.

  The output of the AND circuit AN2 is provided to the OR circuit OR1 as serial data ESO2 from the scan path circuit SC2.

  The scan path circuit SC2 has a configuration capable of outputting serial data SO2 before AND operation to the outside.

  The LSI 400 having such a configuration has the following features compared to the LSI 200 shown in FIG.

  That is, in the LSI 200 shown in FIG. 6, “0” is shifted in as the serial input signals SI1 and SI2 in order to prevent malfunction when there is no failure. For example, the signal of the serial data SO1 could not be given as the serial input signal SI2.

  However, in LSI 400, any signal can be given to serial input signals SI1 and SI2.

  The LSI 400 shown in FIG. 8 includes a bit counter BC that counts bit numbers in synchronization with the serial shift operations of the scan path circuits SC1 and SC2, and further outputs the output value of the bit counter BC to the storage units RM1 and RM2. Compared with the maximum value of the bit number, enable control circuits EC1 and EC2 for outputting enable signals EN1 and EN2 are provided.

  The bit counter BC counts the bit number in synchronization with the serial shift operation of the scan path circuits SC1 and SC2 based on the shift control signal SFT1 or SFT2, and gives the count result to the enable control circuits EC1 and EC2.

  The enable control circuit EC1 is a circuit that performs enable control of the serial data ESO1 of the scan path circuit SC1 connected to the 8-bit storage unit RM1, and the B output of the bit counter BC is 7 or less, that is, the bit number is 7 or less. In some cases, “1” is output as the enable signal EN1, and when the B output of the bit counter BC exceeds 7, “0” is output as the enable signal EN1.

  Accordingly, in the scan path circuit SC1, when the data in the scan path circuit SC1 is shifted out, the data is given to the OR circuit OR1, but after the shift out is completed, the AND circuit AN1 receives “0”. "" Will be output.

  The enable control circuit EC2 is a circuit that performs enable control of the serial data ESO2 of the scan path circuit SC2 connected to the 7-bit storage unit RM2, and the B output of the bit counter BC is 6 or less, that is, the bit number is 6 or less. In some cases, “1” is output as the enable signal EN2, and when the B output of the bit counter BC exceeds 6, “0” is output as the enable signal EN2.

  Therefore, in the scan path circuit SC2, when the data in the scan path circuit SC2 is shifted out, the data is given to the OR circuit OR1, but after the shift out, the AND circuit AN2 receives “0”. "" Will be output.

<D-2. Device operation>
Next, operations of the bit counter BC and the enable control circuits EC1 and EC2 will be described with reference to a timing chart shown in FIG.

  First, prior to the analysis operation, the reset signal RESET is set to “1” to initialize the flip-flop 2 and the position information counter 3 to “0”.

  Next, the reset signal RESET is changed to “0” to release the reset state, the shift control signals SFT1 and SFT2 applied to the scan path circuits SC1 and SC2 are set to “1”, and the clock signal CK is applied. The shift-out starts from the campus circuits SC1 and SC2, and the count-up of the position information counter 3 starts. At the same time, the bit counter BC starts counting up, and the count result is output every moment from the B output.

  The enable control circuit EC1 outputs “1” until the B output reaches 8, but outputs “0” after the B output reaches 8. The enable control circuit EC2 outputs “1” until the B output reaches 7, but outputs “0” after the B output reaches 7.

  Therefore, after the B output reaches 8, the output of the AND circuit AN1 outputs only “0” regardless of the data in the scan path circuit SC1. Similarly, after the B output reaches 7, the output of the AND circuit AN2 outputs only “0” regardless of the data in the scan path circuit SC2.

  Therefore, it is not necessary to shift in “0” as serial input signals SI1 and SI2 after the data is shifted out, and other information can be shifted into scan path circuits SC1 and SC2.

  Therefore, for example, the signal of the serial data SO1 can be given as the serial input signal SI2. This means that the shift control signals SFT1 and SFT2 can be connected in common. Needless to say, any signal may be applied to the serial input signals SI1 and SI2.

  In FIG. 9, after the B output of the bit counter BC reaches 8, the output of the serial data SO1 is represented as an arbitrary value X, and after the B output reaches 7, the serial data SO2 is output. The output is represented as an arbitrary value X.

<D-3. Effect>
As described above, according to the LSI 400 according to the fourth embodiment, any information can be shifted into the scan path circuit even at the time of failure location analysis, which is useful when performing self-diagnosis while performing failure location analysis. . Further, failure position analysis (coding) can be performed while serially shifting out diagnostic information data of the scan path circuit corresponding to the storage unit.

<D-4. Modification>
In the above description, the configuration in which the enable control circuit is provided for each scan path circuit has been described. However, the present invention is not limited to this, and may be arranged according to the type of output bits of the storage unit. .

  That is, for example, if a plurality of storage units are classified into three types according to the number of output bits, it is only necessary to provide three enable control circuits, and storage units having the same number of output bits have one enable control. A common enable signal may be received from the circuit.

  By adopting such a configuration, it is possible to cope with a case where a plurality of types of storage units having different numbers of output bits are provided.

  Note that if all the storage units have the same number of output bits, one enable control circuit may be provided.

<E. Embodiment 5>
<E-1. Device configuration>
FIG. 10 is a diagram showing portions related to the invention in the LSI 500 of the semiconductor integrated circuit device according to the fifth embodiment of the present invention. Note that the same components as those of the LSI 100A described with reference to FIG.

  As shown in FIG. 10, in the LSI 500, the storage unit RM2 is composed of a RAM having 7-bit data outputs XDO (0) to XDO (6), and the scan path circuit SC2 having a comparison function is also 7-bit data. It corresponds to.

  In scan path circuits SC 1 and SC 2, expected values EXP 1 and EXP 2, comparison enable signals CMP 1 and CMP 2, and shift control signals SFT 1 and SFT 2 are respectively used in order to perform comparison operation, serial shift operation, and hold operation independently. , Each is configured to receive independently. However, if it is not necessary to perform independent control, they can be connected in common.

  In LSI 500, scan path circuits SC1 and SC2 connected to storage units RM1 and RM2 respectively include AND circuits AN1 and AN2 at serial output terminal units.

  In other words, in scan path circuit SC1, a serial output terminal unit for outputting 8-bit data received from storage unit RM1 is connected to one input of AND circuit AN1, and the other input of AND circuit AN1 is connected to a scan path circuit. An enable signal EN1 generated based on the serial shift operation of SC1 is provided.

  The output of the AND circuit AN1 is given to the OR circuit OR1 as serial data ESO1 from the scan path circuit SC1.

  The scan path circuit SC1 also has a configuration capable of outputting serial data SO1 before AND operation to the outside.

  In scan path circuit SC2, a serial output terminal for outputting 7-bit data received from storage unit RM2 is connected to one input of AND circuit AN2, and the other input of AND circuit AN2 is connected to a scan path circuit. The enable signal EN2 generated based on the serial shift operation of SC2 is provided.

  The output of the AND circuit AN2 is provided to the OR circuit OR1 as serial data ESO2 from the scan path circuit SC2.

  The scan path circuit SC2 has a configuration capable of outputting serial data SO2 before AND operation to the outside.

  The LSI 500 having such a configuration has the following characteristics as compared to the LSI 200 shown in FIG.

  That is, in the LSI 200 shown in FIG. 6, “0” is shifted in as the serial input signals SI1 and SI2 in order to prevent malfunction when there is no failure. For example, the signal of the serial data SO1 could not be given as the serial input signal SI2.

  However, in LSI 500, any signal can be applied to serial input signals SI1 and SI2.

  In the LSI 500 shown in FIG. 10, the bit number is counted in synchronization with the serial shift operations of the scan path circuits SC1 and SC2 by using the count function of the position information counter 3a included in the failure position analysis circuit ENC. It has become.

  The count information output from the position information counter 3a is compared with the maximum bit number of the storage units RM1 and RM2, and enable control circuits EC1 and EC2 are provided to output enable signals EN1 and EN2.

  In addition to the 3-bit outputs Q (0), Q (1), Q (2) (Q [2: 0]) for outputting the failure position information FAIL_POSI, the position information counter 3a is stored in the storage units RM1 and RM2. It has a 4-bit Q [3: 0] output that can output a value one more than the maximum bit number.

  That is, in the example shown in FIG. 10, since the storage unit RM1 has 8 bits and has the largest number of bits and the maximum bit number is 7, in order to output a value of 8 which is one more than that, 4 bits of B [3: 0] output. Needless to say, the position information counter 3a is a 4-bit counter.

  In addition, it is desirable to add a count stop function to the position information counter 3a in preparation for the case where no failure is detected. In this case, the stop value of the stop function of this counter needs to be larger than the maximum bit number of the storage unit.

  As the shift-out starts from the scan path circuits SC1 and SC2, the position information counter 3a starts counting up, and the count result (Q [3: 0]) is output to the enable control circuits EC1 and EC2 as a B [3: 0] output. Given.

  The enable control circuit EC1 is a circuit that performs enable control of the serial data ESO1 of the scan path circuit SC1 connected to the 8-bit storage unit RM1, and Q [3: 0] (B [3: 0]) When the output is 7 or less, that is, when the bit number is 7 or less, “1” is output as the enable signal EN1, and Q [3: 0] (B [3: 0]) of the position information counter 3a When the output exceeds 7, “0” is output as the enable signal EN1.

  Accordingly, in the scan path circuit SC1, when the data in the scan path circuit SC1 is shifted out, the data is given to the OR circuit OR1, but after the shift out is completed, the AND circuit AN1 receives “0”. "" Will be output.

  The enable control circuit EC2 is a circuit that performs enable control of the serial data ESO2 of the scan path circuit SC2 connected to the 7-bit storage unit RM2, and Q [3: 0] (B [3: 0]) When the output is 6 or less, that is, when the bit number is 6 or less, “1” is output as the enable signal EN2, and Q [3: 0] (B [3: 0]) of the position information counter 3a When the output exceeds 6, “0” is output as the enable signal EN2.

  Therefore, in the scan path circuit SC2, when the data in the scan path circuit SC2 is shifted out, the data is given to the OR circuit OR1, but after the shift out, the AND circuit AN2 receives “0”. "" Will be output.

<E-2. Device operation>
Next, operations of the position information counter 3a and the enable control circuits EC1 and EC2 will be described with reference to timing charts shown in FIGS.

  FIG. 11 shows a timing chart when a failure is detected, and FIG. 12 shows a timing chart when no failure is detected.

  As shown in FIG. 11, first, prior to the analysis operation, the reset signal RESET is set to “1” to initialize the flip-flop 2 and the position information counter 3 a to “0”.

  Next, the reset signal RESET is changed to “0” to release the reset state, the shift control signals SFT1 and SFT2 applied to the scan path circuits SC1 and SC2 are set to “1”, and the clock signal CK is applied. Shift-out starts from the campus circuits SC1 and SC2, and the count-up of the position information counter 3a starts.

  By counting up, the count result is output from the Q [2: 0] output and the Q [3: 0] output.

  When the count of the position information counter 3a reaches 4 (a value indicating the failure position of the storage unit RM2), the signal applied to the hold input HOLD becomes “1”. Thereafter, even if the clock signal CK is given, the count (Q [2: 0], Q [3: 0]) of the position information counter 3a does not increase and the count 4 is held. Based on the held count number, fault position information FAIL_POSI (Q [2: 0]) output is created and output from the fault position analysis circuit ENC.

  In the example of FIG. 11, the data output XDO (4) of the storage unit RM2 is “1” to indicate a failure, so the output of the failure position information FAIL_POSI is “100”.

  Further, the fail flag FAIL_FLAG becomes “1” with a delay of one pulse of the clock signal CK after the signal given to the hold input HOLD becomes “1”.

  Since the Q [3: 0] output of the position information counter 3a holds 4, the enable control circuits EC1 and EC2 continue to maintain 1 output.

  If no failure is detected, as shown in FIG. 12, when the shift-out starts from the scan path circuits SC1 and SC2 and the position information counter 3a starts counting up, the enable control circuit EC1 “1” is output until the 3: 0] output reaches 8, but “0” is output after the B [3: 0] output reaches 8. The enable control circuit EC2 outputs “1” until the B [3: 0] output reaches 7, but outputs “0” after the B [3: 0] output reaches 7.

  Therefore, after the B [3: 0] output reaches 8, the output of the AND circuit AN1 outputs only “0” regardless of the data in the scan path circuit SC1. Similarly, after the B [3: 0] output reaches 7, the output of the AND circuit AN2 outputs only “0” regardless of the data in the scan path circuit SC2.

  Therefore, it is not necessary to shift in “0” as serial input signals SI1 and SI2 after the data is shifted out, and other information can be shifted into scan path circuits SC1 and SC2.

  Therefore, for example, the signal of the serial data SO1 can be given as the serial input signal SI2. This means that the shift control signals SFT1 and SFT2 can be connected in common. Needless to say, any signal may be applied to the serial input signals SI1 and SI2.

  FIG. 12 shows an example in which a count stop function is added to the position information counter 3a. In this example, after the count reaches 8, the value is held.

<E-3. Effect>
As described above, according to the LSI 500 according to the fifth embodiment, any information can be shifted into the scan path circuit even at the time of failure location analysis, which is useful when performing self-diagnosis while performing failure location analysis. .

  In addition, since the enable control circuits EC1 and EC2 are controlled using the count result of the position information counter 3a, the size of the LSI can be compared with the case where a dedicated circuit is provided for controlling the enable control circuits EC1 and EC2. Can be reduced.

<F. Configuration example of storage unit>
In the first to fifth embodiments described above, the storage units RM1 to RMn are configured by a RAM having a redundant function. Hereinafter, the configuration of the RAM having a redundant function will be described with reference to FIGS. An example of the operation will be described.

  FIG. 13 is a block diagram showing the storage unit RM1 having 8-bit data outputs XDO (0) to XDO (7), and shows a configuration having a relief function of the shift redundancy system.

  The storage unit RM1 includes a RAM core C1, a repair control decoder circuit DC, a plurality of input selectors 10 to 18, and output selectors 20 to 27. In FIG. 13, the address signal and write enable signal of the RAM core C1 are not shown.

  As shown in FIG. 13, the RAM core C1 is a 9-bit RAM having a 9-bit data input from DI (0) to DI (8) and a 9-bit data output from DO (0) to DO (8). It is.

  The data inputs DI (0) to DI (8) are configured to receive the outputs of the input selectors 10 to 18, respectively. The input selectors 10 to 18 receive the data inputs XDI (0) to XDI (7) of the storage unit RM1 and are connected so as to share the input selectors 10 to 18 with adjacent inputs. The input is switched between when iosel is “0” and “1”.

  In the input selectors 10 to 18, the smaller data input number of the storage unit RM1 is connected to the 0 input, and when the control signal iosel is “0”, the data given to the 0 input is selected and controlled. When the signal iosel is “1”, data given to one input is selected. The input selector 10 has a configuration in which data 0 is given to the 0 input, and the input selector 18 has data 0 given to the 1 input.

  The data outputs DO (0) to DO (8) are connected to the output selectors 20 to 27 so as to share the output selectors 20 to 27 with adjacent outputs. The outputs are data outputs XDO (0) to XDO (7) of the storage unit RM1, respectively.

  In the output selectors 20 to 27, the data output DO (0) to DO (8) having the smaller number is connected to one input, and the data given to one input when the control signal iosel is “1”. When the control signal iosel is “0”, the data given to the 9 inputs is selected.

  These input selectors 10 to 18 and output selectors 20 to 27 are controlled in conjunction with control signals iosel (0) to iosel (7) output from the repair control decoder circuit DC.

  That is, the control signal iosel (0) controls the selection operation of the input selectors 10 and 11 and the output selector 20, and the control signal iosel (1) controls the selection operation of the input selector 12 and the output selector 21. iosel (2) controls the selection operation of the input selector 13 and the output selector 22, the control signal iosel (3) controls the selection operation of the input selector 14 and the output selector 23, and the control signal iosel (4) The selection operation of the input selector 15 and the output selector 24 is controlled. The control signal iosel (5) controls the selection operation of the input selector 16 and the output selector 25. The control signal iosel (6) is controlled by the input selector 17 and the output selector. 26, the control signal iosel (7) is controlled by the input selector 18 and It is configured to control the selection operation of the output selector 27.

  The relief control decoder circuit DC is supplied with 3 bits ([2: 0]) of relief position code information REP_CODE and a relief enable signal REP_EN from the outside, and the control signals iosel (0) ˜ iosel (7) is output.

  As shown in the bottom column of FIG. 14, when a test for repair analysis is performed or when repair is not necessary (when there is no failure), the repair enable signal REP_EN is set to “0”. At this time, the repair position code information REP_CODE may be an arbitrary value. In this state, the control signals iosel (0) to iosel (7) are all “1”.

  At this time, the data outputs XDO (0) to XDO (7) of the storage unit RM1 are connected to the data outputs DO (0) to DO (7) of the RAM core C1, and the data input XDI (0) of the storage unit RM1. Data inputs DI (0) to DI (7) of the RAM core C1 are connected to .about.XDI (7). Accordingly, in this case, the storage unit RM1 functions as a RAM having 8-bit data input / output.

  The memory cell block corresponding to the data input DI (8) and the data output DO (8) corresponds to a redundant memory cell block, but is not used when the repair enable signal REP_EN is 0.

Next, a case where relief is performed will be described.
When a failure is found in the storage unit RM1, “1” is given as the repair enable signal REP_EN.

  However, when a fuse for repairing a RAM having a faulty part is commonly connected to the storage units RM1 to RMn as in the LSI 100 described with reference to FIG. In some cases, “1” is set as the repair enable signal REP_EN.

  Further, the repair position code information REP_CODE is set according to the failure position, and as the repair position code information REP_CODE, 3-bit (Q [2: 0]) failure position information FAIL_POSI output from the position information counter 3 is used. can do.

  In FIG. 13, it is assumed that a failure exists in the memory cell block corresponding to the data input DI (4) and the data output DO (4). In this case, 4 (binary number) is used as the repair position code information REP_CODE. “100”) is set.

  In this case, it can be seen from the truth table that the control signals iosel (0) to iosel (3) are “1” and the control signals iosel (4) to iosel (7) are “0”.

  Thereby, the data outputs XDO (0) to XDO (3) of the storage unit RM1 are given the data outputs DO (0) to DO (3) of the RAM core C1, and the data output XDO (4) of the storage unit RM1. Data outputs DO (5) to DO (8) of the RAM core C1 are given to .about.XDO (7).

  The data inputs XDI (0) to XDI (3) of the storage unit RM1 are given to the data inputs DI (0) to DI (3) of the RAM core C1, and the data inputs XDI (4) to XDI of the storage unit RM1. (7) is given to the data inputs DI (5) to DI (8) of the RAM core C1.

  Accordingly, the memory unit RM1 functions as a RAM having 8-bit data input / output without using the memory cell blocks corresponding to the data input DI (4) and the data output DO (4) of the RAM core C1.

  In the above example, the remedy method in the case where the memory cell block corresponding to bit number 4 has failed has been described. However, in the truth table shown in FIG. 14, each of the memory cell blocks corresponding to bit numbers 0 to 7 is shown. The repair position code information REP_CODE in the case of repairing is shown.

  FIG. 15 is a block diagram showing the storage unit RM2 having 7-bit data outputs XDO (0) to XDO (7), which is shown as a configuration having a shift redundancy type relief function.

  The storage unit RM2 includes a RAM core C2, a repair control decoder circuit DC, a plurality of input selectors 10-17, and output selectors 20-26. In FIG. 15, the address signal and write enable signal of the RAM core C1 are not shown.

  As shown in FIG. 15, the RAM core C1 is an 8-bit RAM having an 8-bit data input of DI (0) to DI (7) and an 8-bit data output of DO (0) to DO (7). It is.

  The data inputs DI (0) to DI (7) are configured to receive the outputs of the input selectors 10 to 17, respectively. The input selectors 10 to 17 receive the data inputs XDI (0) to XDI (6) of the storage unit RM1 and are connected so as to share the input selectors 10 to 17 with adjacent inputs. The input is switched between when iosel is “0” and “1”.

  In the input selectors 10 to 17, the smaller data input number of the storage unit RM1 is connected to the 0 input. When the control signal iosel is “0”, the data given to the 0 input is selected and controlled. When the signal iosel is “1”, data given to one input is selected. The input selector 10 has a configuration in which data 0 is given to the 0 input, and the input selector 17 has data 0 given to the 1 input.

  The data outputs DO (0) to DO (7) are connected to the output selectors 20 to 26 so as to share the output selectors 20 to 26 with adjacent outputs. The outputs are data outputs XDO (0) to XDO (6) of the storage unit RM2, respectively.

  In the output selectors 20 to 26, the data output DO (0) to DO (7) having the smaller number is connected to one input, and the data given to one input when the control signal iosel is “1”. When the control signal iosel is “0”, the data given to the 9 inputs is selected.

  The input selectors 10 to 17 and the output selectors 20 to 26 are controlled in conjunction with control signals iosel (0) to iosel (6) output from the repair control decoder circuit DC.

  That is, the control signal iosel (0) controls the selection operation of the input selectors 10 and 11 and the output selector 20, and the control signal iosel (1) controls the selection operation of the input selector 12 and the output selector 21. iosel (2) controls the selection operation of the input selector 13 and the output selector 22, the control signal iosel (3) controls the selection operation of the input selector 14 and the output selector 23, and the control signal iosel (4) The selection operation of the input selector 15 and the output selector 24 is controlled. The control signal iosel (5) controls the selection operation of the input selector 16 and the output selector 25. The control signal iosel (6) is controlled by the input selector 17 and the output selector. 26 selection operations are controlled.

  The relief control decoder circuit DC is inputted with 3 bits ([2: 0]) of relief position code information REP_CODE and a relief enable signal REP_EN from the outside, and the control signals iosel (0) ˜ iosel (6) is output.

  Note that the relief operation in the storage unit RM2 is the same as the relief operation in the storage unit RM1 described with reference to FIG. 13 and FIG.

<G. Relief by fuse>
As in the LSI 100 described with reference to FIG. 1, the failure position information FAIL_POSI and the fail flag FAIL_FLAG are converted into serial data via the failure information output logic circuit OL, and read by the LSI test device or the like, and the fuse in the fuse circuit FU1. Therefore, when fuses are provided in one-to-one correspondence with each of the storage units RM1 to RMn, by cutting the fuse corresponding to the corresponding storage unit, the corresponding memory is stored. For example, “1” is given as the repair enable signal REP_EN to the part, and failure position information FAIL_POSI is given as the repair position code information REP_CODE, so that the corresponding storage part can be repaired.

  However, as in the case of the LSI 100 described with reference to FIG. 4, when a configuration in which a fuse for relieving a storage unit having a failure location is commonly connected to a plurality of storage units is described below. Bail out in a simple way.

  As a first method, a method in which the repair position code information REP_CODE shown in FIG. 13 is shared by a plurality of storage units and the repair enable signal REP_EN is not shared is conceivable.

  In this case, the repair enable signal REP_EN signal for the storage unit having the failure can be set to the enable state “1”, and the repair enable signal REP_EN for the storage unit having no failure can be set to the disable state “0”.

  Therefore, even if the repair position code information REP_CODE is given to the storage section without a failure, the replacement to the redundant memory cell block is not executed, and only the storage section without a failure is stored in the repair position code information REP_CODE. A replacement with a redundant memory cell block is performed.

  As a second method, a method in which the repair position code information REP_CODE and the repair enable signal REP_EN are shared by a plurality of storage units is conceivable.

  In this case, the repair enable signal REP_EN is set to the enable state “1” in common to the plurality of storage units.

  In this case, the replacement to the redundant memory cell block based on the repair position code information REP_CODE is executed even in the storage unit having no failure.

  In this case, if there is no failure in the redundant memory cell block, the storage unit after execution of replacement operates as a normal storage unit.

  In general, the area of the redundant memory cell block is smaller than the sum of the areas of the other memory cell blocks, and the probability that there is no failure is high. Therefore, no problem occurs even if replacement is performed in a storage unit without a failure.

  If a failure exists in the redundant memory cell block, it is determined as a defective product by performing self-diagnosis again after the replacement.

  When the second method is applied to an LSI having two types of storage units having different configurations, the following device is required for designing the relief circuit.

  For example, when the storage unit RM1 has 8 bits and the storage unit RM2 has 7 bits as in the LSI 200 shown in FIG. 6, in order to connect these to the same fuse, the repair enable signal REP_EN is in the enable state “1”. Therefore, it is necessary to consider the state where the repair position code information REP_CODE is “111”.

  That is, in the 8-bit storage unit RM1, when the relief position code information REP_CODE is “111”, it indicates that a failure exists in the memory cell block corresponding to the eighth bit, but the 7-bit storage unit RM2 There is no memory cell block corresponding to the eighth bit.

  In this case, when “111” is given as the repair position code information REP_CODE so that the storage unit RM2 is controlled as a normal storage unit having no failure portion, for example, in the non-relief state (iosel) [6: 0] = “1111111”), the repair control decoder circuit DC is designed.

  When the second method is used, if any one of a plurality of storage units has a failure, replacement is executed in all the storage units, so it is necessary to specify the storage unit having the failure. However, when the first method is used, it is necessary to identify the storage unit having a failure and set the repair enable signal REP_EN to “1”.

  This can also be realized by adding a failure determination circuit for each storage unit inside the LSI, or by outputting the serial output data of the parallel-serial conversion circuit to the outside of the LSI and determining it by the LSI test apparatus.

  Note that the failure determination circuit includes, for example, a circuit that performs an OR operation on a plurality of bits output (“1” is defective and “0” is normal) of the comparison circuit, or a serial output of a parallel-serial conversion circuit. A circuit that detects “1” (FAIL information) is considered.

  Further, the failure position detection result FA_RESULT output to the outside via the failure information output logic circuit OL is read by an LSI test device or the like to identify the storage unit having a failure, and for generating a repair enable signal REP_EN for each storage unit The fuse programming can also be determined.

  In the above example, the repair enable signal REP_EN is generated by programming the fuse. However, for example, a register is provided in the output part of the fuse circuit, and the fail flag FAIL_FLAG and the failure position information FAIL_POSI are written in the register. If the output is given to the relief control decoder circuit DC, the relief state test can be performed without programming the fuse.

  Instead of programming the fuse, the fail flag FAIL_FLAG and the failure position information FAIL_POSI may be directly supplied to the repair control decoder circuit DC as the repair enable signal REP_EN and the repair position code information REP_CODE. When the power is turned off, the information of the fail flag FAIL_FLAG and the failure position information FAIL_POSI disappears. Therefore, each time the power is turned on, a self-diagnosis is performed and relief is executed.

1 is a block diagram showing an overall configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. It is a figure which shows the structure of the invention relevant part of the semiconductor integrated circuit device of Embodiment 1 which concerns on this invention. 3 is a timing chart for explaining the operation of the semiconductor integrated circuit device according to the first embodiment of the present invention; It is a block diagram which shows the whole structure of the modification of the semiconductor integrated circuit device of Embodiment 1 which concerns on this invention. It is a figure which shows the structure of the invention relevant part of the modification of the semiconductor integrated circuit device of Embodiment 1 which concerns on this invention. It is a figure which shows the structure of the invention relevant part of the semiconductor integrated circuit device of Embodiment 2 which concerns on this invention. It is a figure which shows the structure of the invention relevant part of the semiconductor integrated circuit device of Embodiment 3 which concerns on this invention. It is a figure which shows the structure of the invention relevant part of the semiconductor integrated circuit device of Embodiment 4 which concerns on this invention. 6 is a timing chart for explaining the operation of the semiconductor integrated circuit device according to the fourth embodiment of the present invention. It is a figure which shows the structure of the invention relevant part of the semiconductor integrated circuit device of Embodiment 5 which concerns on this invention. 10 is a timing chart for explaining the operation of the semiconductor integrated circuit device according to the fifth embodiment of the present invention. 10 is a timing chart for explaining the operation of the semiconductor integrated circuit device according to the fifth embodiment of the present invention. It is a figure explaining the structure of 8-bit RAM which has a redundancy function. It is a figure which shows the truth table explaining operation | movement of 8-bit RAM which has a redundancy function. It is a figure explaining the structure of 7-bit RAM which has a redundancy function. It is a figure which shows the truth table explaining operation | movement of 7-bit RAM which has a redundancy function.

Claims (5)

A plurality of storage units each having a semiconductor storage device having a redundancy function;
A self-diagnosis circuit that outputs a test signal for diagnosing the quality of the operations of the plurality of storage units;
Each of the plurality of storage units is provided on a one-to-one basis, and based on the test signal, each output value of the plurality of storage units and an expected value output from the self-diagnostic circuit in units of memory cells A plurality of comparison circuits that compare and match the expected value with the expected value to determine whether the operation is good or bad and output as bit data;
A plurality of parallel / serial conversion circuits which are provided one-to-one with respect to the plurality of comparison circuits, and which respectively receive the comparison results in the plurality of comparison circuits in parallel, and convert the serial output data into output data;
An OR circuit that receives the serial output data output from each of the plurality of parallel / serial conversion circuits and performs an OR operation;
A semiconductor integrated circuit device comprising: a failure location analysis circuit that identifies a location of a failure memory cell block based on an operation output of the OR circuit.   2. The semiconductor integrated circuit device according to claim 1, wherein the plurality of parallel / serial conversion circuits include a gate circuit that is provided in each output unit and whose gate operation is controlled by a shift control signal that controls a serial shift operation. The semiconductor integrated circuit device includes:
A bit counter that counts a bit number of the serial output data in synchronization with a serial shift operation of the plurality of parallel / serial conversion circuits;
Receiving at least one enable control circuit for receiving a count result from the bit counter and outputting a predetermined enable signal when the count result exceeds a predetermined value;
2. The semiconductor integrated circuit device according to claim 1, wherein the plurality of parallel / serial conversion circuits include gate circuits which are provided in respective output units and whose gate operation is controlled by the enable signal. The failure location analysis circuit is:
For the position information for specifying the position of the failed memory cell block by counting the operation output of the OR circuit and stopping the counting when the bit indicating the defect of the memory cell block is reached in the operation output Have a counter,
The semiconductor integrated circuit device includes:
In response to the count result from the position information counter, the counter further includes at least one enable control circuit that outputs a predetermined enable signal when the count result exceeds a predetermined value.
2. The semiconductor integrated circuit device according to claim 1, wherein the plurality of parallel / serial conversion circuits include gate circuits which are provided in respective output units and whose gate operation is controlled by the enable signal. A plurality of the at least one enable control circuit are arranged according to the type of the number of output bits of the plurality of storage units,
5. The semiconductor integrated circuit device according to claim 3, wherein the predetermined value is set for each enable control circuit so as to correspond to the maximum bit number of each of the storage units having different numbers of output bits.

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