JP4967487B2 - Insulated gate bipolar transistor - Google Patents

Description

  The present invention relates to an insulated gate bipolar transistor.

  Conventionally, an insulated gate bipolar transistor (hereinafter referred to as IGBT) shown in FIG. 5 is known. FIG. 5 is a view omitting a part of a longitudinal sectional view of a conventional IGBT having a trench gate structure. In the IGBT shown in FIG. 5, a field stop layer (hereinafter referred to as FS layer) 4 and a P + layer 3 having an impurity concentration higher than that of the FS layer 4 are formed from the back surface of the N− layer 5. A P-type channel P region 6 is formed on the surface of the N− layer 5, and a plurality of trenches 10 are formed below the surface of the channel P region 6. A gate electrode 9 is formed inside each trench 10 via a silicon oxide film 11. A P-type P body layer 7 having an impurity concentration higher than that of the channel P region 6 is formed below the surface of the channel P region 6 between the trenches 10. An N-type emitter N layer 8 having an impurity concentration higher than that of the FS layer 4 is formed below the surface of the channel P region 6 and around the trench 10. The emitter N layer 8 is formed of the P body layer 7. Contact. An emitter electrode 13 is formed on the surface of the channel P region 6, and the emitter electrode 13 is in contact with the emitter N layer 8 and the P body layer 7. A BPSG (Borophosphosilicate glass) layer 12 is interposed between the emitter electrode 13 and the silicon oxide film 11.

Japanese Patent Laying-Open No. 2005-333112 (paragraphs 34 and 35, FIG. 1)

  However, in the conventional IGBT, if the current density becomes too high, the NPN bipolar transistor (BJT) parasitic near the channel of the N-channel power MOSFET operates, the thyristor operates as a whole element, and the latch-up breakdown occurs. There is.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to realize an IGBT that is difficult to cause latch-up destruction.

In order to achieve the above object, the invention according to claim 1 provides:
A first conductivity type first semiconductor layer (3);
A collector electrode (2) formed on the back surface of the first semiconductor layer;
A second semiconductor layer (4, 5) of the second conductivity type formed on the surface of the first semiconductor layer;
A third semiconductor layer (6) of the first conductivity type formed on the surface of the second semiconductor layer;
A second conductivity type fourth semiconductor layer (8) in contact with the third semiconductor layer, and a gate electrode (9) adjacent to the third semiconductor layer via the first insulating layer (11);
In an insulated gate bipolar transistor (1) having an emitter electrode (13) adjacent to the third semiconductor layer and the fourth semiconductor layer ,
When the region functioning as an insulated gate bipolar transistor is a cell region, and the periphery of the cell region is an outer peripheral region,
The third semiconductor layer of the cell region is formed to extend to the outer peripheral region;
The first conductivity type high concentration region (15) having an impurity concentration higher than that of the third semiconductor layer and having a bottom reaching the inside of the second semiconductor layer is formed in the first region of the outer peripheral region. 3 formed below the surface of the semiconductor layer ;
A connection electrode (18) electrically connected to the emitter electrode (13) is formed in the outer peripheral region;
When the cell region is on the inner side and the outer peripheral region is on the outer side, the first conductivity type low concentration region (16) in which the impurity concentration is set lower than that of the third semiconductor layer (6). ) Is formed below the surface of the second semiconductor layer (4, 5) outside the high concentration region (15), and the inner end of the low concentration region is formed at the second insulating layer (17). ) Through the connection electrode, and the inner end of the low concentration region overlaps the outer end of the third semiconductor layer.

In the outer peripheral region around the cell region, the impurity concentration is set higher than that of the first conductivity type third semiconductor layer, and the bottom of the first conductivity type reaches the inside of the second semiconductor layer. Since the concentration region is formed below the surface of the third semiconductor layer, the electric field around the high concentration region can be strengthened. Therefore, the breakdown voltage of the portion composed of the high concentration region and the second semiconductor layer is set to the cell region. It can be lower than the breakdown voltage.
Therefore, when the IGBT breaks down, before the cell region starts to breakdown, the portion composed of the high-concentration region and the second semiconductor layer starts to breakdown first, so that the IGBT is difficult to latch-up.
As in the embodiment described later, if the first conductivity type is P type and the second conductivity type is N type, the portion composed of the high concentration region, the second semiconductor layer, and the first semiconductor layer is a PNP transistor. Because of the structure, when the IGBT breaks down, the PNP transistor structure portion starts to break down with the breakdown characteristics of the PNP transistor prior to the cell region, so that the IGBT is difficult to latch-up.

  Below the surface of the second semiconductor layer in the outer peripheral region, a first conductivity type low concentration region having an impurity concentration set lower than that of the third semiconductor layer is formed so as to overlap the third semiconductor layer. Therefore, when the low-concentration region is depleted during reverse bias application, the surface electric field in the outer peripheral region can be relaxed, so that a high breakdown voltage can be obtained.

In the invention described in claim 2, in insulated gate bipolar transistor according to claim 1 (1), internal subjected trench (10 of the third semiconductor layer (6) the second semiconductor layer from the surface of (4) , 23), the gate electrode (9) is formed inside through the first insulating layer (11), and the trenches involved in the operation of the cell region are defined as active trenches (10). In this case, a technical means is used in which a dummy trench (23) that is not involved in the operation is disposed adjacent to the active trench.

Since the dummy trench that is not involved in the operation of the cell region is disposed adjacent to the active trench, the potential difference between the cell region and the high-concentration region of the first conductivity type is increased, and the current value intersecting the cell region is increased. Therefore, the breakdown voltage of the cell region can be increased.
In addition, by disposing a dummy trench, the breakdown voltage of the cell region can be increased without increasing the diffusion area of the high concentration region.

According to a third aspect of the present invention, in the insulated gate bipolar transistor (1) according to the first or second aspect, a plurality of the high concentration regions (15) are formed in the third semiconductor layer (6) in the outer peripheral region. ) Using technical means that they are juxtaposed below the surface.

  Since the plurality of high concentration regions are arranged in parallel below the surface of the third semiconductor layer in the outer peripheral region, the current value intersecting with the cell region can be increased, so that the breakdown voltage of the cell region can be increased.

In the embodiment described later, the P type corresponds to the first conductivity type, and the N type corresponds to the second conductivity type. The P + layer 3 corresponds to the first semiconductor layer, and the FS layer 4 and the N− layer 5 correspond to the second semiconductor layer. Further, the channel P region 6 corresponds to the third semiconductor layer, the emitter N layer 8 corresponds to the fourth semiconductor layer, and the P + layer 15 corresponds to the high concentration region of the first conductivity type. The RESURF P layer 16 corresponds to the first conductivity type low concentration region.
In addition, the code | symbol in the said parenthesis respond | corresponds with the code | symbol described in embodiment of the invention mentioned later.

  An embodiment according to the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view showing a part of the IGBT according to this embodiment with a part thereof omitted. FIG. 2 is an explanatory view showing a part of FIG. 1 in an enlarged manner, (a) is an enlarged view of a part of a cell region, (b) is an enlarged view of a cross section taken along the line AA in (d), (C) is the elements on larger scale of the RESURF P layer formed in the outer periphery area | region, (d) is a top view which shows a part of outer periphery area | region.

  The IGBT 1 includes a P + layer (substrate) 3 into which a P-type impurity is introduced at a high concentration, and a collector electrode 2 is formed on the back surface of the P + layer 3. An FS layer 4 made of an N-type impurity diffusion layer is formed on the surface of the P + layer 3, and a low-concentration N− layer 5 is formed on the surface of the FS layer 4. The FS layer 4 is formed from the back side of the chip by ion implantation and heat treatment of an N-type impurity having a dose sufficient to stop the electric field when the IGBT 1 is off.

In this embodiment, the maximum surface concentration of the P + layer 3 is 7.0e17 cm ⁻³ and the diffusion depth is 0.5 μm. The maximum impurity concentration of the FS layer 4 is 3.0e16 cm ⁻³ and the depth of the impurity layer is 1.0 μm. Further, the impurity concentration of the N− layer 5 is 7.1e13 cm ⁻³ and the layer thickness is 120 μm.

  A channel P region 6 into which a P-type impurity is introduced is formed from the surface of the N − layer 5 to the inside in the cell region. Under the surface of the channel P region 6, a plurality of active trenches 10 that are involved in the operation of the cell region are formed as a set of two adjacent trenches. Dummy trenches 23 that are not involved in the operation are arranged adjacent to each other. Each active trench 10 and dummy trench 23 are each formed in a groove shape, and the bottom of each trench reaches the inside of the N − layer 5.

In this embodiment, the surface concentration of the channel P region 6 is 3e17 cm ⁻³ and the diffusion depth is 4.0 μm. Moreover, each trench depth of the active trench 10 and the dummy trench 23 is 5.0 μm, each trench width is 1.0 μm, and an interval between adjacent trenches is 4.0 μm.

  As shown in FIG. 2A, the gate electrode 9 is embedded in each active trench 10 and the dummy trench 23, and the periphery of the gate electrode 9 is covered with the silicon oxide film 11. A P body layer 7 into which a P-type impurity is introduced is formed under the surface of the channel P region 6 formed between each active trench 10, and the boundary between the P body layer 7 and each active trench 10. An emitter N layer 8 into which an N-type impurity is introduced is formed in the channel P region 6 at the site. A BPSG layer 12 is formed on the surface of the silicon oxide film 11 covering the surface of each gate electrode 9, and an emitter electrode 13 is formed on the surface of the BPSG layer 12. The P body layer 7 formed between the active trenches 10 is in contact with the emitter electrode 13.

As shown in FIG. 2B, a channel P region 6a extending from the channel P region 6 of the cell region is formed in the outer peripheral region formed around the cell region, and the channel P region 6a Below the surface, two P + layers 15 which are P-type high concentration regions in which the P-type impurity concentration is set higher than that of the channel P region 6a are formed in a circular shape at intervals (see FIG. FIG. 2 (d)). The bottom of each P + layer 15 reaches the inside of the N− layer 5. That is, the P + layer 15 and the N− layer 5 form a PN junction Zener diode structure, and the cell region is surrounded by the double Zener diode structure.
A silicon oxide film 14 is formed on the surface of each P + layer 15 and the surrounding channel P region 6, and an emitter electrode 13 is formed on the surface of the silicon oxide film 14.

In this embodiment, the width of each P + layer 15 is 8 μm, the surface concentration is 1e18 to 1e19 cm ⁻³ , and the diffusion depth is 8.0 to 9.0 μm, respectively. The distance between the P + layers 15 is 40 μm. The layer thickness of the silicon oxide film 11 is 1000 mm.

As shown in FIG. 1, the P-type low concentration region in which the P-type impurity concentration is set lower than that of the channel P region 6 when the cell region is the inner side and the outer peripheral region is the outer side. The RESURF P layer 16 is formed under the surface of the N− layer 5 outside the outermost P + layer 15. That is, the outermost P + layer 15 is surrounded by the RESURF P layer 16.
As shown in FIG. 2C, the inner end portion of the RESURF P layer 16 overlaps the outer end portion of the channel P region 6a. A silicon oxide film 17 is formed on the surface of the RESURF P layer 16, and a BPSG layer 20 is formed on the surface of the silicon oxide film 17. A connection electrode 18 electrically connected to the emitter electrode 13 is formed on the surface of the inner end portion of the silicon oxide film 17. A BPSG layer 19 is formed on the surface of the connection electrode 18, and an emitter electrode 13 is formed on the surface of the BPSG layer 19.

In this embodiment, the surface density of the RESURF P layer 16 is 1.0 to 1.2e12 cm ⁻² and the diffusion depth is 8.0 μm. The connection electrode 18 is made of polysilicon.

  As shown in FIG. 1, an N-type channel into which an N-type impurity is introduced is located at a portion away from the outer end of the RESURF P layer 16 and below the surface of the N-layer 5 at the end of the IGBT 1. A stopper layer 22 is formed, and an equipotential ring 21 is formed on the surface of the N-type channel stopper layer 22. That is, the outer peripheral region is surrounded by the equipotential ring 21 and the N-type channel stopper layer 22.

As shown in FIG. 2B, since the diffusion depth of the P + layer 15 is deeper than the channel P region 6a and protrudes into the N− layer 5, the electric field around the P + layer 15 is strengthened. Therefore, the breakdown voltage of the Zener diode structure can be made lower than the breakdown voltage of the cell region. For example, the breakdown voltage can be set to 50 to 100 V lower than the breakdown voltage in the cell region.
FIG. 3 is an equivalent circuit of the IGBT 1. ZD in the figure is a PN junction Zener diode formed by each P + layer 15 and N− layer 5. When a voltage is applied between the collector and emitter of the IGBT 1, the breakdown voltage of the Zener diode structure portion is lower than the breakdown voltage of the cell region as described above, and before the cell region starts breakdown, Since the Zener diode structure starts to breakdown, current does not concentrate in the cell region, so that latch-up breakdown is difficult. Note that when the Zener diode structure portion and the P + layer 3 on the back surface thereof are combined, a PNP transistor is formed, so that the Zener diode structure portion breaks down due to the breakdown characteristics of the PNP transistor.
Note that by forming three or more P + layers 15 and increasing the collector current at the time of breakdown, the latch-up breakdown can be made even more difficult.

FIG. 4 is a graph showing the results of an experiment conducted to compare the output characteristics of the IGBT of the present invention and the conventional IGBT. In the figure, the “present invention” is an IGBT having the structure shown in FIG. 1 and having at least one P + layer 15. The “conventional” is an IGBT having the structure shown in FIG. 5 and does not include the dummy trench 23, the P + layer 15, and the RESURF P layer 16.
When the breakdown voltage of the collector-emitter voltage is compared, the breakdown voltage of the IGBT of the present invention is higher than that of the conventional IGBT by Va. That is, since a large amount of current can flow until the IGBT cell breaks down, the IGBT of the present invention is harder to latch-up than the conventional IGBT.

  In the figure, “ZD1 layer” indicates an IGBT of the present invention having one P + layer 15, and “ZD2 layer” indicates an IGBT of the present invention having two P + layers 15. Comparing the collector current when the IGBT breakdown, the collector current in the ZD2 layer is larger by Ia than in the ZD1 layer. That is, the structure having two P + layers 15 can cause a larger collector current to flow at the time of breakdown than the structure having one layer, so that latch-up breakdown is difficult.

  In addition, when the RESURF P layer 16 is depleted when a reverse bias is applied, the surface electric field in the outer peripheral region can be relaxed, so that a high breakdown voltage can be obtained. Further, the magnitude relationship of the breakdown voltage of each part is the RESURF P layer 16 ≧ cell region ≧ Zener diode structure, and therefore, the portion of the Zener diode structure starts breakdown before the cell region starts breakdown. Since it does not concentrate, latch-up is difficult to destroy. The breakdown voltage in the RESURF P layer 16 is, for example, 1500 to 1600V.

Moreover, since the dummy trench 23 is disposed adjacent to the active trench 10, the breakdown voltage of the cell region can be increased. For example, the breakdown voltage of the cell region can be increased from 1200V to about 1450V. Further, since the dummy trench 23 is disposed adjacent to the active trench 10, the potential difference between the cell region and the P + layer 15 is increased, and the current value crossing the cell region can be increased. The breakdown voltage of the cell region can be increased without increasing the diffusion area.
As described above, when the IGBT 1 of the above embodiment is used, it is possible to realize an IGBT that is difficult to cause latch-up destruction.

It is a longitudinal cross-sectional view which abbreviate | omits and shows a part of IGBT which concerns on embodiment of this invention. FIG. 2 is an explanatory view showing a part of FIG. 1 in an enlarged manner, (a) is an enlarged view of a part of a cell region, (b) is an enlarged view of a cross section taken along the line AA in (d), (C) is the elements on larger scale of the RESURF P layer formed in the outer periphery area | region, (d) is a top view which shows a part of outer periphery area | region. It is an equivalent circuit of IGBT1. It is a graph which shows the experimental result done in order to compare the output characteristic of IGBT of this invention, and conventional IGBT. It is a figure which abbreviate | omits and shows the longitudinal cross-sectional view of IGBT of the conventional trench gate structure.

Explanation of symbols

1 .... IGBT, 2 .... collector electrode, 3 .... P + layer (first semiconductor layer),
4. .. FS layer (second semiconductor layer), 5. .. N-layer (second semiconductor layer),
6, 6a .. channel P region (third semiconductor layer), 7 .. P body layer,
8 .. Emitter N layer (fourth semiconductor layer), 9 .. Gate electrode,
10 .. Active trench, 11, 14, 17 .. Silicon oxide film,
12, 19, 20... BPSG layer, 13 .. Emitter electrode,
15. P + layer (first conductivity type high concentration region),
16 .. RESURF P layer (low concentration region of the first conductivity type), 18 ..Connection electrode,
21 ... Equipotential ring, 22 .... N-type channel stopper layer.

Claims (3)

A first semiconductor layer of a first conductivity type;
A collector electrode formed on the back surface of the first semiconductor layer;
A second semiconductor layer of a second conductivity type formed on the surface of the first semiconductor layer;
A third semiconductor layer of a first conductivity type formed on the surface of the second semiconductor layer;
A fourth semiconductor layer of a second conductivity type adjacent to the third semiconductor layer;
A gate electrode adjacent to the third semiconductor layer via a first insulating layer;
In an insulated gate bipolar transistor having an emitter electrode adjacent to the third semiconductor layer and the fourth semiconductor layer ,
When the region functioning as an insulated gate bipolar transistor is a cell region, and the periphery of the cell region is an outer peripheral region,
The third semiconductor layer of the cell region is formed to extend to the outer peripheral region;
The impurity concentration is set to be higher than that of the third semiconductor layer, and the first conductivity type high concentration region whose bottom reaches the inside of the second semiconductor layer is the third semiconductor layer in the outer peripheral region. and that it is formed under the surface of,
A connection electrode electrically connected to the emitter electrode is formed in the outer peripheral region;
When the cell region is on the inner side and the outer peripheral region is on the outer side, the first conductivity type low concentration region whose impurity concentration is set lower than that of the third semiconductor layer is the high concentration The low concentration region is formed below the surface of the second semiconductor layer outside the region, and the inner end of the low concentration region is located below the connection electrode via the second insulating layer. An insulated gate bipolar transistor characterized in that an inner end of the region overlaps an outer end of the third semiconductor layer . A trench is formed from the surface of the third semiconductor layer to the inside of the second semiconductor layer,
When the gate electrode is formed inside through the first insulating layer and a trench that is involved in the operation of the cell region is an active trench, a dummy trench that is not involved in the operation is disposed adjacent to the active trench. The insulated gate bipolar transistor according to claim 1, wherein the bipolar transistor is an insulated gate bipolar transistor. Insulated gate bipolar transistor according to claim 1 or claim 2, wherein a plurality of said high concentration region is arranged below the surface of the third semiconductor layer of the peripheral region.

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