JP4967617B2 - Heat treatment mask manufacturing method - Google Patents

Description

  The present invention relates to a heat treatment mask that shields light applied to the surface of a wafer. The present invention also relates to a heat treatment apparatus using the heat treatment mask, a method for heat treating a wafer using the heat treatment mask, and a method for manufacturing the heat treatment mask. The heat treatment mask of the present invention is used in a heat treatment process when manufacturing a semiconductor device such as a switching element, a diode, a light emitting element, a light receiving element, or a micromachine.

  In the process of manufacturing a semiconductor device, heat treatment is performed on the wafer. The heat treatment is required for various purposes, and is performed, for example, when activating impurities introduced into the wafer or when forming a thermal oxide film on the surface of the wafer. In this type of heat treatment, there is a demand for heating the front side of the wafer to a high temperature while maintaining the back side of the wafer at a low temperature. By heating only the surface side of the wafer to a high temperature, it is possible to activate only the impurities introduced into the shallow region from the surface of the wafer. Alternatively, a thin oxide film can be formed on the surface of the wafer by heating only the surface side of the wafer to a high temperature. In order to meet these demands, a heat treatment method using light generated by a light source such as a flash lamp or a laser has been developed. For example, a rapid thermal process (hereinafter referred to as “RTP”) using a flash lamp irradiates the wafer surface with light having a pulse width of several milliseconds, thereby lowering the back surface of the wafer to a low temperature. While maintaining, the surface side of the wafer can be heated to a high temperature.

  Patent Document 1 proposes a technique that uses a stencil mask in RTP using a flash lamp. Patent Document 1 proposes a technique of using a stencil mask having an opening to irradiate light only on a local area on the surface of the wafer and forming a thermal oxide film only on the local area on the surface of the wafer. .

Japanese Patent Laying-Open No. 2005-19650 (see FIG. 12 of that gazette)

By the way, in the conventional heat treatment method using light, it is general to irradiate the entire surface of the wafer with light. When light is applied to the entire surface of the wafer, a shallow region of the wafer surface is heated to a high temperature over the entire surface of the wafer. Accordingly, a high temperature region is formed over the entire surface of the wafer. On the other hand, the deep region of the wafer is maintained at a low temperature. For this reason, a difference occurs between the amount of thermal expansion on the front side of the wafer and the amount of thermal expansion on the back side of the wafer, and internal stress is generated between the front side and the back side of the wafer. As a result, a situation occurs in which the wafer is deformed.
In the case of heating only a local region on the surface of the wafer as in Patent Document 1, since the high temperature region is limited to the local region on the surface of the wafer, the amount of thermal expansion on the surface side of the wafer is small. For this reason, the internal stress generated between the front surface side and the back surface side of the wafer is small, and deformation of the wafer does not occur. When only a local region on the surface of the wafer is heated as in Patent Document 1, the deformation of the wafer is not a problem.
On the other hand, when heat-treating a wide area of the wafer surface, the thermal expansion area on the front surface side of the wafer is added together in a wide area, so that the total thermal expansion amount on the front surface side of the wafer and the entire back surface side of the wafer are The difference in thermal expansion amount is large, and the wafer is greatly deformed by internal stress generated between the front surface side and the back surface side of the wafer. The technique of Patent Document 1 cannot be used when heat-treating a wide range of the wafer surface, and cannot address the above-described problems.
An object of the present invention is to provide a technique for suppressing the occurrence of deformation of a wafer in heat treatment using light.

The technique disclosed in this specification is characterized by using a mask in heat treatment using light. The technology disclosed in this specification can propose two types of heat treatment masks. Any of the heat treatment masks can provide a common effect that the thermal expansion region of the wafer surface is divided into a plurality of portions. It should be noted that a more useful heat treatment mask can be provided by combining techniques relating to two types of heat treatment masks.
The first type of heat treatment mask includes a light shielding region that shields light and a light transmission region that is partitioned by the light shielding region. The light transmission region is characterized by being partitioned into a plurality of light transmission holes by a partition wall that shields light.
The second type of heat treatment mask includes a light shielding region that shields light and a plurality of light transmission regions partitioned by the light shielding region. Furthermore, it is preferable that the light shielding region is disposed at a position that shields at least a part of the light applied to the dicing line. The “light irradiated to the dicing line” refers to light irradiated to the dicing line of the wafer when it is assumed that nothing exists between the light source and the dicing line of the wafer.
Here, the light transmission region refers to a region formed in the heat treatment mask corresponding to a region to be irradiated with light on the surface of the wafer. Typically, the light transmission region is formed corresponding to a plurality of semiconductor devices built on the surface of the wafer.

First, features of the first type heat treatment mask and the second type heat treatment mask will be briefly described.
The first type of heat treatment mask is characterized in that a light shielding partition is provided in a light transmission region and a plurality of light transmission holes are formed. The light shielding partition forms an area with a small amount of light irradiation on the surface of the wafer. When light is irradiated using the first type of heat treatment mask, the light passing through the light transmission holes is diffracted and overlapped on the surface of the wafer below the light shielding partition. Light is applied to the surface of the wafer by being superimposed below the light shielding partition. At this time, the amount of light irradiation is relatively small in a range located below the light shielding partition on the surface of the wafer. As a result, the thermal expansion region on the surface of the wafer is divided from the adjacent thermal expansion regions, and the deformation of the wafer is suppressed. If the first type of heat treatment mask is used, light can be irradiated with a small amount of light in the area located below the light shielding partition on the surface of the wafer. Can be implemented.
In the second type heat treatment mask, a light shielding region is formed between the light transmitting region and the light transmitting region, and the light shielding region is disposed at a position where at least a part of the light irradiated to the dicing line is shielded. It is characterized by being. In the second type of heat treatment mask, light passing through the light transmission region may be diffracted and overlapped on the surface of the wafer below the light shielding region, or a light shielding region that does not substantially overlap the light is formed. May be. When this second type of heat treatment mask is used to irradiate light, the amount of light irradiation is relatively small in a range located below the light shielding region on the surface of the wafer (in some cases, the light is emitted). Not irradiated). As a result, the thermal expansion region on the surface of the wafer is divided from the adjacent thermal expansion regions, and the deformation of the wafer is suppressed. Note that, below the light shielding area on the surface of the wafer, the amount of light irradiation is reduced and the heat treatment may be insufficient. However, even if the heat treatment is insufficient, the characteristics of the semiconductor device to be manufactured are affected. Will not affect. The technique of arranging the light shielding region at a position where a part of the dicing line is shielded can provide extremely useful results.

  As described above, the first type heat treatment mask and the second type heat treatment mask are both configured to form a distribution of light irradiation amount on the surface of the wafer (light shielding partitions and light shielding regions). ) Has a technical feature. As a result, both the first-type heat treatment mask and the second-type heat treatment mask can be obtained by the prior art in which the thermal expansion region on the surface of the wafer is divided from the adjacent thermal expansion regions to suppress the deformation of the wafer. Can provide no contribution.

Hereinafter, the characteristics of the first type heat treatment mask and the second type heat treatment mask will be described in detail.
The first type of heat treatment mask includes a light shielding region that shields light and a light transmission region that is partitioned by the light shielding region. The light transmission region is characterized by being partitioned into a plurality of light transmission holes by a partition wall that shields light. The first type heat treatment mask may be composed of a single layer or a plurality of layers. In the case where the heat treatment mask is composed of a plurality of layers, the light shielding region only needs to be formed in at least one of the layers of the heat treatment mask, and the light shielding partition also includes at least one of the heat treatment masks. What is necessary is just to be formed in the layer. Further, the light transmission hole may be a through hole in which no substance exists, may be formed of a light transmissive material capable of transmitting light, and is formed by assembling the through hole and the light transmissive material. It may be a region. In the case where a light transmissive material is used for the light transmissive hole, the light transmissive region may be formed of a single type of light transmissive material, or a plurality of types of light transmissive materials are formed together. May be. When a light transmissive material is used for the light transmission hole, it is preferable to change the type of the light transmissive material used in accordance with the type of light generated by the light source.
When light is irradiated using the above-mentioned first type heat treatment mask, the amount of light irradiation is relatively reduced in a range located below the light shielding partition on the surface of the wafer. On the other hand, in the range located below the light transmission hole on the surface of the wafer, the amount of light irradiation is relatively large. For this reason, a distribution is formed in the amount of light irradiated onto the surface of the wafer, and a region with a large amount of light irradiated is divided into a plurality of regions by a region with a small amount of light irradiated. As a result, a similar distribution is formed in the rate of temperature rise on the wafer surface. The technique disclosed in this specification is characterized in that a high irradiation region having a high temperature rising rate and a low irradiation region having a low rising rate are formed on the surface of the wafer. That is, the high irradiation area is not continuously formed over the entire surface of the wafer, and is divided into a plurality of areas by the low irradiation area. The high irradiation area is formed in a dispersed state on the surface of the wafer. FIG. 1 shows this state. FIG. 1A shows a case where the high irradiation region 2 is formed in a continuous state over the entire surface of the wafer 1, and FIG. 1B shows a state where the high irradiation region 2 is dispersed on the surface of the wafer 1. It is a case where it is formed by. If the high irradiation area 2 is formed in a continuous state over the entire surface of the wafer 1, the thermal expansion area on the surface side of the wafer 1 is added in a wide range. The difference between the expansion amount and the total thermal expansion amount on the back side of the wafer 1 is large, and the wafer 1 is greatly deformed. On the other hand, when the high irradiation region 2 is formed in a state of being dispersed on the surface of the wafer 1, the thermal expansion region of each high irradiation region 2 is divided from the thermal expansion region of the adjacent high irradiation region 2. Since the deformation occurs within the range of each high irradiation area 2, the entire deformation of the wafer 1 can be suppressed. Note that the temperature of the low irradiation region may eventually reach a high temperature necessary for the heat treatment. Even in this case, when the high irradiation region 2 is divided by the low irradiation region, the thermal expansion region of each high irradiation region 2 is divided from the thermal expansion region of the adjacent high irradiation region 2, and the deformation of the wafer 1 is individually performed. Therefore, the entire deformation of the wafer 1 can be suppressed.

The second type of heat treatment mask includes a light shielding region that shields light and a plurality of light transmission regions partitioned by the light shielding region. Furthermore, it is preferable that the light shielding region is disposed at a position that shields at least a part of the light applied to the dicing line. The second type of heat treatment mask may be composed of one layer or may be composed of a plurality of layers. When the heat treatment mask includes a plurality of layers, the light shielding region may be formed in at least one of the layers of the heat treatment mask. Further, the light transmission region may be a through hole in which no substance exists, may be formed of a light transmissive material capable of transmitting light, and is formed by assembling the through hole and the light transmissive material. It may be a region. Further, when a light transmissive material is used for the light transmissive region, the light transmissive region may be formed of a single type of light transmissive material, or a plurality of types of light transmissive materials are formed together. May be. When a light transmissive material is used for the light transmissive region, it is preferable to change the type of the light transmissive material used according to the type of light generated by the light source.
When the surface of the wafer is irradiated with light using the second type of heat treatment mask, a region with a small amount of light irradiation, that is, a low irradiation region is formed in at least a part of the region along the dicing line of the wafer. The For this reason, the thermal expansion area of each high irradiation area is separated from the thermal expansion area of the adjacent high irradiation area, and the deformation of the wafer occurs within the range of each high irradiation area. It is done. Further, since the low irradiation region is formed in at least a part of the region along the dicing line of the wafer, even if the heat treatment in this region is insufficient, the characteristics of the semiconductor device to be manufactured are not affected. Therefore, the temperature at which the low irradiation region finally reaches can be kept low. As a result, it is possible to satisfactorily obtain a phenomenon in which the thermal expansion regions of the individual high irradiation regions are separated from the thermal expansion regions of the adjacent high irradiation regions, thereby suppressing the entire deformation of the wafer.
That is, according to the technique disclosed in this specification, it is possible to suppress the deformation of the wafer and heat-treat a wide range of the surface of the wafer without adversely affecting the characteristics of the semiconductor device to be manufactured.

In the second type of heat treatment mask disclosed in this specification, it is preferable that the light transmission region has a plurality of light transmission holes partitioned by partition walls.
In the heat treatment mask of this form, the partition is formed across the light transmission region. Therefore, the partition can improve the mechanical strength of the heat treatment mask.

In the second type of heat treatment mask disclosed in this specification, the partition wall is preferably formed of a light shielding material. This form of heat treatment mask can be evaluated as a combination of the first type heat treatment mask technique and the second type heat treatment mask technique.
According to the heat treatment mask of this embodiment, the deformation of the wafer can be remarkably suppressed and a wide range of the surface of the wafer can be heat treated without adversely affecting the characteristics of the semiconductor device to be manufactured.

In the heat treatment mask that combines the technology of the first type heat treatment mask and the technology of the second type heat treatment mask, the width of the partition wall is narrower than the width of the light shielding region located between the light transmission regions. preferable.
In the heat treatment mask of this embodiment, since the partition walls are formed narrow, the light that has passed through the light transmission holes can be diffracted and overlapped on the surface of the wafer below the partition walls. Although light overlaps the surface of the wafer below the partition wall, the amount of light irradiation below the partition wall is smaller than the irradiation amount below the light transmission holes. For this reason, the rate of temperature increase on the surface of the wafer below the partition walls is smaller than the rate of temperature increase on the surface of the wafer below the light transmission holes. Therefore, the surface temperature of the wafer below the light transmission hole first rises, and then the surface temperature of the wafer below the partition wall increases. As a result, the phenomenon that the thermal expansion of the surface of the wafer below the light transmission hole is transmitted to the thermal expansion of the surface of the wafer below the adjacent light transmission hole is suppressed, and the deformation of the wafer is further suppressed. On the other hand, the light passing through the light transmission hole can be diffracted and overlapped on the surface of the wafer below the partition wall, so that the temperature of the wafer surface below the light transmission hole does not rise to an excessive temperature. The temperature of the surface of the wafer below the partition wall can also be heated to a required temperature.

In the second type of heat treatment mask disclosed in the present specification, the pattern of the light shielding region and the pattern of the dicing line are preferably equal.
When the surface of the wafer is irradiated with light using the above-mentioned second type heat treatment mask, a low light irradiation region, that is, a low irradiation region is formed over the entire region along the wafer dicing line. Is done. For this reason, the high irradiation region is formed in a more fragmented state on the surface of the wafer. As a result, the thermal expansion area of each high irradiation area is separated from the thermal expansion area of the adjacent high irradiation area, and the deformation of the wafer occurs within the range of each high irradiation area. It is done.
Note that if the surface of the wafer is irradiated with light using the second type of heat treatment mask, each high-irradiation region substantially coincides with the range in which each semiconductor device exists. Therefore, heat treatment required for the semiconductor device to be manufactured can be performed.

In the first-type or second-type heat treatment mask disclosed in this specification, the light transmission hole may be a through-hole penetrating from the surface to the back surface of the film or plate formed of the light shielding material. Good.
The light generated by the light source can pass through a film or plate formed of a light shielding material through the through hole.

In the first-type or second-type heat treatment mask disclosed in this specification, it is preferable that the through hole is filled with a light-transmitting material.
When the through hole is filled with the light transmissive material, the light generated by the light source can pass through the film or plate formed of the light shielding material through the light transmissive material. Furthermore, since the light transmissive material is filled in the through holes, the mechanical rigidity of the heat treatment mask is high.

  The heat treatment mask disclosed in this specification can be used for various kinds of light. For example, the light may be a flashlight using xenon.

It is preferable that the first-type or second-type heat treatment mask disclosed in the present specification further includes a reinforcing layer formed on the light incident side. The reinforcing layer is preferably formed in the light shielding region when observed from the light irradiation direction. The reinforcing layer does not need to be formed in the entire range of the light shielding region, and may be formed in at least a part of the light shielding region.
If the reinforcing layer is formed along the light shielding region, even if the reinforcing layer shields the light, the light irradiation distribution on the surface of the wafer is not affected. On the other hand, the reinforcing layer can improve the mechanical rigidity of the heat treatment mask. That is, the presence of the reinforcing layer can improve the mechanical rigidity of the heat treatment mask without hindering the light irradiation distribution on the wafer surface. The technique of making the heat treatment mask into a laminated structure is extremely useful.

  In the first-type or second-type heat treatment mask disclosed in the present specification, diamond, silicon carbide, or silicon nitride is preferably used as the light shielding material. Furthermore, it is preferable to use single crystal silicon, sapphire, or quartz as the material of the reinforcing layer.

  The heat treatment apparatus using the heat treatment mask disclosed in this specification is extremely useful. A heat treatment apparatus disclosed in this specification includes a light source, an installation table on which a wafer is installed, and the heat treatment mask provided between the installation table and the light source.

  According to the technique disclosed in this specification, a method for manufacturing the first type or the second type of heat treatment mask can be provided. One method of manufacturing a heat treatment mask disclosed in this specification includes a step of forming a plurality of trenches from the surface of a film or plate of a light shielding material toward a deep portion, and filling the light transmissive material in the trenches. And a step of polishing the back surface of the light shielding material film or plate until the light transmissive material filled in the trench is exposed.

  In one manufacturing method of a heat treatment mask that combines the technology of the first type of heat treatment mask and the technology of the second type of heat treatment mask disclosed in the present specification, the surface of the light shielding material film or plate is used. When forming a plurality of trenches toward the deep part, it is preferable to form a wide shielding partition and a narrow fine partition between adjacent trenches. More preferably, when forming a plurality of trenches from the surface of the film or plate of light shielding material toward the deep part, the light formed in the region overlapping with the dicing line of the wafer when observed from the light irradiation direction It is preferable to form a plurality of trenches in a region other than the shielding region.

  One method of manufacturing a heat treatment mask that combines the technology of the first type of heat treatment mask and the technology of the second type of heat treatment mask disclosed in this specification is to form a narrow width after forming a plurality of trenches. It is preferable to further include a step of oxidizing the entire fine partition wall and leaving an unoxidized region in a part of the wide shielding partition wall. More preferably, after forming a plurality of trenches, the entire partition wall separating adjacent trenches in the light transmission region is oxidized, and an unoxidized region is left in a part of the partition wall forming the light shielding region. It is preferable that the method further includes a step.

  Another method of manufacturing a heat treatment mask that combines the technology of the first type of heat treatment mask and the technology of the second type of heat treatment mask disclosed in the present specification is to laminate a first layer and a second layer. Forming a plurality of first trenches that reach the second layer through the first layer of the laminated structure, and a second trench that reaches the first layer through the second layer and communicates with the first trench The process of forming is provided. In another manufacturing method of the heat treatment mask disclosed in this specification, at least the first layer is a light shielding material. Furthermore, a partition wall that separates adjacent second trenches is formed along the partition wall that separates adjacent first trenches.

  In another manufacturing method of a heat treatment mask that combines the technology of the first type of heat treatment mask and the technology of the second type of heat treatment mask disclosed in the present specification, between adjacent first trenches, It is preferable to form a wide shielding partition and a narrow fine partition. In this case, a partition wall that separates adjacent second trenches is formed along the shielding partition wall.

  In another manufacturing method of a heat treatment mask that combines the technology of the first type of heat treatment mask and the technology of the second type of heat treatment mask disclosed in this specification, the material of the first layer is diamond, carbonized. Silicon or silicon nitride is used, and single crystal silicon, sapphire, or quartz is preferably used as the material of the second layer.

  According to the technique disclosed in this specification, it is possible to suppress the deformation of the wafer and heat-treat a wide range of the surface of the wafer without affecting the characteristics of the semiconductor device to be manufactured.

Preferred features of the technology disclosed in this specification are listed.
(First Feature) The heat treatment mask is preferably used in a rapid thermal process (RTP) process.
(Second Feature) It is preferable to use a xenon flash lamp light source, a halogen lamp light source, or a hydrogen lamp light source as the light source.
(Third Feature) When a xenon flash lamp light source is used, it is preferable to use single crystal silicon, diamond, or silicon nitride as the light-impermeable material. When a xenon flash lamp light source is used, it is preferable to use silicon oxide or silsesquioxane as the light transmissive material.

(First embodiment)
Hereinafter, with reference to FIGS. 2-4, the form and usage method of the mask 10 for heat processing are demonstrated. The mask 10 is used when a rapid thermal process (RTP) is performed on a wafer 12 having a thickness of about 400 μm or less. The mask 10 is introduced to the surface portion of the processing range by heating the temperature of the processing range on the surface of the wafer 12 to at least about 1000 ° C. while maintaining the temperature of the back surface of the wafer 12 at about 700 ° C. or lower. Used when activating impurities. More preferably, the mask 10 is used when the temperature of the processing range of the front surface of the wafer 12 is heated to about 1300 ° C. or higher while the temperature of the back surface of the wafer 12 is maintained at about 500 ° C. or lower. FIG. 2 shows a plan view of the mask 10. FIG. 3 is a longitudinal sectional view of the mask 10 corresponding to the line III-III in FIG. In FIG. 3, in addition to the mask 10, a susceptor 14 (an example of an installation table) and a wafer 12 (silicon wafer) are also illustrated. FIG. 4 schematically shows an enlarged cross-sectional view of a main part between the mask 10 and the wafer 12.
3 and 4 show a state in which the mask 10 is used. The mask 10 selectively shields the light generated by the flash lamp light source 18 according to the position on the surface of the wafer 12. As shown in FIG. 3, the wafer 12 is mounted on a susceptor 14 provided in the processing chamber. The mask 10 is disposed between the flash lamp light source 18 and the wafer 12, selectively shields the light generated by the flash lamp light source 18 and irradiates the surface of the wafer 12 with the transmitted light. The dots shown in FIGS. 3 and 4 indicate the light generated by the flash lamp light source 18.

As shown in FIGS. 2 and 3, the mask 10 includes a mask layer 22 of single crystal silicon. The mask layer 22 includes a light shielding region 28 of single crystal silicon extending across the mask 10. The mask layer 22 further includes a plurality of light transmission regions 26 defined by the light shielding regions 28. A plurality of light transmission regions 26 are collected to form an irradiation region 24. The irradiation region 24 substantially coincides with a range where a plurality of semiconductor devices formed on the surface of the wafer 12 exist when viewed from a direction perpendicular to the surface of the wafer 12. The range of the semiconductor device here refers to a range that is later divided into chips. The light shielding area 28 crosses the irradiation area 24 in the vertical and horizontal directions.
In each of the light transmission regions 26, a through-hole penetrating from the front surface to the back surface of the mask layer 22 is formed. The through hole of the light transmission region 26 has a substantially rectangular planar shape when viewed in plan. The width W26 of the through hole of the light transmission region 26 is about 5 to 10 mm. The width W28 of the light shielding region 28 is about 0.1 to 0.2 mm.
The flash lamp light source 18 uses xenon (Xe), and the wavelength range of the generated light is about 400 nm. Single crystal silicon has an opaque characteristic with respect to the wavelength region of light. Therefore, the light generated by the flash lamp light source 18 is shielded by the light shielding region 28, passes through the mask layer 22 through the through hole of the light transmitting region 26, and is irradiated onto the surface of the wafer 12.

  In the mask 10, the range of the through hole of the light transmission region 26 and one range of the plurality of semiconductor devices formed on the surface of the wafer 12 are substantially coincident when observed from the light irradiation direction. Has been. A region between the semiconductor devices formed on the surface of the wafer 12 is a dicing line. That is, the light shielding region 28 of the mask 10 is disposed at a position that shields the light irradiated to the dicing line. The pattern of the light shielding area 28 of the mask 10 is equal to the pattern of the dicing line of the wafer 12.

  As shown in FIGS. 3 and 4, the light generated by the flash lamp light source 18 passes through the through hole of the light transmission region 26 of the mask 10 and is irradiated on the surface of the wafer 12. For this reason, in the range located below the light transmission region 26 on the surface of the wafer 12, the amount of light irradiation is relatively large. On the other hand, in the range located below the light shielding region 28 on the surface of the wafer 12, the amount of light irradiation is relatively small. As shown in FIG. 4, when the distance G <b> 10 between the mask layer 22 of the mask 10 and the wafer 12 is small, the light may not be substantially irradiated below the light shielding region 28. However, depending on the distance G10, the light passing through the through hole of the light transmission region 26 is diffracted and overlaps below the light shielding region 28 until reaching the surface of the wafer 12. Even if the light is diffracted and superimposed, a shielding pattern with a small amount of light irradiation is formed below the light shielding region 28. Note that by increasing the width W28 of the light shielding region 28, the light shielding region 28 forms a shielding pattern with a smaller amount of light irradiation on the surface of the wafer 12, and the amount of light irradiation further increases on the surface of the wafer 12. A small region can be formed. A method for determining the width W28 of the light shielding area 28 will be described later.

  For this reason, a distribution is formed in the amount of light irradiated onto the surface of the wafer 12, and a region having a large amount of light is divided into a plurality of regions by a region having a small amount of light. As a result, a similar distribution is formed in the rate of temperature rise on the surface of the wafer 12. That is, a high irradiation region 16 having a large temperature increase rate on the surface of the wafer 12 and a low irradiation region having a low temperature increase rate are formed. The high irradiation region 16 is not formed continuously over the entire surface of the wafer 12, but is formed in a dispersed state on the surface of the wafer 12. If the high irradiation regions 16 are formed in a state of being dispersed on the surface of the wafer 12, the thermal expansion regions of the individual high irradiation regions 16 are divided from the thermal expansion regions of the adjacent high irradiation regions 16, and the deformation of the wafer 12 is caused. Since it occurs within the range of each high irradiation region 16, the entire deformation of the wafer 12 is suppressed.

In the region where the amount of light irradiation is small, that is, in the low irradiation region, the temperature increase is suppressed as compared with the high irradiation region 16, so that the heat treatment becomes insufficient. However, since the region where the amount of light irradiation is small is formed along the dicing line of the wafer 12, even if the heat treatment is insufficient, the characteristics of the semiconductor device to be manufactured are not adversely affected. A sufficient heat treatment is performed on the semiconductor device.
When heat treatment is performed using the mask 10, deformation of the wafer 12 can be suppressed and a wide range of the surface of the wafer 12 can be heat treated without adversely affecting the characteristics of the semiconductor device to be manufactured.

(Method for setting the width W28 of the light shielding area 28)
In the mask 10, the light shielding region 28 is formed along the dicing line of the wafer 12. According to the technique disclosed in this specification, the light shielding region 28 may not be formed along the dicing line of the wafer 12 in order to suppress the entire deformation of the wafer 12. In the technique disclosed in this specification, a high irradiation region 16 having a high temperature rising speed and a low irradiation region having a low rising speed are formed on the surface of the wafer 12, and the high irradiation region 16 is divided by the low irradiation region. If so, it is proposed that the deformation of the entire wafer 12 is suppressed. That is, even if the temperature of the low irradiation region finally reaches the high temperature necessary for the heat treatment, if the high irradiation region 16 is divided by the low irradiation region, the thermal expansion region of each high irradiation region 16 Are separated from the thermal expansion region of the adjacent high irradiation region 16, and the deformation of the wafer 12 occurs within the range of each high irradiation region 16, so that the entire deformation of the wafer 12 is suppressed. Therefore, it is important that the mask 10 has a light shielding region 28 that divides the light transmission region 26. If the light shielding region 28 is formed, the distribution of the light irradiation amount on the surface of the wafer 12. The high irradiation region 16 and the low irradiation region can be formed on the surface of the wafer 12. Therefore, in order to obtain the effect of suppressing the entire deformation of the wafer 12, it is not an essential requirement that the light shielding region 28 is formed along the dicing line of the wafer 12.
For example, the light shielding area 28 may extend in the light transmission area 26. In other words, a light shielding region extending in the vertical and horizontal directions regardless of the dicing line may be formed in the irradiation region 24 of the mask layer 22. In this form of mask, the irradiation region 24 is evaluated as a light transmission region, the mask layer 22 around the irradiation region 24 is evaluated as a light shielding region, the light shielding region is evaluated as a light shielding partition, and the light shielding property is evaluated. When the region defined by the partition walls is evaluated as a light transmission hole, it can be considered as the first type heat treatment mask disclosed in this specification. Even with this type of mask, as described above, the high irradiation region 16 and the low irradiation region can be formed on the surface of the wafer 12, and deformation of the entire wafer 12 can be suppressed.
In the technology disclosed in this specification, it is desirable that the thermal expansion region of the high irradiation region 16 is divided from the thermal expansion region of the adjacent high irradiation region 16. For this purpose, it is desirable that the temperature increase rate in the low irradiation region is about 200 ° C./msec or less. Alternatively, it is desirable that the temperature increase rate of the low irradiation region is about 30% or less with respect to the increase rate of the high irradiation region 16. If a region satisfying this condition exists between the high irradiation regions 16, the thermal expansion regions of the individual high irradiation regions 16 are well separated from the thermal expansion regions of the adjacent high irradiation regions 16, and the wafer 12 is deformed. The phenomenon that it occurs within the range of each high-irradiation region 16 can be obtained favorably.
The low irradiation region can be defined by irradiation energy density instead of temperature irradiation. In this case, it is desirable that the irradiation energy density at the temperature of the low irradiation region is about 10 J / cm ² or less. Alternatively, the low irradiation region is desirably about 30% or less with respect to the irradiation energy density of the high irradiation region 16.
More preferably, the width W28 of the light shielding region 28 is set so that the temperature of the low irradiation region does not substantially increase. If a low irradiation area where the temperature does not substantially increase is formed on the surface of the wafer 12, the deformation of the wafer 12 is completely within the range of the individual high irradiation areas 16. Can be prevented. The width W28 of the light shielding region 28 for that purpose can be obtained using the following mathematical formula.
The relationship between the irradiation time by the flash lamp light source 18 and the heat transfer distance in the wafer 12 can be approximately expressed by the following equation.

  Here, ρ is the density of the wafer 12, Cp is the specific heat of the wafer 12, δ is the heat transfer distance, F0 is the Fourier number (in this embodiment, “1”), and k is the wafer. 12 heat transfer coefficient.

When it is assumed that the distance G10 between the mask layer 22 of the mask 10 and the wafer 12 is sufficiently small, and the area irradiated with light on the surface of the wafer 12 and the range of the through hole of the light transmission area 26 are completely coincident with each other, By setting the width W28 of the shielding region 28 to be twice or more the heat transfer distance δ, a region where the temperature does not substantially increase can be formed on the surface of the wafer 12 below the light shielding region 28. Actually, it is also necessary to consider that light passing through the through hole of the light transmission region 26 is diffracted, and the width W28 of the light shielding region 28 is sufficiently larger than twice the heat transfer distance δ. It is desirable. When a region where the temperature does not substantially increase is formed on the surface of the wafer 12, the deformation of the wafer 12 is completely within the range of the individual high-irradiation regions 16, thereby preventing the wafer 12 from being damaged more effectively. be able to.
Since the irradiation time of the xenon flash lamp light source 18 is about 1 to 3 msec, the heat transfer distance δ is about 20 to 50 μm. Therefore, the width W28 of the light shielding region 28 is preferably about 40 μm or more. More preferably, the width W28 of the light shielding region 28 is 100 μm or more.

(Modification of the first embodiment)
FIG. 5 schematically shows a cross-sectional view of a mask 100 according to a modification of the first embodiment. In addition, the same code | symbol is attached | subjected about the component same as the mask 10 of 1st Example, and the description may be abbreviate | omitted.
As shown in FIG. 5, in the mask 100, the through hole 26 a in the light transmission region is filled with a light transmissive material through which light can pass. Silicon oxide is used as the light transmissive material. Silsesquioxane or the like may be used instead of silicon oxide.
If the through hole 26a is formed of a light transmissive material, the light generated by the flash lamp light source 18 can pass through the mask layer 22 through the light transmissive material.
When the through hole 26a is filled with a light transmissive material, the mechanical rigidity of the mask layer 22 is improved as compared with the case where no substance is present in the through hole.

With reference to FIG. 6, a method of manufacturing a mask 100 of a modification will be described.
First, as shown in FIG. 6A, a silicon single crystal mask layer 22 (silicon substrate) is prepared, and a photoresist 32 is patterned on the surface of the mask layer 22 using a photoresist technique. The range in which the photoresist 32 is removed corresponds to the range in which the through hole 26a of the mask 100 is formed.
Next, as shown in FIG. 6B, a plurality of trenches 26b are formed from the surface of the mask layer 22 toward the deep portion using a reactive ion etching technique. A light shielding region 28 is formed between the adjacent trenches 26b.
Next, as shown in FIG. 6C, a filling material such as silsesquioxane, a liquid material of silicon oxide or SOD is filled in the trench 26b by using an ink jet or screen printing method, and the through hole 26a. Form. At this time, you may perform the baking for volatilizing the solvent used for the filler. Fillers such as silsesquioxane, silicon oxide liquid material, or SOD can pass light generated by the Xe flash lamp light source 18.
Next, as shown in FIG. 6D, polishing is performed from the front surface side and the back surface side of the mask layer 22 to the position of the broken line. Through these steps, the mask 100 shown in FIG. 5 can be obtained.

(Second embodiment)
With reference to FIGS. 7-9, the form and usage method of the mask 200 which combined the technique of the 1st type heat processing mask and the technique of the 2nd type heat processing mask are demonstrated. FIG. 7 shows a plan view of the mask 200. FIG. 8 is a longitudinal sectional view of the mask 200 corresponding to the line VIII-VIII in FIG. FIG. 8 schematically shows an enlarged cross-sectional view of a main part between the mask 200 and the wafer 12. 8 and FIG. 9, the width of the light shielding region 28 and the fine partition walls 29, the number of the fine partition walls 29, and the like do not coincide with the plan view of FIG. This is because of simplification. The same components as those of the mask 10 of the first embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

  As shown in FIGS. 7 to 9, in the mask 200, a plurality of light transmission holes 226 are dispersedly formed in the light transmission region 26. The plurality of light transmission holes 226 are partitioned by a partition wall 29 between adjacent light transmission holes 226. The partition wall 29 is made of single crystal silicon. The width W29 of the partition wall 29 between the adjacent light transmission holes 226 is narrower than the width W28 of the light shielding region 28. A partition wall 29 between adjacent light transmission holes 226 extends in the light transmission region 26 in the vertical and horizontal directions. The light transmission hole 226 is a through hole penetrating from the front surface to the back surface of the mask layer 22. The width W28 of the light shielding region 28 is about 0.1 to 0.2 mm. The width W29 of the partition wall 29 between the adjacent light transmission holes 226 is about 10 μm.

  As shown in FIG. 9, light generated by a flash lamp light source (not shown) passes through the light transmission hole 226 of the mask 200 and is irradiated on the surface of the wafer 12. On the other hand, the light shielding area 28 shields light. Furthermore, the partition walls 29 between the adjacent light transmission holes 226 also shield light. Since the partition walls 29 are formed to be narrow, the light passing through the light transmission holes 226 can be diffracted and overlapped on the surface of the wafer 12 below the partition walls 29. Although the light overlaps on the surface of the wafer 12 below the partition wall 29, the light irradiation amount below the partition wall 29 is smaller than the irradiation amount below the light transmission hole 226. For this reason, the rising speed of the surface temperature of the wafer 12 below the partition wall 29 is smaller than the increasing speed of the surface temperature of the wafer 12 below the light transmission hole 226. Therefore, the surface temperature of the wafer 12 below the light transmission hole 226 first rises, and then the surface temperature of the wafer 12 below the partition wall 29 rises. As a result, the phenomenon that the thermal expansion region of the surface of the wafer 12 below the light transmission hole 226 is transmitted to the surface of the wafer 12 below the adjacent light transmission hole 226 is suppressed, and deformation of the wafer 12 is further suppressed.

  Furthermore, in the mask 200, the partition wall 29 between the adjacent light transmission holes 226 is provided, so that the mechanical rigidity of the mask layer 22 can be improved. In other words, when the narrow partition wall 29 is used, the distribution of light irradiation can be formed on the surface of the wafer, and the mechanical rigidity of the mask layer 22 can be improved.

The wide light shielding region 28 forms a region with a small amount of light irradiation on the surface of the wafer 12. Similarly, the narrow partition wall 29 forms a region with a small amount of light irradiation on the surface of the wafer 12. However, since the width of the partition wall 29 is formed narrower than the width of the light shielding region 28, the decrease in the light irradiation amount by the partition wall 29 is smaller than the decrease in the light irradiation amount by the light shielding region 28. Accordingly, the temperature of the surface of the wafer 12 below the partition wall 29 is higher than the temperature of the surface of the wafer 12 below the light shielding region 28. Further, since the width of the partition wall 29 is narrow, the temperature of the surface of the wafer 12 below the partition wall 29 also rises from the surroundings due to heat conduction. Therefore, the temperature of the surface of the wafer 12 below the partition wall 29 is heated to a necessary temperature. As a result, sufficient heat treatment can be performed on each semiconductor device formed on the wafer 12.
It is desirable that the width of the partition wall 29 is set using the above formula 1. When it is assumed that the distance G200 between the mask layer 22 of the mask 200 and the wafer 12 is sufficiently small, and the region irradiated with light on the surface of the wafer 12 and the range of the through hole of the light transmission hole 226 completely match. By setting the width W29 of 29 to be equal to or less than twice the heat transfer distance δ, the temperature of the surface of the wafer 12 below the partition wall 29 can be raised. Actually, considering that the light passing through the through hole of the light transmitting hole 226 is diffracted, the temperature of the surface of the wafer 12 below the partition wall 29 can be raised to a temperature necessary for the heat treatment.
It should be noted that the surface of the wafer 12 below the wide light shielding region 28 has a small amount of light irradiation and a small amount of heat conduction from the surroundings, so that a region with insufficient heat treatment is formed. However, since the surface of the wafer 12 below the light shielding region 28 coincides with the dicing line, even if the heat treatment is insufficient, the characteristics of the semiconductor device to be manufactured are not adversely affected.
When heat treatment is performed using the mask 200, deformation of the wafer 12 can be suppressed and a wide range of the surface of the wafer 12 can be heat treated without adversely affecting the characteristics of the semiconductor device to be manufactured.

  Note that the mask 200 may be formed of only the narrow partition wall 29 without forming the wide light shielding region 28. This form of mask can be thought of as the first type of heat treatment mask disclosed herein. Even with this form of mask, a low-irradiation region with a small amount of light irradiation can be formed on the surface of the wafer, and deformation of the entire wafer can be suppressed. In the mask of this form, the dicing line on the surface of the wafer is also heat-treated, but there is no problem even if the dicing line is heat-treated.

(Modification 1 of the second embodiment)
FIG. 10 schematically shows a cross-sectional view of a mask 300 according to a modification of the second embodiment. The same components as those of the mask 200 of the second embodiment are denoted by the same reference numerals, and the description thereof may be omitted.
As shown in FIG. 10, in the mask 300, the light transmission hole 226a is formed of a light transmissive material that can transmit light. Silicon oxide is used as the light transmissive material. Silsesquioxane or the like may be used instead of silicon oxide.
When the light transmitting hole 226a is formed of a light transmitting material, light generated by a flash lamp light source (not shown) can pass through the mask layer 22 through the light transmitting material.
When the light transmitting hole 226a is filled with a light transmitting material, the mechanical rigidity of the mask layer 22 is improved as compared with the case where no substance is present in the light transmitting hole.

(Modification 2 of the second embodiment)
FIG. 11 schematically shows a cross-sectional view of a mask 400 according to a modification of the second embodiment. The same components as those of the mask 200 of the second embodiment are denoted by the same reference numerals, and the description thereof may be omitted.
As shown in FIG. 11, in the mask 400, the light transmission holes 226a and the narrow partition walls 29a are formed of a light transmissive material capable of transmitting light. Silicon oxide is used as the light transmissive material. Silsesquioxane or the like may be used instead of silicon oxide.
In this case, it can be considered that a structure of a combination of light transmitting materials of different materials (light transmitting hole 226a and narrow partition wall 29a) is formed in the light transmitting region.
When the light transmitting hole 226a and the narrow partition wall 29a are formed of a light transmitting material, light generated by a flash lamp light source (not shown) can pass through the mask layer 22 through the light transmitting material. .

With reference to FIG. 12, a method of manufacturing a mask 400 of a modification will be described.
First, as shown in FIG. 12A, a silicon single crystal mask layer 22 (silicon substrate) is prepared, and a photoresist 34 is patterned on the surface of the mask layer 22 by using a photoresist technique. The range where the photoresist 34 is removed corresponds to the range where the light transmission holes 226a of the mask 400 are formed.
Next, as shown in FIG. 12B, a plurality of trenches 226b are formed from the surface of the mask layer 22 toward the deep portion using a reactive ion etching technique. Between the adjacent trenches 226b, a wide shielding partition 28b and a narrow fine partition 29b are formed.
Next, as shown in FIG. 12C, the mask layer 22 is thermally oxidized. The thermal oxidation at this time is performed under the condition that an unoxidized portion remains in the wide shielding partition wall 28b and the entire narrow fine partition wall 29b is oxidized. Thereby, a part of the silicon single crystal remains inside the wide shielding partition wall 28b, and the single crystal silicon of the narrow fine partition wall 29b is completely transformed into silicon oxide. As a result, the wide shielding partition wall 28b becomes the light shielding region 28, and the narrow fine partition wall 29b becomes the partition wall 29a capable of transmitting light. A thin layer of silicon oxide is also formed on the surface of the light shielding region 28. This thin layer of silicon oxide is not shown in the cross-sectional view of FIG. 11, but is omitted in FIG. 11 because it is almost negligible. In consideration of the formation of a thin layer of silicon oxide, the width of the wide shielding partition 28b may be set so that the required width of the light shielding region 28 is obtained.
Next, as shown in FIG. 12D, a trench 226b is filled with a filling material such as silsesquioxane, a liquid material of silicon oxide or SOD using an ink jet or screen printing method, and light transmission holes are formed. 226a is formed. At this time, you may perform the baking for volatilizing the solvent used for the filler. Silsesquioxane, a liquid material of silicon oxide, or a filler such as SOD is a material that transmits light generated by a flash lamp light source of Xe.
Next, as shown in FIG. 12E, polishing is performed from the front surface side and the back surface side of the mask layer 22 to the position of the broken line. Through these steps, the mask 400 shown in FIG. 11 can be obtained.

The manufacturing method of the mask 400 has the following features.
(1) In the manufacturing method of the mask 400, a plurality of trenches 226b are formed in a range corresponding to the light transmission region, and the trench 226b is filled with a filler such as silsesquioxane, a liquid material of silicon oxide, or SOD. . In general, a liquid material such as silsesquioxane or silicon oxide or a filler such as SOD tends to shrink in the case of a liquid material, and high stress tends to occur in the case of thermal oxidation. For this reason, for example, if one groove is formed in a range corresponding to the light transmission region and the filler is filled in the groove, the mask is damaged when the filler contracts or is thermally oxidized. Things can happen. However, in the manufacturing method of the mask 400, a plurality of trenches 226b are formed in a range corresponding to the light transmission region, and the above-described filler is filled in the trenches 226b. Therefore, since the volume of each filler is reduced, it is possible to avoid a situation where the mask is damaged.
(2) In the manufacturing method of the mask 400, a plurality of trenches 226b are formed in a range corresponding to the light transmission region. For example, when one groove is formed in a range corresponding to the light transmission region, there is a problem that the depth of the groove varies depending on the position in the groove. This phenomenon is mainly caused by a decrease in the etching rate at the boundary of the etching pattern due to the microloading effect when reactive ion etching is performed. However, in the manufacturing method of the mask 400, the plurality of trenches 226b are formed in a range corresponding to the light transmission region. As a result, the variation in depth when reactive ion etching is performed is improved.
(3) In the manufacturing method of the mask 400, it is preferable to use a screen printing method when filling the filler. If the screen printing method is used, the filling of the filler can be divided into a plurality of times, and the drying process can be divided into a plurality of times. That is, if the screen printing method is used, the filling and drying cycles of the filler can be repeated, and damage to the mask and filler can be avoided.

(Third embodiment)
FIG. 13 schematically shows a longitudinal sectional view of the mask 500. As shown in FIG. 13, a mask 500 includes a mask layer 22 and a reinforcing layer 52 provided on the light incident side. The mask layer 22 has substantially the same form as the mask layer 22 of the mask 200 shown in FIG.
The reinforcing layer 52 includes a plurality of second transmission holes 56 penetrating from the front surface to the back surface. The second transmission hole 56 faces the light transmission hole 226 of the mask layer 22. The second transmission hole 56 is a through hole penetrating from the front surface to the back surface of the reinforcing layer 52. The portion 54 between the adjacent second transmission holes 56 is formed in the wide light shielding region 28 of the mask layer 22 when observed from the light irradiation direction.
When the portion 54 between the adjacent second transmission holes 56 is formed along the wide light shielding region 28 of the mask layer 22, the portion 54 between the adjacent second transmission holes 56 shields light. However, the light irradiation distribution on the surface of the wafer 12 formed by the mask layer 22 is not affected. On the other hand, the portion 54 between the adjacent second transmission holes 56 can improve the mechanical rigidity of the mask 500. That is, the presence of the reinforcing layer 52 can improve the mechanical rigidity of the mask 500 without hindering the distribution of the light irradiation amount on the surface of the wafer 12 formed by the mask layer 22.

Since the reinforcing layer 52 improves the mechanical rigidity of the mask 500, the thickness of the mask layer 22 can be reduced. In general, the mask 500 is manufactured by using a reactive ion etching technique, and the aspect ratio of the reactive ion etching technique is about 20 or so. Therefore, when the light transmission hole 226 having a narrow width is formed in the mask layer 22, the thickness of the mask layer 22 must be reduced. For this reason, the mechanical rigidity of the mask layer 22 is lowered.
In the mask 500, the mask layer 22 can be reinforced by the reinforcing layer 52, and the mechanical rigidity of the mask 500 can be improved. As a result, the thickness of the mask layer 22 can be reduced, and a narrow light transmission hole 226 can be formed in the mask layer 22.

  In the mask 500, the material of the mask layer 22 and the reinforcing layer 52 is such that the thermal conductivity of the mask layer 22 is larger than the thermal conductivity of the reinforcing layer 52 and the thermal capacity of the mask layer 22 is smaller than the thermal capacity of the reinforcing layer 52. When is selected, extremely useful results can be obtained. Specifically, diamond or silicon carbide is selected as the material of the mask layer 22, and single crystal silicon is selected as the material of the reinforcing layer 52.

When light is irradiated toward the surface of the wafer 12 using the mask 500, the light is also applied to the mask 500, and the temperature of the mask 500 rises. In the mask 500, a material having a high thermal conductivity is used for the mask layer 22. Therefore, heat generated in the mask 500 can be efficiently conducted to the peripheral side of the mask 500 through the mask layer 22. However, if a material having a high thermal conductivity is used for the reinforcing layer 52, the heat capacity of the mask 500 is reduced, and the mask 500 reaches a high temperature before the heat is conducted to the peripheral side, and the mask 500 is damaged. Will be.
In the mask 500, the heat capacity of the reinforcing layer 52 is larger than that of the mask layer 22. For this reason, it can suppress that the temperature of the mask 500 rises rapidly. If both the mask layer 22 and the reinforcing layer 52 are made of a material having a large heat capacity, the heat conduction to the peripheral side of the mask 500 is lowered, and the cooling effect of the mask 500 is lowered.
In the mask 500, the mask layer 22 and the reinforcing layer 52 are made of different materials, thereby suppressing a rapid temperature rise of the mask 500 and efficiently conducting heat generated in the mask 500 toward the peripheral side. Can do. According to the mask 500, the maximum temperature that the mask 500 reaches during use is significantly reduced. The deformation of the mask 500 is remarkably suppressed.

With reference to FIG. 14, the manufacturing method of the mask 500 is demonstrated.
First, as shown in FIG. 14A, a silicon single crystal reinforcing layer 52 is prepared, and a CVD diamond mask layer 22 is grown on the surface of the reinforcing layer 52 by using a CVD (Chemical Vapor Deposition) method. To do. Next, a photoresist 36 is patterned on the surface of the mask layer 22 using a photoresist technique. The range where the photoresist 36 is removed corresponds to the range where the light transmission holes 226 are formed.
Next, as shown in FIG. 14B, a plurality of light transmission holes 226 (which are the first trenches) that reach the reinforcing layer 52 through the mask layer 22 are formed by using the reactive ion etching technique. To do. Between the adjacent light transmission holes 226, a wide light shielding region 28 (which is a shielding partition) and a narrow partition 29 (fine partition) are formed.
Next, as shown in FIG. 14C, a photoresist 38 is patterned on the back surface of the reinforcing layer 52 using a photoresist technique. The range where the photoresist 38 is removed corresponds to the range where the second light transmission hole 56 is formed.
Next, as shown in FIG. 14D, a plurality of second light transmission holes 56 (which are second trenches) that penetrate the reinforcing layer 52 and reach the mask layer 22 and communicate with the light transmission holes 226 are formed. To do. At this time, a portion 54 between the adjacent second light transmission holes 56 is formed along the light shielding region 28 of the mask layer 22. Through these steps, a mask 500 shown in FIG. 13 can be obtained.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

(A) A case where a high temperature region is formed continuously on the entire surface of the wafer is shown. (B) The case where the high temperature region is formed in a dispersed state on the surface of the wafer is shown. The top view of the mask of 1st Example is typically shown. FIG. 3 is a longitudinal sectional view corresponding to line III-III in FIG. 2. The principal part expanded sectional view between a mask and a wafer is typically shown. The longitudinal cross-sectional view of the mask of the modification of 1st Example is shown. (A) The 1st manufacturing process of the mask of the modification of 1st Example is shown. (B) The 2nd manufacturing process of the mask of the modification of 1st Example is shown. (C) The 3rd manufacturing process of the mask of the modification of 1st Example is shown. (D) The 4th manufacturing process of the mask of the modification of 1st Example is shown. The top view of the mask of 2nd Example is shown typically. The longitudinal cross-sectional view corresponding to the VIII-VIII line of FIG. 7 is shown. The principal part expanded sectional view between a mask and a wafer is typically shown. The longitudinal cross-sectional view of the mask of the modification 1 of 2nd Example is shown. The longitudinal cross-sectional view of the mask of the modification 2 of 2nd Example is shown. (A) The 1st manufacturing process of the mask of the modification 2 of 2nd Example is shown. (B) The 2nd manufacturing process of the mask of the modification 2 of 2nd Example is shown. (C) The 3rd manufacturing process of the mask of the modification 2 of 2nd Example is shown. (D) The 4th manufacturing process of the mask of the modification 2 of 2nd Example is shown. (E) The 5th manufacturing process of the mask of the modification 2 of 2nd Example is shown. The longitudinal cross-sectional view of the mask of 3rd Example is shown. (A) The 1st manufacturing process of the mask of 3rd Example is shown. (B) The 2nd manufacturing process of the mask of 3rd Example is shown. (C) The 3rd manufacturing process of the mask of 3rd Example is shown. (D) The 4th manufacturing process of the mask of 3rd Example is shown.

Explanation of symbols

10, 100, 200, 300, 400, 500: Mask 12: Wafer 14: Susceptor 18: Flash lamp light source 22: Mask layer 24: Irradiation region 26: Light transmission region 226, 226a: Light transmission hole 28: Light shielding region 29 : Bulkhead

Claims (6)

It is a method for manufacturing a heat treatment mask that shields light irradiated on the surface of a wafer,
Forming a plurality of trenches from the surface of the light shielding material film or plate toward the deep portion;
Filling the trench with a light transmissive material;
Polishing the back surface of the light shielding material film or plate until the light transmissive material filled in the trench is exposed;
A method for manufacturing a mask for heat treatment, comprising: When forming a plurality of trenches from the surface of the light shielding material film or plate toward the deep part,
2. The heat-treating mask manufacturing method according to claim 1 , wherein a wide shielding partition and a narrow fine partition are formed between adjacent trenches. 3. The method according to claim 2 , further comprising the step of oxidizing the entire narrow fine partition wall after forming the plurality of trenches and leaving an unoxidized region in a part of the wide shielding partition wall. A method for manufacturing a mask for heat treatment. It is a method for manufacturing a heat treatment mask that shields light irradiated on the surface of a wafer,
Forming a plurality of first trenches that reach the second layer through the first layer of the stacked structure in which the first layer and the second layer are stacked;
Forming a second trench penetrating the second layer and reaching the first layer and communicating with the first trench;
At least the first layer is a light shielding material,
A method of manufacturing a mask for heat treatment, wherein a partition wall separating adjacent second trenches is formed along the partition wall separating adjacent first trenches. A wide shielding partition and a narrow fine partition are formed between adjacent first trenches,
5. The heat treatment mask manufacturing method according to claim 4 , wherein a partition wall separating adjacent second trenches is formed along the shielding partition wall. For the first layer, diamond, silicon carbide, or silicon nitride is used,
The method for manufacturing a mask for heat treatment according to claim 4 or 5 , wherein the second layer is made of single crystal silicon, sapphire, or quartz.

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