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JP4967652B2 - Current-voltage amplifier circuit and semiconductor test apparatus - Google Patents
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JP4967652B2 - Current-voltage amplifier circuit and semiconductor test apparatus - Google Patents

Current-voltage amplifier circuit and semiconductor test apparatus Download PDF

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JP4967652B2
JP4967652B2 JP2006353886A JP2006353886A JP4967652B2 JP 4967652 B2 JP4967652 B2 JP 4967652B2 JP 2006353886 A JP2006353886 A JP 2006353886A JP 2006353886 A JP2006353886 A JP 2006353886A JP 4967652 B2 JP4967652 B2 JP 4967652B2
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太亮 阿部
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Description

本発明は、電流および電圧を増幅あるいは減衰する電流電圧増幅回路に関し、特にLSIテスタや電流電圧測定器に用いて好適な電流電圧増幅回路、およびこれを用いた半導体試験装置に関するものである。   The present invention relates to a current-voltage amplifier circuit that amplifies or attenuates current and voltage, and more particularly to a current-voltage amplifier circuit suitable for use in an LSI tester or a current-voltage measuring instrument, and a semiconductor test apparatus using the same.

従来から、出力電流の制限値および出力電圧を制御できる電流出力回路は知られていた。例えば特許文献1(特開2002−286808)には、5個の増幅器(オペアンプ)を用いて、電流出力回路は出力電圧と出力電流の制限値の両方を独立に制御することが可能な回路が提案されている。しかし、このような電流出力回路は回路構成が複雑であり、回路が大型化するという問題がある。また半導体試験装置の構造上、被試験デバイス(Device Under Test:以下「DUT」という。)の近傍に回路を配置することが難しい。このため、大電流域では経路抵抗やインダクタンスによる電流応答が不十分となり、微小電流域では浮遊容量によるセトリング時間の遅れとなり、高速、高精度測定を阻害している。   Conventionally, a current output circuit capable of controlling an output current limit value and an output voltage has been known. For example, Patent Document 1 (Japanese Patent Laid-Open No. 2002-286808) discloses a circuit that uses five amplifiers (op-amps) and the current output circuit can independently control both the output voltage and the output current limit value. Proposed. However, such a current output circuit has a problem in that the circuit configuration is complicated and the circuit becomes large. In addition, due to the structure of the semiconductor test apparatus, it is difficult to place a circuit in the vicinity of a device under test (hereinafter referred to as “DUT”). For this reason, the current response due to the path resistance and inductance becomes insufficient in the large current region, and the settling time is delayed due to the stray capacitance in the very small current region, which hinders high-speed and high-accuracy measurement.

そこで本件出願人は、特許文献2(特開2005−192141)において、簡単な構成で出力電流の範囲を可変することができる電流増幅回路を提供している。   In view of this, the present applicant has provided a current amplifying circuit capable of varying the range of the output current with a simple configuration in Japanese Patent Laid-Open No. 2005-192141.

図3は、特許文献2にかかる電流増幅回路101の基本構成を説明する図である。Q1は反転入力端子と非反転入力端子の2つの入力端子および1つの出力端子を有する増幅器である。INは入力端子であり、増幅器Q1の非反転入力端子に接続される。抵抗R1は、一端は増幅器Q1の非反転入力端子に、他端は増幅器Q1の出力端子に接続される。抵抗R2は、一端は増幅器Q1の出力端子に、他端は増幅器Q1の反転入力端子に接続される。OUTは出力端子であり、増幅器Q1の反転入力端子と抵抗R2の間に接続される。   FIG. 3 is a diagram for explaining the basic configuration of the current amplifier circuit 101 according to Patent Document 2. As shown in FIG. Q1 is an amplifier having two input terminals of an inverting input terminal and a non-inverting input terminal and one output terminal. IN is an input terminal and is connected to the non-inverting input terminal of the amplifier Q1. The resistor R1 has one end connected to the non-inverting input terminal of the amplifier Q1 and the other end connected to the output terminal of the amplifier Q1. The resistor R2 has one end connected to the output terminal of the amplifier Q1, and the other end connected to the inverting input terminal of the amplifier Q1. OUT is an output terminal connected between the inverting input terminal of the amplifier Q1 and the resistor R2.

上記構成において、入力端子INの電圧をVi、電流をIi、出力端子OUTの電圧をVo、電流をIoとする。増幅器Q1の非反転入力端子および反転入力端子には電流が流れず、かつこれら2つの入力端子間には電位差が発生しないことから、下記(1)、(2)式が成立する。
Vo=Vi ・・・・・・・・・・・・・・・・・ (1)
Vo=R2×Io+R1×Ii+Vi ・・・・・ (2)
すると、次式(3)を導出することができる。
Io=−(R1/R2)×Ii ・・・・・・・・ (3)
すなわち、増幅器1つと抵抗2本のみで、電圧が変化せず、かつ電流のみを増幅する電流増幅回路を構成することができる。なお、入力電流と出力電流の関係は抵抗R1,R2の抵抗比を変えることによって任意の値に設定することができる。R2をR1より大きくすると、電流減衰器として使用することができる。
In the above configuration, the voltage at the input terminal IN is Vi, the current is Ii, the voltage at the output terminal OUT is Vo, and the current is Io. Since no current flows through the non-inverting input terminal and the inverting input terminal of the amplifier Q1, and no potential difference is generated between these two input terminals, the following equations (1) and (2) are established.
Vo = Vi (1)
Vo = R2 × Io + R1 × Ii + Vi (2)
Then, the following expression (3) can be derived.
Io = − (R1 / R2) × Ii (3)
That is, it is possible to configure a current amplifying circuit that amplifies only the current without changing the voltage by using only one amplifier and two resistors. The relationship between the input current and the output current can be set to an arbitrary value by changing the resistance ratio of the resistors R1 and R2. When R2 is larger than R1, it can be used as a current attenuator.

そして上記回路を半導体試験装置の電圧印加電流測定出力に接続することにより、電流レンジ以上の出力電流を測定することが可能となる。すなわち半導体試験装置において所定の電流値が測定されたとき、測定された電流のR1/R2倍の電流がDUTに流れたということがわかる。   Then, by connecting the above circuit to the voltage application current measurement output of the semiconductor test apparatus, it becomes possible to measure the output current above the current range. That is, it can be seen that when a predetermined current value is measured in the semiconductor test apparatus, a current R1 / R2 times the measured current flows through the DUT.

図4は特許文献2に記載された構成であって、上記の電流増幅回路を2つ直列に接続して、電流制限機能を付加した構成を示す図である。図3に示した電流増幅回路101は、入力信号Iiが電流制限を受けると帰還がかかり、出力端子OUTから更に電流を流そうとして出力電圧が上昇する。この実施例では図3の電流増幅回路101の前段にもう一つ同じ構成の電流増幅回路102を接続することにより、電流量を補償して出力電圧の上昇を回避し、通常の電圧・電流制限回路として動作させるようにしたものである。
特開2002−286808号公報 特開2005−192141号公報
FIG. 4 shows a configuration described in Patent Document 2, in which two current amplifying circuits are connected in series and a current limiting function is added. In the current amplifier circuit 101 shown in FIG. 3, feedback is applied when the input signal Ii is subjected to current limitation, and the output voltage rises as a further current flows from the output terminal OUT. In this embodiment, another current amplifying circuit 102 having the same configuration is connected to the previous stage of the current amplifying circuit 101 in FIG. 3 to compensate for the amount of current to avoid an increase in output voltage, and to achieve normal voltage / current limiting. It is made to operate as a circuit.
Japanese Patent Laid-Open No. 2002-286808 JP 2005-192141 A

しかし、上記特許文献2に記載された構成では、確かに測定レンジ以上の出力電流を測定することは可能であるが、出力レンジ以上の電圧を印加することはできなかった。また、抵抗R2と増幅器Q1の出力端子との接続位置であるセンシング点とDUTとの間にリレーS1が配置されていたため、正確な電圧を出力することが難しかった。   However, in the configuration described in Patent Document 2, it is possible to measure an output current exceeding the measurement range, but it is impossible to apply a voltage exceeding the output range. Further, since the relay S1 is disposed between the sensing point, which is the connection position between the resistor R2 and the output terminal of the amplifier Q1, and the DUT, it is difficult to output an accurate voltage.

そこで本発明は、半導体試験装置のレンジ以上に電圧を増幅して印加し、レンジ以上の電流や微小な電流を測定することを可能にする電流電圧増幅回路、およびこれを用いた半導体試験装置を提供することを目的としている。   Therefore, the present invention provides a current-voltage amplifier circuit that makes it possible to amplify and apply a voltage over a range of a semiconductor test apparatus and measure a current exceeding the range or a minute current, and a semiconductor test apparatus using the same. It is intended to provide.

上記課題を解決するために、本発明にかかる電流電圧増幅回路の代表的な構成は、
非反転入力端子に入力信号が入力され、非反転入力端子と出力端子との間に電流オフセット相殺回路と第1抵抗が直列接続され、出力端子と反転入力端子との間に第2抵抗と電圧比設定回路が直列接続され、第2抵抗と電圧比設定回路との間に被試験デバイスに信号を伝達する出力信号線が接続される第1増幅器を備えた電流増幅回路を有し、
前記電圧比設定回路は、前記出力信号線に非反転入力端子が接続され、反転入力端子と出力端子とが短絡され、出力端子は第3抵抗と第4抵抗の直列回路を介して接地され、第3抵抗と第4抵抗の間に前記第1増幅器の反転入力端子が接続される第2増幅器で構成され、
前記電流オフセット相殺回路は、出力端子が前記第1抵抗を介して前記第1増幅器の非反転入力端子に接続され、反転入力端子と出力端子とが短絡され、非反転入力端子が第5抵抗を介して接地されるとともに第6抵抗を介して前記前記第1増幅器の出力端子に接続される第3増幅器で構成されたことを特徴とする。
In order to solve the above problems, a typical configuration of a current-voltage amplifier circuit according to the present invention
An input signal is input to the non-inverting input terminal, a current offset cancellation circuit and a first resistor are connected in series between the non-inverting input terminal and the output terminal, and a second resistor and voltage are connected between the output terminal and the inverting input terminal. A current amplifying circuit including a first amplifier, in which a ratio setting circuit is connected in series, and an output signal line for transmitting a signal to the device under test is connected between the second resistor and the voltage ratio setting circuit;
In the voltage ratio setting circuit, a non-inverting input terminal is connected to the output signal line, an inverting input terminal and an output terminal are short-circuited, and an output terminal is grounded via a series circuit of a third resistor and a fourth resistor, A second amplifier in which an inverting input terminal of the first amplifier is connected between a third resistor and a fourth resistor;
The current offset cancellation circuit has an output terminal connected to the non-inverting input terminal of the first amplifier via the first resistor, the inverting input terminal and the output terminal are short-circuited, and the non-inverting input terminal has a fifth resistor. And a third amplifier connected to the output terminal of the first amplifier via a sixth resistor .

上記構成によれば、簡単な構成で出力電流の範囲を拡縮しうると共に、印加する電圧を高精度に増幅することができる。従って半導体試験装置と被試験デバイスとの間に本回路を配置することにより、半導体試験装置のレンジ以上の電圧を増幅して印加し、レンジ以上の電流や微小な電流を測定することができる。   According to the above configuration, the range of the output current can be expanded and reduced with a simple configuration, and the applied voltage can be amplified with high accuracy. Therefore, by arranging this circuit between the semiconductor test apparatus and the device under test, it is possible to amplify and apply a voltage exceeding the range of the semiconductor test apparatus and measure a current exceeding the range or a minute current.

上記電圧比設定回路によって電圧を増幅した場合、電流が流れていない場合であっても電圧が増幅されるため、オフセット電流が流れてしまう。しかし上記電流オフセット相殺回路によれば、オフセット電流を削減し、より正確な測定値を得ることができる。   When the voltage is amplified by the voltage ratio setting circuit, the voltage is amplified even when no current is flowing, so that an offset current flows. However, according to the current offset cancellation circuit, the offset current can be reduced and a more accurate measurement value can be obtained.

また第3抵抗および第4抵抗の比と、第5抵抗および第6抵抗の比が等しいことが好ましい。これによりオフセット電流をほぼ解消することができ、測定値をオフセットするまでもなく正確な値を得ることができる。   Moreover, it is preferable that the ratio between the third resistor and the fourth resistor is equal to the ratio between the fifth resistor and the sixth resistor. As a result, the offset current can be almost eliminated, and an accurate value can be obtained without offsetting the measured value.

出力信号線において、該出力信号線と第2増幅器の非反転入力端子とが接続するセンシング点と、第2抵抗との間に、スイッチ回路を設けたことを特徴とする。試験装置とDUTとの間に設けられるスイッチ回路よりもDUT側にセンシング点を配置することにより、DUTに印加される電圧を正確に反映し、高精度に電圧を増幅することができる。   In the output signal line, a switch circuit is provided between the second resistor and a sensing point where the output signal line and the non-inverting input terminal of the second amplifier are connected. By arranging the sensing point on the DUT side of the switch circuit provided between the test apparatus and the DUT, the voltage applied to the DUT can be accurately reflected and the voltage can be amplified with high accuracy.

さらに第2の電流増幅回路を備え、該第2の電流増幅回路の出力信号線を、第1増幅器の非反転入力端子に接続してもよい。第1増幅器への入力信号が電流制限を受けると帰還がかかり、出力端子から更に電流を流そうとして出力電圧が上昇してしまう。しかし上記構成によれば、電流量を補償して出力電圧の上昇を回避し、電圧・電流制限回路として動作させることができる。   Further, a second current amplifier circuit may be provided, and the output signal line of the second current amplifier circuit may be connected to the non-inverting input terminal of the first amplifier. When the input signal to the first amplifier is subjected to current limitation, feedback is applied, and the output voltage rises as a further current flows from the output terminal. However, according to the above configuration, the amount of current can be compensated to avoid an increase in output voltage, and the circuit can be operated as a voltage / current limiting circuit.

本発明によれば、半導体試験装置のレンジ以上に電圧を増幅して印加し、レンジ以上の電流や微小な電流を測定することができる。   According to the present invention, it is possible to amplify and apply a voltage over a range of a semiconductor test apparatus and measure a current over the range or a minute current.

本発明にかかる電流電圧増幅回路の実施形態について説明する。なお、以下の実施例に示す寸法、材料、その他電圧値や電流値、抵抗値など具体的な数値などは、発明の理解を容易とするための例示に過ぎず、特に断る場合を除き、本発明を限定するものではない。   An embodiment of a current-voltage amplifier circuit according to the present invention will be described. Note that the dimensions, materials, and other specific values such as voltage values, current values, and resistance values shown in the following examples are merely examples for facilitating understanding of the invention, and unless otherwise specified. The invention is not limited.

図1は本実施形態にかかる電流電圧増幅回路の構成を説明する図である。図1に示す回路は、大別すれば電流増幅回路201、電圧比設定回路301、電流オフセット相殺回路401、第2の電流増幅回路501から構成されている。INは入力端子であり、例えば半導体試験装置の制御部から入力信号が印可される。OUTは出力端子であり、例えばDUTに対して出力信号を出力する。   FIG. 1 is a diagram for explaining the configuration of a current-voltage amplifier circuit according to this embodiment. The circuit shown in FIG. 1 includes a current amplifier circuit 201, a voltage ratio setting circuit 301, a current offset cancellation circuit 401, and a second current amplifier circuit 501. IN is an input terminal, for example, an input signal is applied from the control unit of the semiconductor test apparatus. OUT is an output terminal that outputs an output signal to, for example, the DUT.

電流増幅回路201は、反転入力端子と非反転入力端子の2つの入力端子と1つの出力端子を有し、非反転入力端子に入力信号が入力される第1増幅器(以下、「増幅器Q1」という。)と、増幅器Q1の非反転入力端子と出力端子との間に接続される第1抵抗(以下、「抵抗R1」という。)と、増幅器Q1の出力端子と反転入力端子との間に接続される第2抵抗(以下、「抵抗R2」という。)とを備え、抵抗R2と増幅器Q1の反転入力端子との間に被試験デバイス(Device Under Test:以下「DUT」という。)に信号を伝達する出力信号線L1を接続して構成している。出力信号線L1には、DUTとの接続をON/OFFするスイッチ回路としてのリレーS1が設けられている。抵抗R2と増幅器Q1の出力端子との接続位置であるセンシング点Pと称する。   The current amplifier circuit 201 has two input terminals, an inverting input terminal and a non-inverting input terminal, and one output terminal, and a first amplifier (hereinafter referred to as “amplifier Q1”) in which an input signal is input to the non-inverting input terminal. ), A first resistor (hereinafter referred to as “resistor R1”) connected between the non-inverting input terminal and the output terminal of the amplifier Q1, and a connection between the output terminal and the inverting input terminal of the amplifier Q1. And a signal is sent to the device under test (hereinafter referred to as “DUT”) between the resistor R2 and the inverting input terminal of the amplifier Q1. An output signal line L1 for transmission is connected. The output signal line L1 is provided with a relay S1 as a switch circuit for turning on / off the connection with the DUT. This is referred to as a sensing point P which is a connection position between the resistor R2 and the output terminal of the amplifier Q1.

電圧比設定回路301は、出力信号線L1に非反転入力端子が接続され、反転入力端子と出力端子とが短絡された第2増幅器(以下「増幅器Q2」という。)と、増幅器Q1の反転入力端子と接地にその両端が接続される第3抵抗(以下、「抵抗R3]という。)と、増幅器Q1の反転入力端子と増幅器Q2の出力端子にその両端が接続される第4抵抗(以下「抵抗R4]という。)と、を備えている。   In the voltage ratio setting circuit 301, a non-inverting input terminal is connected to the output signal line L1, a inverting input terminal and an output terminal are short-circuited (hereinafter referred to as “amplifier Q2”), and an inverting input of the amplifier Q1. A third resistor (hereinafter referred to as “resistor R3”) whose both ends are connected to the terminal and the ground, and a fourth resistor (hereinafter referred to as “resistor R3”) whose both ends are connected to the inverting input terminal of the amplifier Q1 and the output terminal of the amplifier Q2. Resistor R4]).

電流オフセット相殺回路401は、抵抗R1に出力端子が接続され、反転入力端子と出力端子とが短絡された第3増幅器(以下「増幅器Q3]という。)と、増幅器Q3の非反転入力端子と接地にその両端が接続される第5抵抗(以下「抵抗R5]という。)と、増幅器Q3の非反転入力端子と増幅器Q1の出力端子にその両端が接続される第6抵抗(以下「抵抗R6」という。)と、を備えている。   The current offset cancellation circuit 401 includes a third amplifier (hereinafter referred to as “amplifier Q3”) in which an output terminal is connected to the resistor R1, an inverting input terminal and an output terminal are short-circuited, and a non-inverting input terminal of the amplifier Q3 and a ground. And a sixth resistor (hereinafter referred to as “resistor R6”) whose both ends are connected to the non-inverting input terminal of the amplifier Q3 and the output terminal of the amplifier Q1. And).

第2の電流増幅回路501は、非反転入力端子に入力信号が入力され、反転入力端子と出力端子とが短絡された増幅器Q4と、増幅器Q4の非反転入力端子と出力端子との間にその両端を接続される抵抗R7と、増幅器Q4の出力端子と反転入力端子との間にその両端を接続される抵抗R8とを備え、抵抗R8と増幅器Q4の反転入力端子との間に電流増幅回路201に信号を伝達する出力信号線を接続している。第2の電流増幅回路501から出力された信号は、電流増幅回路201の増幅器Q1の非反転入力端子に入力される。   The second current amplification circuit 501 has an amplifier Q4 in which an input signal is input to the non-inverting input terminal and the inverting input terminal and the output terminal are short-circuited, and between the non-inverting input terminal and the output terminal of the amplifier Q4. A resistor R7 having both ends connected, and a resistor R8 having both ends connected between the output terminal and the inverting input terminal of the amplifier Q4, and a current amplifier circuit between the resistor R8 and the inverting input terminal of the amplifier Q4 An output signal line for transmitting a signal is connected to 201. The signal output from the second current amplifier circuit 501 is input to the non-inverting input terminal of the amplifier Q1 of the current amplifier circuit 201.

上記構成の回路の動作について説明する。信号の流れに沿って、まず第2の電流増幅回路501の動作について説明する。   The operation of the circuit having the above configuration will be described. First, the operation of the second current amplification circuit 501 will be described along the signal flow.

第2の電流増幅回路501において、抵抗R8の下流側の電圧をV2、電流をI2とする。反転入力端子と出力端子とが短絡されていることから、入力端子INの電圧Viと電圧V2は等しくなる。
V2=Vi ・・・・・・・・・・・・・・・・・ (4)
上記背景技術において説明したように、V2は次式で表すことができる。
V2=R8×I2+R7×Ii+Vi ・・・・・ (5)
すると、次式(3)を導出することができる。
I2=−(R7/R8)×Ii ・・・・・・・・ (6)
本実施形態において第2の電流増幅回路501はR7=R8としており、電流を等倍に増幅する(Ii=I2)。なお、電流値は同じであるが、増幅器Q4の電源によって電流を補償することができ、入力信号の電流Iiが電流制限を受けること(許容量を超えてしまって電流が流せない状態)を防止している。これにより出力電圧の上昇を回避し、電圧・電流制限回路として動作させることができる。
In the second current amplifier circuit 501, the voltage downstream of the resistor R8 is V2, and the current is I2. Since the inverting input terminal and the output terminal are short-circuited, the voltage Vi and the voltage V2 at the input terminal IN are equal.
V2 = Vi (4)
As described in the background art above, V2 can be expressed by the following equation.
V2 = R8 × I2 + R7 × Ii + Vi (5)
Then, the following expression (3) can be derived.
I2 = − (R7 / R8) × Ii (6)
In the present embodiment, the second current amplification circuit 501 sets R7 = R8, and amplifies the current at an equal magnification (Ii = I2). Although the current value is the same, the current can be compensated by the power supply of the amplifier Q4, and the current Ii of the input signal is prevented from being limited (a state in which the current cannot exceed the allowable amount and cannot flow). is doing. As a result, an increase in output voltage can be avoided and the voltage / current limiting circuit can be operated.

電流増幅回路201は第2の電流増幅回路501を発展させた回路であって、電流をR1/R2倍に増幅する。そしてセンシング点Pと増幅器Q1の反転入力端子は短絡されておらず、電圧比設定回路301が介在している。   The current amplifier circuit 201 is a circuit obtained by developing the second current amplifier circuit 501 and amplifies the current R1 / R2 times. The sensing point P and the inverting input terminal of the amplifier Q1 are not short-circuited, and the voltage ratio setting circuit 301 is interposed.

電圧比設定回路301において増幅器Q2は、抵抗R3、R4からなる分圧回路に他の回路の影響を遮断するために設けられており、非反転入力端子、反転入力端子、および出力端子のいずれも同じ電圧になっている。そして抵抗R3、R4で分圧された電圧V5が増幅器Q1の非反転入力端子に入力される。増幅器Q1は、この分圧された電圧V5が第2の電流増幅回路501から入力された電圧V2と同じになるように増幅するため、DUTに印加される電圧V4は次式で表される。
V4=(R3+R4)/R3×V2・・・・・・・ (7)
すなわち、電流増幅回路201に電圧比設定回路301を付加することにより、テスタ電圧の印加値を(R3+R4)/(R3)倍に増幅することができる。
In the voltage ratio setting circuit 301, the amplifier Q2 is provided to block the influence of other circuits on the voltage dividing circuit composed of the resistors R3 and R4, and any of the non-inverting input terminal, the inverting input terminal, and the output terminal is provided. The voltage is the same. The voltage V5 divided by the resistors R3 and R4 is input to the non-inverting input terminal of the amplifier Q1. Since the amplifier Q1 amplifies the divided voltage V5 so as to be the same as the voltage V2 input from the second current amplification circuit 501, the voltage V4 applied to the DUT is expressed by the following equation.
V4 = (R3 + R4) / R3 × V2 (7)
That is, by adding the voltage ratio setting circuit 301 to the current amplifier circuit 201, the applied value of the tester voltage can be amplified by (R3 + R4) / (R3) times.

さらに本実施形態においては、リレーS1を、センシング点Pと抵抗R2との間に配置している。このように、スイッチ回路よりもDUT側にセンシング点Pを配置することにより、DUTに印加される電圧を正確に反映し、高精度に電圧を増幅することができる。   Furthermore, in this embodiment, relay S1 is arrange | positioned between the sensing point P and resistance R2. Thus, by arranging the sensing point P on the DUT side of the switch circuit, the voltage applied to the DUT can be accurately reflected and the voltage can be amplified with high accuracy.

ここで、電圧の増幅は、電流が流れていない場合であっても行われる。従って、増幅器Q1の出力端子と入力端子との間には電位差が生じている。そのため、仮に増幅器Q1の出力端子と非反転入力端子とを単に(第2の電流増幅回路501と同様に)抵抗R1によって接続すると電流が流れてしまい、一定の電流値が上乗せされて測定されてしまう。この上乗せされた電流を、オフセット電流と称する。   Here, the amplification of the voltage is performed even when no current flows. Therefore, a potential difference is generated between the output terminal and the input terminal of the amplifier Q1. Therefore, if the output terminal and the non-inverting input terminal of the amplifier Q1 are simply connected by the resistor R1 (similar to the second current amplification circuit 501), a current flows, and a constant current value is added and measured. End up. This added current is referred to as an offset current.

電流オフセット相殺回路401はオフセット電流を削減または解消するために設けられている。増幅器Q1の出力端子からは抵抗R5、R6からなる分圧回路が接地されており、分圧された電圧が増幅器Q3に入力される。増幅器Q3の出力端子は、抵抗R1を介して増幅器Q1の非反転入力端子に接続される。概略としては、電圧比設定回路301の作用によって上昇した電圧を、予め落としてから抵抗R1に入力するものである。   The current offset cancellation circuit 401 is provided to reduce or eliminate the offset current. A voltage dividing circuit including resistors R5 and R6 is grounded from the output terminal of the amplifier Q1, and the divided voltage is input to the amplifier Q3. The output terminal of the amplifier Q3 is connected to the non-inverting input terminal of the amplifier Q1 through the resistor R1. As an outline, the voltage increased by the action of the voltage ratio setting circuit 301 is dropped in advance and then input to the resistor R1.

なお、オフセット電流が発生したとしても、測定値から所定のオフセット電流(DUTに流れる電流が0であるときの測定値)を差し引くことにより、DUTに流れる電流を測定することは可能である。しかし本実施形態のように、電流オフセット相殺回路401によって増幅させた電圧を等倍に近づけることによりオフセット電流を削減することができ、より正確な測定値を得ることができる。特に抵抗R5、R6からなる分圧比と、電圧比設定回路301の抵抗R3、R4からなる分圧比とを等しくすることにより、オフセット電流をほぼ解消することができ、測定値をオフセットするまでもなく正確な値を得ることができる。   Even if the offset current is generated, it is possible to measure the current flowing through the DUT by subtracting a predetermined offset current (measured value when the current flowing through the DUT is 0) from the measured value. However, the offset current can be reduced by making the voltage amplified by the current offset cancellation circuit 401 close to the same magnification as in this embodiment, and a more accurate measurement value can be obtained. In particular, the offset current can be almost eliminated by making the voltage dividing ratio composed of the resistors R5 and R6 equal to the voltage dividing ratio composed of the resistors R3 and R4 of the voltage ratio setting circuit 301, and it is not necessary to offset the measured value. Accurate values can be obtained.

上記構成によれば、本実施形態にかかる電流電圧増幅回路のゲイン値は、次のように表すことができる。
電流ゲイン=R1/R2・・・・・・・・・・・・ (8)
電圧ゲイン=(R3+R4)/R3・・・・・・・ (9)
電流測定値=(R1/R2)×((R3+R4)/R3)・・(10)
ただしR3=R5、R4=R6とする
上記R1〜R6の値を変更することにより、任意の高電圧を印加し、任意のレンジの電流を測定することが可能になる。
According to the above configuration, the gain value of the current-voltage amplifier circuit according to the present embodiment can be expressed as follows.
Current gain = R1 / R2 (8)
Voltage gain = (R3 + R4) / R3 (9)
Current measurement value = (R1 / R2) × ((R3 + R4) / R3) (10)
However, by changing the values of the above R1 to R6 such that R3 = R5 and R4 = R6, it is possible to apply an arbitrary high voltage and measure a current in an arbitrary range.

すなわち、印加する電圧をわずか2つの抵抗R3、R4の比で設定することができるため、簡単な構成で高精度に増幅することができる。従って半導体試験装置と被試験デバイスとの間に本回路を配置することにより、半導体試験装置のレンジ以上の電圧を増幅して印加することができる。また測定する電流についても、出力電流の範囲を2つの抵抗R1、R2の比で設定することができ、簡単な構成で拡縮しうると共に、測定レンジ以上の電流や微小な電流を測定することができる。   That is, since the voltage to be applied can be set by the ratio of only two resistors R3 and R4, it can be amplified with a simple configuration with high accuracy. Therefore, by arranging this circuit between the semiconductor test apparatus and the device under test, a voltage exceeding the range of the semiconductor test apparatus can be amplified and applied. As for the current to be measured, the range of the output current can be set by the ratio of the two resistors R1 and R2, which can be expanded and reduced with a simple configuration, and can measure a current exceeding the measurement range or a minute current. it can.

なお、電圧比設定回路301において抵抗R3、R4を設けずに、増幅器Q2の出力端子と増幅器Q1の反転入力端子に直接接続することもできる。これにより、等倍の電圧ゲインとなるが、DUTから受ける変動の影響を遮断し、高度に安定化した電圧を印加することができる。この場合において電流オフセット相殺回路401が不要であることはいうまでもない。   The voltage ratio setting circuit 301 may be directly connected to the output terminal of the amplifier Q2 and the inverting input terminal of the amplifier Q1 without providing the resistors R3 and R4. Thereby, the voltage gain becomes equal, but the influence of fluctuations received from the DUT can be cut off and a highly stabilized voltage can be applied. In this case, it goes without saying that the current offset canceling circuit 401 is unnecessary.

図2に、半導体試験装置の全体構成を示す。図2において、2は半導体試験装置本体、3はDUTが搭載されているテストロードである。半導体試験装置本体2には電源やDCパラメトリック測定器が内蔵されている。   FIG. 2 shows the overall configuration of the semiconductor test apparatus. In FIG. 2, 2 is a semiconductor test apparatus main body, and 3 is a test load on which a DUT is mounted. The semiconductor test apparatus main body 2 includes a power source and a DC parametric measuring instrument.

半導体試験装置では、その構成上、半導体試験装置本体2とテストロード3との間の距離は5〜10mと長くなることが多い。また、半導体試験装置本体2からテストロード3に供給する電流は数μAの微少電流から数十Aの大電流まで幅があり、かつ急激に変動する場合が多い。   In the semiconductor test apparatus, the distance between the semiconductor test apparatus main body 2 and the test load 3 is often as long as 5 to 10 m due to its configuration. Further, the current supplied from the semiconductor test apparatus main body 2 to the test load 3 has a range from a very small current of several μA to a large current of several tens of A and often fluctuates rapidly.

例えば、正常状態では数μAの電流で動作しているDUTが動作不良になると、急激な電圧降下が発生して数十Aの電流が流れる。この電流のためにDUTが破壊されると、電流値は数μAに急激に減少する。   For example, in a normal state, when a DUT operating with a current of several μA malfunctions, a sudden voltage drop occurs and a current of several tens of A flows. When the DUT is destroyed due to this current, the current value rapidly decreases to several μA.

半導体試験装置本体2からテストロード3に微少電流を流すと、この間のケーブルの容量のために静定時間が長くなる。また、急激に変化する大電流を流すと、ケーブルのインダクタンスのためにテストロード3端での電圧の変化が緩やかになってしまう。   When a minute current is supplied from the semiconductor test apparatus main body 2 to the test load 3, the stabilization time becomes longer due to the cable capacity during this period. In addition, when a large current that changes rapidly is applied, the voltage change at the end of the test load 3 becomes gradual due to the inductance of the cable.

そのため、半導体試験装置本体2からはケーブルの容量やインダクタンスの影響を受けにくい大きさの電流で供給し、テストロード3に本発明の電流電圧増幅回路を搭載し、増幅あるいは減衰してからDUTに供給するようにすると、高精度な測定が可能になる。   For this reason, the semiconductor test apparatus body 2 is supplied with a current that is not easily affected by the capacitance and inductance of the cable, and the current voltage amplifier circuit of the present invention is mounted on the test load 3 to be amplified or attenuated before being supplied to the DUT. If it supplies, a highly accurate measurement will be attained.

以上、添付図面を参照しながら本発明の好適な実施例について説明したが、本発明は係る例に限定されないことは言うまでもない。当業者であれば、特許請求の範囲に記載された範疇内において、各種の変更例または修正例に想到し得ることは明らかであり、それらについても当然に本発明の技術的範囲に属するものと了解される。   Although the preferred embodiments of the present invention have been described above with reference to the accompanying drawings, it goes without saying that the present invention is not limited to such examples. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

本発明は、電流および電圧を増幅あるいは減衰する電流電圧増幅回路に関し、特にLSIテスタや電流電圧測定器に用いて好適な電流電圧増幅回路、およびこれを用いた半導体試験装置として利用することができる。   The present invention relates to a current-voltage amplifier circuit that amplifies or attenuates current and voltage, and in particular, can be used as a current-voltage amplifier circuit suitable for use in an LSI tester or a current-voltage measuring instrument, and a semiconductor test apparatus using the same. .

実施形態にかかる電流電圧増幅回路の構成を説明する図である。It is a figure explaining the structure of the current voltage amplifier circuit concerning embodiment. 半導体試験装置の全体構成を示す図である。It is a figure which shows the whole structure of a semiconductor test apparatus. 従来例にかかる電流増幅回路101の基本構成を説明する図である。It is a figure explaining the basic composition of the current amplification circuit 101 concerning a prior art example. 従来例にかかる電流増幅回路を2つ直列に接続して、電流制限機能を付加した構成を示す図である。It is a figure which shows the structure which connected two current amplifier circuits concerning a prior art example in series, and added the current limiting function.

符号の説明Explanation of symbols

L1 …出力信号線
P …センシング点
Q1〜Q4 …増幅器
R1〜R6 …抵抗
S1、S2 …リレー
2 …半導体試験装置本体
3 …テストロード
101 …電流増幅回路
102 …電流増幅回路
201 …電流増幅回路
301 …電圧比設定回路
401 …電流オフセット相殺回路
501 …第2の電流増幅回路
L1 ... Output signal line P ... Sensing points Q1 to Q4 ... Amplifiers R1 to R6 ... Resistors S1 and S2 ... Relay 2 ... Semiconductor test equipment body 3 ... Test load 101 ... Current amplifier circuit 102 ... Current amplifier circuit 201 ... Current amplifier circuit 301 ... Voltage ratio setting circuit 401 ... Current offset cancellation circuit 501 ... Second current amplification circuit

Claims (5)

非反転入力端子に入力信号が入力され、非反転入力端子と出力端子との間に電流オフセット相殺回路と第1抵抗が直列接続され、出力端子と反転入力端子との間に第2抵抗と電圧比設定回路が直列接続され、第2抵抗と電圧比設定回路との間に被試験デバイスに信号を伝達する出力信号線が接続される第1増幅器を備えた電流増幅回路を有し、
前記電圧比設定回路は、前記出力信号線に非反転入力端子が接続され、反転入力端子と出力端子とが短絡され、出力端子は第3抵抗と第4抵抗の直列回路を介して接地され、第3抵抗と第4抵抗の間に前記第1増幅器の反転入力端子が接続される第2増幅器で構成され、
前記電流オフセット相殺回路は、出力端子が前記第1抵抗を介して前記第1増幅器の非反転入力端子に接続され、反転入力端子と出力端子とが短絡され、非反転入力端子が第5抵抗を介して接地されるとともに第6抵抗を介して前記前記第1増幅器の出力端子に接続される第3増幅器で構成されたことを特徴とする電流電圧増幅回路。
An input signal is input to the non-inverting input terminal, a current offset cancellation circuit and a first resistor are connected in series between the non-inverting input terminal and the output terminal, and a second resistor and voltage are connected between the output terminal and the inverting input terminal. A current amplifying circuit including a first amplifier, in which a ratio setting circuit is connected in series, and an output signal line for transmitting a signal to the device under test is connected between the second resistor and the voltage ratio setting circuit;
In the voltage ratio setting circuit, a non-inverting input terminal is connected to the output signal line, an inverting input terminal and an output terminal are short-circuited, and an output terminal is grounded via a series circuit of a third resistor and a fourth resistor, A second amplifier in which an inverting input terminal of the first amplifier is connected between a third resistor and a fourth resistor;
The current offset cancellation circuit has an output terminal connected to the non-inverting input terminal of the first amplifier via the first resistor, the inverting input terminal and the output terminal are short-circuited, and the non-inverting input terminal has a fifth resistor. And a third amplifier connected to the output terminal of the first amplifier via a sixth resistor .
前記第3抵抗および第4抵抗の比と、前記第5抵抗および第6抵抗の比が等しいことを特徴とする請求項1記載の電流電圧増幅回路。 2. The current-voltage amplifier circuit according to claim 1 , wherein a ratio of the third resistor and the fourth resistor is equal to a ratio of the fifth resistor and the sixth resistor . 前記出力信号線において、該出力信号線と前記第2増幅器の非反転入力端子とが接続されるセンシング点と前記第2抵抗との間に、スイッチ回路を設けたことを特徴とする請求項1記載の電流電圧増幅回路。 In the output signal line, according to claim 1, wherein during the sensing point and the non-inverting input terminal of said the output signal line and the second amplifier is connected to said second resistor, in that a switching circuit The current-voltage amplifier circuit described. さらに第2の電流増幅回路を備え、該第2の電流増幅回路の出力信号線を、前記第1増幅器の非反転入力端子に接続したことを特徴とする請求項1記載の電流電圧増幅回路。 The current-voltage amplifier circuit according to claim 1 , further comprising a second current amplifier circuit, wherein an output signal line of the second current amplifier circuit is connected to a non-inverting input terminal of the first amplifier . 被試験デバイスの電気的試験を行う半導体試験装置であって、A semiconductor test apparatus for conducting an electrical test of a device under test,
被試験デバイスに電圧を印加して電流を測定する制御部と、A control unit that applies a voltage to the device under test and measures current;
請求項1乃至請求項4のいずれか1項記載の電流電圧増幅回路とを備えたことを特徴とする半導体試験装置。A semiconductor test apparatus comprising the current-voltage amplifier circuit according to claim 1.
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