JP4973263B2 - Connection failure detection circuit and method - Google Patents

Description

  The present invention relates to a connection failure detection circuit and method, and more particularly to a connection failure detection circuit that detects a connection failure in a transmission line connecting a driver circuit and a receiver circuit.

  Due to the increase in the number of pins of LSI, the terminal density is increased in the semiconductor integrated circuit, and the connection pads such as solder failures are likely to occur due to the miniaturization of the connection pads. In addition, the LSI package is becoming larger, and connection failure is likely to occur due to distortion or the like generated in the LSI package. As a confirmation method when a connection failure occurs, there is a method of detecting a physical connection by electrical measurement using an external measurement device such as a curve tracer. In this method, by utilizing the characteristics of an ESD (electro-static discharge) circuit connected to an external connection terminal of a driver circuit or a receiver circuit, whether or not the connection is open, that is, connected to the ESD circuit. It is detected electrically.

  Unlike the above, there is a technique described in Patent Document 1 as a technique for detecting a connection failure without using an external measuring device. In the semiconductor integrated circuit described in Patent Document 1, the receiver side of the transmission line is terminated by a termination resistor. In the connection failure test, a test signal is sent from the driver side, and then the potential of the output node of the driver is compared with a predetermined reference potential. In a situation where no connection failure occurs, the signal transmitted from the driver side is not reflected on the receiver side. On the other hand, when there is a connection failure between the output node of the driver and the receiver circuit, signal reflection occurs at that point, thereby increasing the potential of the output node. By detecting this potential increase of the output node, it can be determined whether or not there is a connection failure.

JP 2006-278797 A

  In the method of detecting a connection failure using the characteristics of the ESD circuit using an external measuring instrument, when the ESD circuit is connected to both ends of the signal transmission line, the connection failure occurs on either side. However, there is a problem that this cannot be detected. That is, as shown in FIG. 3, when the driver circuit 201 and the receiver circuit 202 are connected by a signal transmission path 203 on the same printed circuit board, the output terminal 204 of the driver circuit 201 is connected to the output circuit 204 in the driver circuit. Since the ESD circuit 205 and the ESD circuit 206 in the receiver circuit 202 are connected, even when a connection failure occurs at the output terminal 204, the characteristics of the ESD circuit 206 in the receiver circuit 202 are detected by an external measurement device. Connection failure cannot be detected.

  Moreover, in patent document 1, the presence or absence of connection failure generation | occurrence | production is detected by the presence or absence of signal reflection. Considering that this technology is applied to a configuration in which the input terminal of the receiver circuit is connected to the ESD circuit, in the configuration in which the ESD circuit is connected, signal reflection occurs even when there is no connection failure at the receiver end. Therefore, it cannot be determined whether signal reflection has occurred due to poor connection. That is, the technique described in Patent Document 1 is a technique that can be applied to a configuration in which a transmission line is connected to a termination resistor. However, this technology is used as it is in a configuration in which an ESD circuit is connected to an input terminal of a receiver circuit. It cannot be applied.

  The present invention provides a connection failure detection circuit and a connection failure detection method capable of detecting a connection failure between a driver and a receiver without using an external measuring device even for a semiconductor integrated circuit having an ESD circuit on the receiver side. With the goal.

In order to achieve the above object, a connection failure detection circuit according to the present invention is a connection failure detection circuit for detecting a connection failure in a transmission line connecting a driver circuit and a receiver circuit, from the driver circuit via the transmission line. A test signal transmission circuit for transmitting a test signal toward the receiver circuit; and a reflection amplitude of a reflected wave of the test signal in the receiver circuit at the time of a test , a sum of an initial amplitude of the test signal and the reflection amplitude And a reflection amplitude control circuit that limits the amplitude of the output voltage of the driver circuit to a limit voltage lower than the power supply voltage of the driver circuit, and the output node voltage of the test signal transmission circuit is detected at a predetermined timing after the test signal is transmitted a voltage detection circuit for output, said voltage voltage detected by the detection circuit, than and the limit voltage lower than the power supply voltage of the driver circuit Ku is higher than the set determination voltage, characterized in that it comprises, a judging circuit judges that the connection failure has occurred in the transmission line.

A connection failure detection method according to the present invention is a connection failure detection method for detecting a connection failure in a transmission line connecting a driver circuit and a receiver circuit, and the test signal transmission circuit causes the driver circuit to pass through the transmission line. A test signal is sent to the receiver circuit, and the reflected amplitude of the reflected wave of the test signal is the sum of the initial amplitude of the test signal and the reflected amplitude with respect to the test signal. A reflected wave whose amplitude is limited to a voltage that is lower than the power supply voltage of the driver circuit is generated, and the voltage of the output node of the test signal transmission circuit is detected at a predetermined timing after the test signal is transmitted. out, the detected voltage, the higher than higher set determination voltage than and the limit voltage lower than the power supply voltage of the driver circuit, the heat transfer Judged to be defective connection to the line is generated, characterized in that.

  In the connection failure detection circuit and method of the present invention, at the time of testing, the amplitude of signal reflection in the receiver circuit is limited to a predetermined amplitude, the test signal is transmitted from the driver circuit side, and the test signal transmitted in the driver circuit is transmitted. A connection failure is detected by detecting the amplitude of the reflected signal with respect to. When there is a poorly connected part on the transmission line, the reflected signal is reflected at that point, so that the reflected amplitude is larger than a predetermined amplitude limited in the receiver circuit. Therefore, by checking the reflection amplitude, it is possible to check whether the test signal sent from the driver circuit has reached the receiver circuit, and a connection failure occurs between the driver circuit and the receiver circuit. It can be detected whether or not.

In the connection failure detection method of the present invention, the reflection amplitude control circuit clamps the amplitude of the test signal to the limit voltage during a test, and totally reflects a signal transmitted through the transmission line during a normal operation. It is possible to adopt a configuration that allows If the signal is totally reflected in the receiver circuit during the test as in normal operation, the signal amplitude reflected in the driver circuit is detected on the driver circuit side. It is impossible to determine whether the signal is reflected at the terminal. Therefore, during the test, in order to limit the reflection amplitude to a desired amplitude, the reflection amplitude control circuit clamps the amplitude of the test signal to the limit voltage . In this way, by controlling the reflection amplitude when the signal is reflected in the receiver circuit to a different amplitude between the normal operation and the test, whether or not the test signal has reached the receiver circuit on the driver circuit side. Can be determined.

  In the connection failure detection circuit of the present invention, the reflection amplitude control circuit connects the ESD circuit connected to the input terminal of the receiver circuit and the cathode of the ESD circuit to a low-potential side power supply during a test, and A configuration including an ESD connection switching circuit for connecting the cathode of the ESD circuit to the high potential side power supply can be employed. In this case, during normal operation, even if an interface signal transmitted from the driver circuit side is input to the input terminal, the ESD circuit is in a reverse bias state, so the ESD circuit does not affect the interface signal. On the other hand, during a test, when a test signal is input to the input terminal, the ESD circuit is in a forward bias state, and the voltage at the input terminal is clamped to the forward voltage of the ESD circuit. In this way, by switching the connection destination of the ESD circuit by the ESD connection switching circuit, the reflection amplitude can be controlled to be different between the normal operation and the test.

In the connection failure detection circuit according to the present invention, the voltage detection circuit detects the voltage of the output node at a timing after the test signal is sent and after the time when the test signal reciprocates through the transmission line. it can. Further, in the connection failure detection circuit of the present invention, the voltage detection circuit detects the voltage of the output node at a timing before the test signal reciprocates through the transmission line after the test signal is sent. Can be adopted. When a connection failure has occurred at the driver end of the transmission line, the test signal sent from the test signal sending circuit is totally reflected at the output terminal of the driver circuit, so the voltage at the output node of the test signal sending circuit Immediately after sending the test signal, the voltage rises to a voltage corresponding to total reflection. On the other hand, if a connection failure has occurred at the receiver end of the transmission line, the test signal is reflected at the input terminal of the receiver circuit and returns to the receiver circuit after going back and forth along the transmission line. The voltage at the output node rises to a voltage corresponding to total reflection after the test signal reciprocates through the transmission line. Therefore, by detecting the reflection amplitude at a timing after the test signal travels back and forth in the transmission line within the driver circuit, it is determined whether the test signal has reached the receiver circuit, that is, there is a connection failure. It can be determined whether or not it has occurred. In addition, a connection failure has occurred by detecting the reflection amplitude at two timings before and after the test signal travels back and forth on the transmission line, and examining from which timing the voltage corresponding to the total reflection is detected. In this case, it can be determined whether the connection failure occurs at the driver end or the receiver end.

In connection failure detection circuit of the present invention, the voltage detection circuit after transmission of the test signal, takes in the voltage of the output node of said test signal sending circuit at a predetermined timing, than the voltage of the output node is the determination voltage A configuration including a flip-flop circuit that inverts the output between “1” and “0” depending on whether it is high or not can be adopted. In this case, the flip-flop circuit may employ a configuration that outputs “1” if the voltage of the output node is equal to or higher than the determination voltage, and outputs “0” if the voltage is lower than the determination voltage . By like this, the value of the flip-flop circuit is outputted, in the case where the test signal arrives at the receiver circuit, the reflected amplitude is limited to a predetermined amplitude, and if totally reflected at the connection failure location By inverting the output of the flip-flop circuit, it can be determined whether there is a connection failure.

In the connection failure detection circuit of the present invention, the voltage detection circuit takes in the voltage of the output node at a timing after the time when the test signal reciprocates through the transmission line elapses after the test signal is sent. A configuration including one flip-flop and a second flip-flop circuit that takes in the voltage of the output node after a time for the test signal to reciprocate through the transmission line can be employed. In this case, it is possible to determine whether or not a connection failure has occurred by examining the output of the second flip-flop circuit. Further, by comparing the output of the first flip-flop circuit and the output of the second flip-flop circuit, when the connection failure occurs, the connection failure occurs at the driver end, or It can be determined whether the error occurs at the receiver end.

In the connection failure detection circuit of the present invention, the determination circuit determines whether or not a connection failure has occurred in the transmission line based on the output of the first flip-flop and the output of the second flip-flop. and, if connection failure occurs in the driver end of the transmission line, it can be adopted the configuration you determine has occurred at the receiver end. In this case, in a semiconductor integrated circuit having a connection failure detection circuit, it is possible to determine whether or not a connection failure has occurred, and to identify the location where the connection failure has occurred. Judgment can be made.

  In the connection failure detection circuit and method of the present invention, at the time of testing, the amplitude of signal reflection in the receiver circuit is limited to a predetermined amplitude, the test signal is transmitted from the driver circuit side, and the test signal transmitted in the driver circuit is transmitted. The amplitude of the reflected signal with respect to is detected. When there is a poorly connected part on the transmission line, the reflected signal is reflected at that point, so that the reflected amplitude is larger than a predetermined amplitude limited in the receiver circuit. Therefore, by examining the reflection amplitude, it is possible to examine whether or not the test signal transmitted from the driver circuit has reached the receiver circuit. Therefore, in the present invention, it is possible to detect whether or not a connection failure has occurred between the driver circuit and the receiver circuit without using an external measuring device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. The semiconductor integrated circuit 100 includes a driver circuit 101 and a receiver circuit 102. The driver circuit 101 includes flip-flop circuits 111, 120, and 122, an output circuit 112, an ESD circuit 113, receivers 119 and 121, delay circuits 123 and 124, and a determination circuit 126. The receiver circuit 102 includes an input circuit 118, an ESD circuit 117, and an ESD connection switching circuit 125. The output terminal 114 of the driver circuit 101 and the input terminal 116 of the receiver circuit 102 are connected by a transmission line 103 such as a printed wiring board.

  The flip-flop circuit 111 is a part of the internal logic unit. The output circuit 112 outputs the output of the flip-flop circuit 111 from the output terminal 114 toward the transmission line 103. The flip-flop circuit 111 and the output circuit 112 constitute a test signal output circuit, and outputs a test signal toward the transmission line 103 during the test. An ESD circuit 113 is inserted between the output terminal 114 and the Vdd power supply line. A signal output from the output terminal 114 is input to the input terminal 116 of the receiver circuit 102 via the transmission line 103. A signal input to the input terminal 116 is output to an internal logic unit (not shown) by the input circuit 118.

  The ESD circuit 117 of the receiver circuit 102 is connected between the input terminal 116 and the ESD connection switching circuit 125. The ESD connection switching circuit 125 switches the voltage applied to the cathode of the diode constituting the ESD circuit 117 between the Vdd power supply and GND based on a command from a control unit (not shown). In the normal use state of the semiconductor integrated circuit 100, the ESD connection switching circuit 125 connects the cathode of the diode constituting the ESD circuit 117 to the Vdd power supply. Further, when the connection failure test is performed in the semiconductor integrated circuit 100, the cathode of the diode constituting the ESD circuit 117 is connected to the GND. The ESD circuit 117 and the ESD connection switching circuit 125 constitute a reflection amplitude control circuit that limits the reflection amplitude with respect to the signal input to the receiver circuit 102 to a predetermined amplitude during the test.

  The node N1 between the output circuit 112 and the output terminal 114 of the driver circuit 101 has two sets of reflection amplitude detection circuits (receiver 119 and flip-flop circuit 120, receiver 121 and flip-flop, each composed of a receiver and a flip-flop. Circuit 122) is connected. The reflection amplitude detection circuit detects the amplitude of the reflection signal based on the voltage at the node N1. More specifically, after the signal is output by the output circuit 112, the voltage of the node N1 is taken in, and it is detected whether or not the voltage of the node N1 is higher than a predetermined level.

  The flip-flop circuit 120 latches the voltage of the node N1 input through the receiver 119 based on the clock signal delayed by the delay circuit 123 by a predetermined delay time (TD1). The flip-flop circuit 122 latches the voltage of the node N1 input through the receiver 121 based on the clock signal delayed by a predetermined delay time (TD2) by the delay circuit 124. The delay times of the delay circuits 123 and 124 are adjusted so that the flip-flop circuits 120 and 122 can latch the node N1 at a predetermined timing, respectively.

  When the test signal transmitted from the driver circuit 101 reaches the receiver circuit 102, the amplitude of the test signal is limited to a predetermined amplitude by the ESD circuit 117. On the other hand, when a connection failure occurs between the output terminal of the driver circuit 101 and the input terminal of the receiver circuit 102 and there is an open part, signal reflection occurs at that point. Therefore, the presence / absence of a connection failure can be determined from the amplitude after the test signal is transmitted. The determination circuit 126 determines the presence or absence of signal reflection based on the data latched by the flip-flop circuits 120 and 122. That is, it is determined whether the transmission line 103 is normally connected or open. A large-scale semiconductor integrated circuit (hereinafter referred to as LSI) is generally in a case called a package and is rarely directly connected to a printed circuit board, but here, for convenience of explanation, The driver circuit 101 will be described as including an LSI package.

  An operation during normal operation of the semiconductor integrated circuit 100 will be described. During normal operation, that is, when a signal (interface signal) is exchanged between the driver circuit 101 and the receiver circuit 102, the power supply line Vdd is in an on state. The ESD connection switching circuit 125 selects the Vdd power supply side, and the voltage Vdd is applied to the cathode of the diode constituting the ESD circuit 117 in the receiver circuit 102. In this state, even if a voltage lower than the voltage Vdd is applied to the input terminal 116, the diode constituting the ESD circuit 117 is reverse-biased, so that the interface signal is the same as the open state. Therefore, the ESD circuit 117 does not affect the operation with respect to the interface signal.

  Next, the operation when testing for defective connections will be described. In the test, the ESD connection switching circuit 125 selects the GND side, and the cathode of the ESD circuit 117 in the receiver circuit 102 becomes the GND voltage. In this state, when a voltage is applied to the input terminal 106, the diode constituting the ESD circuit 117 is forward-biased, so that a current flows into the ESD circuit 117. Assuming that the forward voltage of the diode is Vf, the potential difference between GND and the input terminal 116 is Vf. Therefore, even when a voltage higher than the forward voltage Vf is applied to the input terminal 116, it is higher than the forward voltage Vf. It will be clamped without applying a high voltage.

  FIG. 2 shows an operation waveform of the node N 1 in the driver circuit 101. (A) is an operation waveform when the receiver end is open, (b) is an operation waveform when the connection is normal, and (c) is an operation when the driver end is open. The waveform is shown. Hereinafter, in order to simplify the description, the output impedance of the driver circuit 101 and the impedance of the transmission line 103 are assumed to be the same.

  First, the case where the receiver end is open, that is, the case where a connection failure occurs at the connection point between the input terminal 116 and the transmission line 103 will be described. At the time of testing, a test signal is output from the flip-flop circuit 111 at a predetermined clock timing. This test signal is sent to the transmission line 103 via the output circuit 112. Assuming that the impedance of the driver circuit 101 is equal to the impedance of the transmission line 103, the initial amplitude of the test signal is half the amplitude (Vdd / 2) of the power supply voltage Vdd of the driver circuit 101.

  When a test signal having an amplitude of Vdd / 2 reaches the receiver end, since the connection point between the input terminal 116 and the transmission line 103 is not connected at the receiver end of the transmission line 103, the test signal is Total reflection is performed at the receiver end, and a reflected signal (reflected wave) having an amplitude Vdd / 2 is generated. The reflected wave returns to the driver circuit 101, so that the voltage at the node N1 has an initial amplitude (Vdd / 2) after the time when the test signal reciprocates through the transmission line 103 from the timing when the test signal is output. ) And the reflection amplitude (Vdd / 2) is Vdd (FIG. 2A).

  Next, a case where no connection failure has occurred will be described. The point that the initial amplitude of the test signal output to the transmission line 103 is Vdd / 2 is the same as when the receiver end is open. Since the ESD circuit 117 having the forward voltage Vf is connected to the input terminal 116, a reflected wave having a reflected amplitude of Vdd / 2 is generated with respect to a test signal having an originally reflected amplitude of Vdd / 2. Thus, it should be Vdd, and is clamped at the Vf voltage by the ESD circuit 117. Therefore, the voltage at the node N1 becomes the voltage Vf clamped by the ESD circuit 117 after the time when the test signal reciprocates through the transmission line 103 from the timing when the test signal is output (FIG. 2B).

  Next, a case where the driver end is open, that is, a case where a connection failure occurs at the connection point between the output terminal 114 and the transmission line 103 will be described. When the flip-flop circuit 111 outputs a test signal, the output circuit 112 tries to send the test signal to the transmission line 103, but the connection point between the output terminal 114 and the transmission line 103 is at the driver end of the transmission line 103. Not connected. In this case, the initial amplitude of the test signal becomes the same voltage as the power supply voltage Vdd, and the voltage at the node N1 becomes Vdd immediately after the output of the test signal (FIG. 2C).

  Referring to FIGS. 2A to 2C, the manner in which the voltage at the node N1 changes varies depending on whether or not a connection failure has occurred and the location where it occurs. Accordingly, by latching the node N1 before and after the signal round-trip time of the transmission line 103 by the flip-flop circuits 120 and 122, it is possible to determine whether or not a connection failure has occurred and where it occurs. The delay time (TD1) of the delay circuit 123 is set to be shorter than the time for the test signal to reciprocate through the transmission line 103, and the delay time (TD2) of the delay circuit 124 is the time for the test signal to reciprocate through the transmission line 103. Is set to a longer time. Further, the determination voltage when the flip-flop circuits 120 and 122 determine the logic of the node N1, that is, whether the latched signal is “0” or “1” when the node N1 is latched. The determination voltage when determining is a voltage lower than Vdd and higher than Vdd / 2 and Vf.

  When a connection failure occurs at the receiver end, as shown in FIG. 2A, at the latch timing of the flip-flop circuit 120, the voltage of the node N1 is Vdd / 2, and Vdd / 2 <determination voltage. Therefore, the flip-flop circuit 120 captures “0”. Further, at the latch timing of the flip-flop circuit 122, the voltage of the node N1 becomes Vdd, and Vdd> the determination voltage, so that the flip-flop circuit 122 takes in “1”. Therefore, the data output from the flip-flop 120 is “0”, and the data output from the flip-flop 122 is “1”.

  When no connection failure has occurred, as shown in FIG. 2B, the voltage of the node N1 is Vdd / 2 at the latch timing of the flip-flop circuit 120, so that the flip-flop circuit 120 captures 0 ″. At the latch timing of the flip-flop circuit 122, the voltage at the node N1 is slightly higher than Vdd / 2 and becomes Vf, but since Vf <the determination voltage, the flip-flop circuit 120 captures “0”. Therefore, the data output from the flip-flop 120 and the flip-flop 122 are both “0”.

  When a connection failure occurs at the driver end, as shown in FIG. 2C, the potential of the node N1 becomes Vdd immediately after the output of the test signal, so that the flip-flop circuits 120 and 122 are respectively Capture “1”. Therefore, the data output from the flip-flop 120 and the flip-flop 122 are both “1”.

  The determination circuit 126 determines the presence / absence of a connection failure and the occurrence location from the combination of the data output from the flip-flop circuit 120 and the data output from the flip-flop circuit 122. That is, if the data output from the flip-flop circuit 120 is “0” and the data output from the flip-flop circuit 122 is “1”, it is determined that a connection failure has occurred at the receiver end. If the data output from the flip-flop circuit 120 is “0” and the data output from the flip-flop circuit 122 is also “0”, it is determined that no connection failure has occurred. If the data output from the flip-flop circuit 120 is “1” and the data output from the flip-flop circuit 122 is also “1”, it is determined that a connection failure has occurred at the driver end.

  In the present embodiment, during normal operation, the ESD connection switching circuit 125 causes the cathode connection destination of the ESD circuit 117 to be a Vdd power supply, so that the ESD circuit 117 functions as an electrostatic protection element, while during testing, an ESD connection is established. By using the switching circuit 125 to connect the cathode of the ESD circuit 117 to GND, the ESD circuit 117 clamps the amplitude of the reflected wave with respect to the test signal to a predetermined voltage level (Vf). By doing so, the amplitude of the test signal observed on the driver circuit 101 side is different depending on whether or not a connection failure represented by a solder failure occurs in the transmission line 103 or not. Can be. Therefore, the driver circuit 101 captures the waveform of the test signal emitted from the driver end reflected from the receiver end, and logically determines this, whereby it is possible to logically easily determine the presence / absence of a connection failure. .

  In this embodiment, two sets of reflection amplitude detection circuits detect the reflection amplitude of the transmitted test signal before and after the signal round-trip time of the transmission line 103. When the connection failure occurs at the driver end, the reflection amplitude becomes Vdd immediately after the test signal is sent. When the connection failure occurs at the receiver end, the reflection amplitude is transmitted after the test signal is sent. It becomes Vdd after the elapse of time for traveling back and forth on the line 103. Therefore, by detecting the reflection amplitude before and after the signal round-trip time of the transmission line 103, and examining the combination of the reflection amplitude before and after the signal round-trip time, the connection failure occurs at the driver end or the receiver end. You can identify if there is.

  In the present embodiment, the determination circuit 126 in the semiconductor integrated circuit 100 can determine whether or not a connection failure has occurred and can identify the location where the connection has occurred, and can easily and without occurrence of a connection failure without using an external device. And the location of the occurrence can be specified. Furthermore, the detection of connection failure can be easily realized by switching the control in the environment where the information processing apparatus in which the semiconductor integrated circuit 100 is mounted is operated, and the effect that connection analysis is not required can be facilitated. is there.

  Although the present invention has been described based on the preferred embodiment, the connection failure detection circuit and method of the present invention are not limited to the above embodiment, and various modifications and changes can be made to the configuration of the above embodiment. Changes are also included in the scope of the present invention.

1 is a block diagram showing a configuration of a semiconductor integrated circuit including a connection failure detection circuit according to an embodiment of the present invention. (A)-(c) is a wave form diagram which shows the signal waveform observed by a driver end. The block diagram which shows the connection state of the conventional driver circuit and receiver circuit.

Explanation of symbols

100: semiconductor integrated circuit 101: driver circuit 102: receiver circuit 103: transmission lines 111, 120, 122: flip-flop circuit 112: output circuit 113, 117: ESD circuit 114: output terminal 116: input terminal 118: input circuit 119, 121: Receiver 123, 124: Delay circuit 125: ESD connection switching circuit 126: Determination circuit

Claims (10)

In a connection failure detection circuit that detects a connection failure in a transmission line that connects a driver circuit and a receiver circuit,
A test signal sending circuit for sending a test signal from the driver circuit to the receiver circuit via the transmission line;
At the time of testing, the reflected amplitude of the reflected wave in the receiver circuit of the test signal is the amplitude at which the sum of the initial amplitude of the test signal and the reflected amplitude is a lower limit voltage than the power supply voltage of the driver circuit Reflection amplitude control circuit to limit to,
After transmission of the test signal, at a predetermined timing, a voltage detection circuit that detect the voltage of the output node of said test signal sending circuit,
If the voltage detected by the voltage detection circuit is higher than the determination voltage set lower than the power supply voltage of the driver circuit and higher than the limit voltage, it is determined that a connection failure has occurred in the transmission line. A connection failure detection circuit, comprising: The connection according to claim 1, wherein the reflection amplitude control circuit clamps the amplitude of the test signal to the limit voltage during a test and totally reflects a signal transmitted through the transmission line during a normal operation. Defect detection circuit.   The reflection amplitude control circuit connects an ESD circuit connected to an input terminal of the receiver circuit, a cathode of the ESD circuit to a low potential side power source during a test, and a cathode of the ESD circuit during a normal operation. The connection failure detection circuit according to claim 1, further comprising an ESD connection switching circuit connected to the connection. 4. The voltage detection circuit according to claim 1, wherein after the test signal is sent, the voltage of the output node is detected at a timing later than a time when the test signal reciprocates through the transmission line. Connection failure detection circuit. 5. The voltage detection circuit according to claim 1, wherein after the test signal is sent, the voltage of the output node is detected at a timing before the test signal reciprocates through the transmission line. Connection failure detection circuit. The voltage detection circuit after transmission of the test signal, takes in the voltage of the output node of said test signal sending circuit at a predetermined timing, depending on whether the voltage of the output node is higher than the determination voltage, the output " and a flipflop circuit which inverts between 1 "and" 0 ", connection failure detector circuit according to any one of claims 1-5.   The connection failure detection circuit according to claim 6, wherein the flip-flop circuit outputs “1” if the voltage of the output node is equal to or higher than the determination voltage, and outputs “0” if the voltage is lower than the determination voltage. The voltage detection circuit, wherein after delivery of the test signal, a first flip flop for capturing the voltage of said output node at a timing earlier than the time said test signal reciprocates the transmission line has passed, the test signal The connection failure detection circuit according to claim 6 , further comprising: a second flip-flop circuit that takes in the voltage of the output node after elapse of time for reciprocating through the transmission line. The determination circuit determines whether a connection failure has occurred in the transmission line based on the output of the first flip-flop and the output of the second flip-flop, and whether the connection failure has occurred in the transmission line. or occurring in the driver end, you determine has occurred at the receiver end, connection failure detection circuit of claim 8. A connection failure detection method for detecting a connection failure of a transmission line connecting a driver circuit and a receiver circuit,
A test signal sending circuit sends a test signal from the driver circuit to the receiver circuit via the transmission line,
In the receiver circuit, with respect to the test signal, the reflected amplitude of the reflected wave of the test signal is limited such that the sum of the initial amplitude of the test signal and the reflected amplitude is lower than the power supply voltage of the driver circuit Generates a reflected wave limited in amplitude to become a voltage ,
After transmission of the test signal, at a predetermined timing, it detects the voltage of the output node of said test signal sending circuit,
If the detected voltage is lower than the power supply voltage of the driver circuit and higher than a determination voltage set higher than the limit voltage, it is determined that a connection failure has occurred in the transmission line. A connection failure detection method as a feature.

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