JP4978136B2 - Solid-state imaging device and solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device and a solid-state imaging device, and more particularly to a CCD (Charge-Coupled Device) type solid-state imaging device and a solid-state imaging device having two or more horizontal transfer registers.

  Conventionally, a CCD (Charge-Coupled Device) type solid-state imaging device has a plurality of light receiving elements arranged in parallel vertically and horizontally on a semiconductor substrate, a plurality of vertical transfer registers respectively adjacent to the light receiving elements, and this vertical transfer. A horizontal transfer register is provided adjacent to one end of the register, and charges accumulated in each light receiving element in response to light reception are transferred by the vertical transfer register and the horizontal transfer register.

  The horizontal transfer register is provided with an output amplifier circuit at the end, and this output amplifier circuit can output a voltage corresponding to the charge amount of the transferred charge, so that the charge amount information accumulated in each light receiving element can be output. Output as a voltage signal.

  In the solid-state imaging device provided with such a solid-state imaging device, since further enhancement of functionality is required, the solid-state imaging device used in the solid-state imaging device is required to have higher pixels and higher frame rate. Yes.

  In particular, when the number of pixels in a solid-state image sensor is increased, the frame rate decreases due to an increase in the number of light receiving elements formed on a semiconductor substrate, making it difficult to shorten the shooting interval, There is a risk that the handling of the solid-state imaging device may be lowered when the solid-state imaging device is used.

  Therefore, in recent years, in order to increase the number of pixels of the solid-state image pickup device and improve the frame rate, the solid-state image pickup device increases the drive frequency or multiplexes the output channels of signals output from the horizontal transfer register. Things have been done.

  When a plurality of output channels are used, a plurality of horizontal transfer registers may be provided. Specifically, as shown in FIG. 27, the first area is sandwiched between imaging regions 200 in which a plurality of light receiving elements 100 are arranged vertically and horizontally. The horizontal transfer register 300a and the second horizontal transfer register 300b are arranged to face each other (see, for example, Patent Document 1).

  Necessary number of vertical transfer registers arranged adjacent to the light receiving element 100 and transferring charges accumulated in the light receiving element 100 to the first horizontal transfer register 300a or the second horizontal transfer register 300b are arranged in the imaging region 200. In particular, in the solid-state imaging device shown in FIG. 10, a first vertical transfer register 400a that transfers charges to the first horizontal transfer register 300a and a second vertical transfer that transfers charges to the second horizontal transfer register 300b. The registers 400b are alternately arranged.

Thus, the frame rate can be improved by outputting signals from the first horizontal transfer register 300a and the second horizontal transfer register 300b. In FIG. 27, 500a is a first output amplifier circuit provided at the end of the first horizontal transfer register 300a, and 500b is a second output amplifier circuit provided at the end of the second horizontal transfer register 300b.
Japanese Patent Laid-Open No. 08-125158

  In the above-described solid-state imaging device, a color filter is mounted in most cases. The color filter is a single color filter disposed on each light receiving element. In the case of a so-called RGB primary color filter, the color filter is composed of three colors of red (R), green (G), and blue (B). The filter of any one of these three colors is arranged.

  In FIG. 27, the color of the filter provided on each light receiving element 100 is represented by “R”, “G”, and “B”, “R” indicates that the portion is a red filter, and “G” indicates that the portion is It is a green filter and “B” indicates that the portion is a blue filter. The color filter of FIG. 27 shows a color filter configuration in a Bayer array (checkered pattern array) widely used in general RGB primary color filters.

  Such a color filter is configured by repeating and arranging basic units in which filters of respective colors are arranged in a predetermined pattern. In particular, in a Bayer array color filter, a basic unit in a repetitive pattern is arranged on one diagonal. And two filters arranged in two columns and two rows, each consisting of one red filter and one blue filter arranged on the other diagonal.

  Therefore, when the first vertical transfer register and the second vertical transfer register are alternately provided as described above, the charge accumulated in one light receiving element among the charge amounts in the two green filters, The electric charges accumulated in the other light receiving element are transferred by the first horizontal transfer register and the second horizontal transfer register, respectively, and converted into signals and output separately.

  In this case, the output signal is affected by the process variation in the first output amplifier circuit provided in the first horizontal transfer register and the process variation in the second output amplifier circuit provided in the second horizontal transfer register. By adding each individually, there is a problem that an indefinite output characteristic difference occurs between the signal output from the first horizontal transfer register and the signal output from the second horizontal transfer register. The output characteristics include output characteristics of the amplifier circuit, output linearity, noise superimposed on the output, and the like. This characteristic is a superposition of the characteristics of the vertical transfer register, the horizontal transfer register, and the output circuit.

  For signals with different filter colors, it is possible to correct the output characteristic difference by the output characteristic correction process for each color by a separate circuit when generating the image data signal using these signals. In the case of the same color as in the filter, the same colors are visually compared at the same time, so that the difference in output characteristics is conspicuous and the image quality may be deteriorated.

Therefore, in the solid-state imaging device of the present invention, a plurality of light receiving elements provided in the imaging region of the semiconductor substrate, a plurality of color filters provided on the light receiving element for filtering with a predetermined color, and the light receiving elements are adjacent to each other. And a plurality of vertical transfer registers that transfer charges from the light receiving element to the horizontal transfer register, and a plurality of horizontal transfers that transfer the charges transferred from the vertical transfer registers and output signals based on the charges, respectively. In a solid-state imaging device having a transfer register, charges accumulated in the light receiving element based on light transmitted through the same color filter in the color filter are transferred by the same horizontal transfer register.
In the solid-state imaging device of the present invention, the color image sensor is disposed adjacent to the light receiving element, provided on one side of the light receiving elements arranged in a line in the vertical direction, and any one of the plurality of color filters. A first vertical transmission path from which charges accumulated in the light receiving element are read based on the light filtered by the color filter, and the light receiving element arranged adjacent to the light receiving element and arranged in a line in the vertical direction. The color filter having a color other than the color of the color filter provided on the light receiving element provided on the other side of the element and on the light receiving element in which the charge read out by the first vertical transmission path is accumulated among the color filters of the plurality of colors And a second vertical transmission path from which charges accumulated in the light receiving element are read out based on the light filtered by the light receiving element, and the receiving lines arranged in a line in the vertical direction. A channel stop provided between an element and the first vertical transmission line, and between the light receiving element arranged in a line in the vertical direction and the second vertical transmission line, and the channel stop includes the channel stop, The light receiving element from which charges are read by the first vertical transmission path is provided on the second vertical transmission path side, and the light receiving elements from which charges are read by the second vertical transmission path is provided on the first vertical transmission path side. The predetermined light receiving elements are connected to each other.

Furthermore, the solid-state imaging device of the present invention is also characterized by the following points.
(1) The color filter is configured by repeating and arranging basic units in which filters of respective colors are arranged in a predetermined pattern, and the basic unit is provided with two or more filters of the same color.
(2) The plurality of horizontal transfer registers are at least two horizontal transfer registers sandwiching the imaging region, and the plurality of vertical transfer registers are respectively connected to one horizontal transfer register, and the same color in the basic unit in the color filter The electric charge accumulated in the light receiving element filtered by the filter is read out to the same vertical transfer register.
(3) The basic unit is a Bayer array, and the same color is green.

In the solid-state imaging device of the present invention, a plurality of light receiving elements provided in the imaging region of the semiconductor substrate, a plurality of color filters provided on the light receiving element for filtering with a predetermined color, and the light receiving elements are adjacent to each other. And a plurality of vertical transfer registers that transfer charges from the light receiving element to the horizontal transfer register, and a plurality of horizontal transfers that transfer the charges transferred from the vertical transfer registers and output signals based on the charges, respectively. In a solid-state imaging device including a solid-state imaging device having a transfer register, the solid-state imaging device uses the same horizontal transfer register to store charges accumulated in the light receiving element based on light transmitted through the same color filter in the color filter. I decided to forward it.
Further, in the solid-state imaging device of the present invention, the color filter is disposed adjacent to the light receiving element and provided on one side of the light receiving elements arranged in a line in the vertical direction, and any one of the color filters of the plurality of colors A first vertical transmission path from which charges accumulated in the light receiving element are read based on the light filtered by the color filter, and the light receiving element arranged adjacent to the light receiving element and arranged in a line in the vertical direction. The color filter having a color other than the color of the color filter provided on the light receiving element provided on the other side of the element and on the light receiving element in which the charge read out by the first vertical transmission path is accumulated among the color filters of the plurality of colors And a second vertical transmission path from which charges accumulated in the light receiving element are read out based on the light filtered by the light receiving element, and the receiving lines arranged in a line in the vertical direction. A solid-state image sensor having a channel stop provided between the light receiving element and the second vertical transmission path arranged between the element and the first vertical transmission path and in a line in the vertical direction; The stop is provided on the second vertical transmission path side in the light receiving element from which charges are read out by the first vertical transmission path, and the first vertical transmission is performed in the light receiving element from which charges are read out by the second vertical transmission path. It is provided on the road side and is connected between the predetermined light receiving elements.

  According to the present invention, the charges stored in the light receiving elements based on the light transmitted through the filters of the same color in the color filters are transferred by the same horizontal transfer register and output as signals, so that the signals of the same color Can be prevented from being affected by the difference in the output characteristics of the horizontal transfer register.

  In the solid-state imaging device of the present invention and the solid-state imaging device including the solid-state imaging device, a light receiving element, a vertical transfer register, and a horizontal transfer register are formed at predetermined positions on the semiconductor substrate, and a plurality of color filters are formed on the semiconductor substrate A solid-state imaging device is configured by providing a color filter composed of the following. In particular, a plurality of horizontal transfer registers are provided to increase the frame rate.

  In particular, in the solid-state imaging device of the present invention, the charges accumulated in the light receiving element based on the light filtered by the same color filter in the color filter are transferred by the same horizontal transfer register and output as a signal. Is.

  Therefore, since the same color signal is generated by the same output amplifier circuit provided in the subsequent stage of each horizontal transfer register, it is possible in principle to prevent the influence of the difference in output characteristics between the same color signals.

  In addition, the plurality of horizontal transfer registers are at least two horizontal transfer registers sandwiching the imaging area, and the plurality of vertical transfer registers are connected to one horizontal transfer register, respectively, and the same color in the basic unit in the color filter By reading the electric charges accumulated in the light receiving element filtered by the filter in the same vertical transfer register, the electric charges can be transferred as they are in the same horizontal transfer register and output as signals.

  In the following, for convenience of explanation, “charges accumulated in the light receiving element based on light filtered by passing through the same color filter in the color filter” will be referred to as “signal charges”.

  When a predetermined image data signal is generated from this signal by eliminating the influence of the difference in output characteristics in the same color signal, the output amplifier circuit of each horizontal transfer register can be obtained only by gain correction processing such as white balance. Can be reliably corrected, and noise can be prevented from occurring in the image data signal.

  In addition, since correction signal processing for correction for correcting the difference in output characteristics for the same color, which has been conventionally required, can be eliminated, the manufacturing efficiency of the solid-state imaging device and the solid-state imaging device can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic block diagram of a solid-state imaging device A of the present embodiment. The solid-state imaging device A of this embodiment is a digital still camera called a so-called digital camera. The solid-state imaging device A is not limited to a digital still camera, and may be a digital video camera, a camera unit built in a mobile phone, or the like.

  FIG. 1 shows a solid-state imaging device 10 for imaging in the solid-state imaging device A and a timing generator 20 that generates a driving signal for driving the solid-state imaging device 10 at a predetermined timing. In addition, the solid-state imaging device A includes a power supply unit such as a battery, a storage unit that stores an image data signal generated by imaging, and a control unit that controls the entire solid-state imaging device A. The circuits constituting these circuits are separate circuits (chips other than the solid-state imaging device 10) in this figure, but may be provided on the same chip or may be provided by dividing functions into several chips. Note that the solid-state imaging device 10 of the present embodiment will be described as an interlaced CCD solid-state imaging device.

  The solid-state imaging device 10 is constituted by a semiconductor substrate, and on this semiconductor substrate, a plurality of light receiving elements 11 made of photodiodes arranged in a row at a predetermined interval and an imaging region 12 in which the light receiving elements 11 are arranged are arranged. A first horizontal transfer register 13a and a second horizontal transfer register 13b which are arranged in a sandwiched manner, a first vertical transfer register 14a which is arranged on one side of the light receiving elements 11 arranged in a line in the vertical direction, and a first horizontal transfer register 14a which is arranged on the other side. Two vertical transfer registers 14b are provided.

  Further, a color filter is provided on the semiconductor substrate. In the present embodiment, the color filter is a so-called 2 × 2 primary color filter having a Bayer arrangement, and the green filters are arranged in a checkered pattern. For convenience of explanation, in FIG. 1, the color of the filter disposed on each light receiving element 11 is indicated by “R”, “G”, and “B”, and “R” is a red filter, “G” indicates that a green filter is provided, and “B” indicates that a blue filter is provided. In this embodiment, a region surrounded by a two-dot chain rectangular frame indicated by U in FIG. 1 is a basic unit of a color filter.

  In this embodiment, the horizontal transfer uses a well-known two-phase driving method, and the two phases of the driving signal are indicated by a first horizontal driving signal Hφ1 and a second horizontal driving signal Hφ2, respectively. Transfer is performed by supplying and applying to both the transfer register 13a and the second horizontal transfer register 13b.

  In particular, the first horizontal transfer register 13a and the second horizontal transfer register 13b are disposed to face each other across the imaging region 12 in which the light receiving element 11 is disposed, and the first horizontal transfer register 13a and the second horizontal transfer register 13b are input from the timing generator 20. By the drive signal Hφ1 and the second horizontal drive signal Hφ2, the first horizontal transfer register 13a transfers signal charges from left to right on the drawing of FIG. 1, and the second horizontal transfer register 13b is shown in FIG. In the drawing, signal charges are transferred from right to left.

  A first output amplifier circuit 15a and a second output amplifier circuit 15b are provided at the ends of the first horizontal transfer register 13a and the second horizontal transfer register 13b, respectively. The first output amplifier circuit 15a and the second output amplifier circuit 15b are provided. Thus, a required voltage signal is generated and output based on the transferred signal charge.

  In the present embodiment, the first horizontal transfer register 13a including the first output amplifier circuit 15a is described, and the second horizontal transfer register 13b including the second output amplifier circuit 15b is described.

  The first vertical transfer register 14a is provided on one side of the light receiving elements 11 arranged in a line in the vertical direction in FIG. 1, and the second vertical transfer register 14b is provided on the other side, and the light receiving elements 11 are provided in the imaging region 12. The first vertical transfer registers 14a and the second vertical transfer registers 14b are alternately arranged with the sandwiched therebetween.

  The first vertical transfer register 14a and the second vertical transfer register 14b have a first vertical drive signal Vφ1, a second vertical drive signal Vφ2, a third vertical drive signal Vφ3, and a fourth vertical drive input from the timing generator 20, respectively. The first vertical transfer register 14a is driven by the signal Vφ4 and transfers the signal charge from the bottom to the top in the drawing of FIG. 1, and reads the signal charge to the first horizontal transfer register 13a. The two vertical transfer registers 14b transfer signal charges from the top to the bottom in the drawing of FIG. 1, and read the signal charges to the second horizontal transfer register 13b.

  When taking out image data picked up by the solid-state image pickup device 10 configured as described above, signal charges are read out from the odd-numbered light receiving elements 11 in the image pickup region 12 shown in FIG. As a second field, signal charges are read out from the light-receiving elements 11 in the even-numbered columns of the imaging region 12 shown in FIG.

  Here, in the present embodiment, as shown in FIG. 2A, when the signal charge is read in the first field, a green filter is provided in the odd-numbered light receiving elements 11 in the imaging region 12. The signal charge of the light receiving element 11 is read to the first vertical transfer register 14a, and the signal charge of the light receiving element 11 provided with the red filter is read to the second vertical transfer register 14b.

  The signal charges read to the first vertical transfer register 14a are transferred to the first horizontal transfer register 13a and output from the first horizontal transfer register 13a as a first green signal. The signal charge read to the second vertical transfer register 14b is transferred to the second horizontal transfer register 13b and is output as a red signal from the second horizontal transfer register 13b.

  Next, as shown in FIG. 2B, when reading out the signal charge in the second field, the light receiving element 11 provided with a green filter in the light receiving elements 11 in the even-numbered columns of the imaging region 12. The signal charge is read to the first vertical transfer register 14a, and the signal charge of the light receiving element 11 provided with the blue filter is read to the second vertical transfer register 14b.

  The signal charges read to the first vertical transfer register 14a are transferred to the first horizontal transfer register 13a and output from the first horizontal transfer register 13a as a second green signal. The signal charge read to the second vertical transfer register 14b is transferred to the second horizontal transfer register 13b and is output as a blue signal from the second horizontal transfer register 13b.

  As described above, the first green signal read in the first field and the second green signal read in the second field are transferred only by the first vertical transfer register 14a, respectively, and are transferred to the first horizontal transfer register 13a. , The first green signal and the second green signal have no output characteristic difference, and a high-quality image data signal can be generated.

  In addition, the signal charges in the light receiving elements filtered by the same color filter in the basic unit are read and transferred to the same vertical transfer register, so that the transfer can be performed in the same horizontal transfer register as it is. The horizontal transfer register can be easily designed.

  As described above, in the first field, the signal charge of the light receiving element 11 provided with the green filter is read to the first vertical transfer register 14a, and the signal charge of the light receiving element 11 provided with the red filter is obtained. In addition to reading to the second vertical transfer register 14b, in the second field, the signal charge of the light receiving element 11 provided with the green filter is read to the first vertical transfer register 14a, and the light receiving element 11 provided with the blue filter. In order to read out the signal charges to the second vertical transfer register 14b, each light receiving element 11 adjusts the reading direction of the signal charges as shown in FIG.

  In the light receiving element 11 provided with the green filter, the channel stop 16 is provided on the second vertical transfer register 14b side opposite to the first vertical transfer register 14a, and in the light receiving element 11 provided with the red and blue filters, A channel stop 16 is provided on the side of the first vertical transfer register 14a opposite to the second vertical transfer register 14b, and the movement direction of the signal charge is regulated by the channel stop 16 so that a predetermined first vertical transfer register 14a or first 2 The signal charge is read out to the vertical transfer register 14b.

  As shown in FIG. 3, channel stops 16 provided alternately at both ends of the vertical transfer register are connected between predetermined pixels while being arranged alternately so as not to be electrically isolated. I try to fulfill the stop function. That is, in the channel stop 16, the potential difference between the edge and the center of the imaging region is suppressed by applying a predetermined potential (currently the GND potential is widely used), and the holes generated in the light receiving element or the vertical transfer register are suppressed. Thus, functions such as noise suppression by discarding to a predetermined potential are not impaired.

  In FIG. 3, in the first vertical transfer register 14a and the second vertical transfer register 14b, “1”, “2”, “3”, and “4” are the first vertical drive signal Vφ1, the second vertical drive signal Vφ2, and the first 3 shows each register to which a bias of 3 vertical drive signal Vφ3 and 4th vertical drive signal Vφ4 is applied. In the first field, reading is performed by applying a read voltage to the electrode of the register portion of “1”. Signal potential is read out from the light receiving element 11 provided with the green filter to the first vertical transfer register 14a, and the second vertical is output from the light receiving element 11 provided with the red filter. The signal charge is read out to the transfer register 14b, and in the second field, the read potential is applied by applying a read voltage to the electrode of the register portion of “3”. Thus, the signal charge is read from the light receiving element 11 provided with the green filter to the first vertical transfer register 14a, and also from the light receiving element 11 provided with the blue filter to the second vertical transfer register 14b. The signal charge is read out.

  The electrodes to which the first vertical drive signal Vφ1, the second vertical drive signal Vφ2, the third vertical drive signal Vφ3, and the fourth vertical drive signal Vφ4 are respectively input are formed as follows.

  As shown in FIG. 4A, first, on the semiconductor substrate, the second electrode 22 is provided so as to cover the “2” region of the vertical transfer register, and the “4” region of the vertical transfer register is covered. A fourth electrode 24 is provided as described above. Particularly, as shown in FIG. 4A, the second electrode 22 and the fourth electrode 24 are each formed in a linear pattern and connected in the horizontal direction, and are applied from a bus line provided outside a pixel region (not shown). The vertical drive signal is applied in the horizontal direction in the figure.

  Next, as shown in FIG. 4B, the first electrode 21 is provided on the second electrode 22 in a straight line like the second electrode 22, and the first electrode 21 is provided on the fourth electrode 24. Similar to the four electrodes 24, a third electrode 23 is provided in a straight line.

  In particular, the first electrode 21 has a linear shape narrower than that of the second electrode 22 and is provided with a protruding portion that protrudes in the orthogonal direction and covers the area “1” of the vertical transfer register. The third electrode 23 has a linear shape narrower than that of the fourth electrode 24, and is provided with a protruding portion that protrudes in the orthogonal direction and covers the area “3” of the vertical transfer register.

  On the first electrode 21, the second electrode 22, the third electrode 23, and the fourth electrode 24, semiconductor layers to be the first vertical transfer register 14a and the second vertical transfer register 14b are formed.

  In the above-described embodiment, the signal charge transfer direction of the first horizontal transfer register 13a is opposite to the signal charge transfer direction of the second horizontal transfer register 13b. However, as shown in FIG. The signal charges may be transferred in the same direction by the first horizontal transfer register 13a and the second horizontal transfer register 13b.

  In the embodiment described above, the first horizontal transfer register 13a and the second horizontal transfer register 13b are provided in parallel with the horizontal direction in the drawing as shown in FIG. 1, and the first vertical transfer register 14a and the second vertical transfer register are provided. The register 14b is provided in parallel with the horizontal direction in the drawing as shown in FIG. 1, but the first horizontal transfer register 13a 'and the second horizontal transfer register 13b' are sandwiched between the imaging region 12 as shown in FIG. The first vertical transfer register 14a ′ and the second vertical transfer register 14b ′ may be provided in parallel with the vertical direction in the drawing.

  The term “horizontal” in the first horizontal transfer registers 13a and 13a ′ and the second horizontal transfer registers 13b and 13b ′, and the “vertical” in the first vertical transfer registers 14A and 14a ′ and the second vertical transfer registers 14b and 14b ′. Is used to distinguish the first horizontal transfer registers 13a and 13a ′ and the second horizontal transfer registers 13b and 13b ′ from the first vertical transfer registers 14A and 14a ′ and the second vertical transfer registers 14b and 14b ′. It is a term that is only used idiomatically, and does not limit the directionality.

  In the above-described embodiment, the color filter is a 2 × 2 primary color filter, but is not limited to the 2 × 2 primary color filter. Other than the primary color filter, cyan “Cy”, yellow “Ye”, magenta “Mg”, A complementary color filter using green “G” may be used. Further, the arrangement of the filters is not limited to 2 × 2, but may be 2 × 4.

  FIG. 7 shows the readout direction of the signal charges to the first vertical transfer register 14a and the second vertical transfer register 14b when the 2 × 4 complementary color filter is used, and FIG. 7A shows the first field. FIG. 7B shows a read state in the second field. In the first field, a readout signal is applied to the first electrode 21, and in the second field, a readout signal is applied to the third electrode 23 to read out the signal charge from the predetermined light receiving element 11. Is going.

  FIG. 8 shows the readout direction of the signal charges to the first vertical transfer register 14a and the second vertical transfer register 14b in the case of a modification of the 2 × 4 complementary color filter in FIG. 7, and FIG. The read state in the first field, and FIG. 8B shows the read state in the second field.

  The 2 × 4 complementary color filter in FIG. 8 is obtained by partially changing the arrangement of cyan “Cy” and yellow “Ye” in the 2 × 4 complementary color filter in FIG.

  FIG. 9 shows the readout direction of the signal charge to the first vertical transfer register 14a and the second vertical transfer register 14b when the 2 × 8 complementary color filter is used, and FIG. 9A shows the first field. FIG. 9B shows a read state in the second field. In the first field, a readout signal is applied to the first electrode 21, and in the second field, a readout signal is applied to the third electrode 23 to read out the signal charge from the predetermined light receiving element 11. Is going.

  The first horizontal transfer registers 13a and 13a ′ and the second horizontal transfer registers 13b and 13b ′ are not limited to two, and two or more horizontal transfer registers may be provided as necessary. Specifically, as shown in FIG. 10, a first horizontal transfer register 33-1 and a second horizontal transfer register 33-2 are disposed on one side edge across an imaging region 32 in which a plurality of light receiving elements 31 are arranged vertically and horizontally. And the third horizontal transfer register 33-3 and the fourth horizontal transfer register 33-4 may be provided on the other side edge. That is, so-called 4-channel output. In addition, two or more may be provided instead of two.

  By thus doubling the number of horizontal transfer registers, the transfer efficiency in the horizontal transfer registers can be greatly improved, and the number of pixels at a high frame rate can be increased. In FIG. 10, 34-1 is a first vertical transfer register and 34-2 is a second vertical transfer register, which are alternately arranged between rows of light receiving elements 31 arranged in a row in the vertical direction. In FIG. 10, 35-1 is a first output amplifier circuit provided at the end of the first horizontal transfer register 33-1, and 35-2 is a second output amplifier provided at the end of the second horizontal transfer register 33-2. The circuit 35-3 is a third output amplifier circuit provided at the end of the third horizontal transfer register 33-3, and 35-4 is a fourth output amplifier circuit provided at the end of the fourth horizontal transfer register 33-4.

  However, as shown in FIG. 10, when two horizontal transfer registers are provided on the side edge of the imaging region 32, another new problem arises. That is, as shown in FIG. 10, in the first field, the signal charge is read from the light receiving element 31 provided with the green filter to the first vertical transfer register 34-1 and the red filter is provided. The signal charge is read from the light receiving element 31 to the second vertical transfer register 34-2, and the signal is sent from the first vertical transfer register 34-1 to the third horizontal transfer register 33-3 and the fourth horizontal transfer register 33-4. When the signal charge is transferred from the second vertical transfer register 34-2 to the first horizontal transfer register 33-1 and the second horizontal transfer register 33-2, the first output amplifier circuit 35- 1 and the second output amplifier circuit 35-2 output a signal based on the signal charge in the light receiving element 31 provided with a red filter, and a third output amplifier circuit 35-3 and a fourth output amplifier circuit 35-4. To the light receiving element 31 provided with a green filter. Becomes a signal based on use charge is output, it has become possible to output the same color signal from the two horizontal transfer registers. The second field has the same problem.

  Therefore, as described above, in the first field and the second field, signal charges are not read out from the pixels along the extending direction of the vertical transfer register, but as shown in FIG. When two horizontal transfer registers are provided across the two, a signal of the same color is output from each horizontal transfer register by reading in units of two pixels along the extending direction of the vertical transfer register in each field. I decided to let them.

  In FIG. 10, since the color filter is a 2 × 2 primary color filter, the basic unit is provided with two green filters, and in the following, as shown in FIG. The green filter adjacent in the left-right direction is labeled “Gb”, and the green filter adjacent in the left-right direction in FIG. 11 of the red filter is labeled “Gr”.

  For convenience of explanation, the signal charge in the light receiving element 31 provided with the blue filter indicated by “B” is referred to as “B signal charge”, and the red filter indicated by “R” is provided. The signal charge in the light receiving element 31 is called “R signal charge”, and the signal charge in the light receiving element 31 provided with the green filter indicated by “Gb” is called “Gb signal charge”. The signal charge in the light receiving element 31 provided with the green filter indicated by “Gr” is referred to as “Gr signal charge”.

  In order to output a signal of the same color from each horizontal transfer register, the Gb signal charge, the Gr signal charge, the B signal charge, and the R signal charge are respectively output in the first field and the second field. It is necessary to read out to each vertical transfer register, and in order to perform this reading, the first electrode 21, the second electrode 22, the third electrode 23, and the fourth electrode 24 described in FIG. 12, every other first electrode 21 is a main first electrode 21a, and the first electrodes 21 other than the main first electrode 21a are sub-first electrodes 21b, and every third third electrode 21a. The electrode 23 is the main third electrode 23a and the third electrode 23 other than the main third electrode 23a is the sub third electrode 23b. In the first field, the potentials of the main first electrode 21a and the main third electrode 23a are simultaneously " By setting “High”, the receiver provided with a filter indicated by white letters in FIG. The signal charge is read from the element 31, and the signal charges are read from the remaining light receiving elements 31 by simultaneously setting the potentials of the sub first electrode 21b and the sub third electrode 23b to “High” in the second field. Considered to do.

  Thus, in the case of FIG. 11, the B signal charge is read by the first horizontal transfer register 33-1, the R signal charge is read by the second horizontal transfer register 33-2, and the third horizontal transfer register is read. The Gb signal charge can be read by 33-3, the Gr signal charge can be read by the fourth horizontal transfer register 33-4, and the same color signal should be output from the same horizontal transfer register.

  However, in this case, there is a possibility that proper operation cannot actually be performed due to the following problems.

  That is, the main first electrode 21a, the sub first electrode 21b, the second electrode 22, the main third electrode 23a, the sub third electrode 23b, and the fourth electrode 24 are shown in the timing chart of FIG. By the first vertical drive signal Vφ1a, the sub first vertical drive signal Vφ1b, the second vertical drive signal Vφ2, the main third vertical drive signal Vφ3a, the sub third vertical drive signal Vφ3b, and the fourth vertical drive signal Vφ4 When each bias is applied, the first vertical transfer register 34-1 transfers the Gb signal charge and the Gr signal charge as shown in FIG.

  Here, in FIG. 14, for convenience of explanation, among the registers in the first vertical transfer register 34-1 and the second vertical transfer register 34-2, a register to which a bias based on the main first vertical drive signal Vφ1a is applied is shown. V1a is a register to which a bias based on the sub first vertical drive signal Vφ1b is applied, V1b is a register to which a bias is applied based on the second vertical drive signal Vφ2, and a bias is applied based on the main third vertical drive signal Vφ3a. The register to be applied with a bias based on the sub-third vertical drive signal Vφ3b is denoted as V3b, and the register to which a bias potential based on the fourth vertical drive signal Vφ4 is applied is denoted as V4. Therefore, the first vertical transfer register 34-1 follows V4 → V1a → V2 → V3a → V4 → V1b → V2 → V3b → V4 → V1a → V2 → V3a →. The registers are arranged in order, and the second vertical transfer register 34-2 is V1a → V2 → V3b → V4 → V1b → V2 → V3a → V4 → V1a → V2 → V3b → along the signal charge transfer direction. Registers are arranged in the order of V4 →.

  At this time, in the second vertical transfer register 34-2, as shown in FIG. 15, the R signal charge and the B signal charge are transferred, and the color mixture of the R signal charge and the B signal charge is performed at the timing t3. Therefore, it is difficult to transfer signal charges normally.

  That is, when the transfer of the Gb signal charge and the Gr signal charge and the transfer of the R signal charge and the B signal charge are performed by four-phase drive signals, the gates for separating the signals are different from each other. In addition, at least one of the colors is mixed.

  Therefore, among the vertical drive signals, as shown in the timing chart of FIG. 16, color generation occurs using the main first vertical drive signal Vφ1a, the main third vertical drive signal Vφ3a, and the fourth vertical drive signal Vφ4. It was decided to apply a bias that forms a barrier to prevent this. That is, in the present embodiment, the occurrence of color mixture is prevented by adjusting the bias at the timing t2 in the timing chart of FIG.

  In particular, the register V1a to which the main first vertical drive signal Vφ1a is applied and the register V3a to which the main third vertical drive signal Vφ3a is applied must be provided across the register V4 to which the fourth vertical drive signal Vφ4 is applied. In this embodiment, an electrode to which each vertical drive signal is input is formed as follows.

  That is, as shown in FIG. 17, first, on the semiconductor substrate, the second electrode 42 covering the “V2” region of the vertical transfer register and the fourth electrode covering the “V4” region of the vertical transfer register are provided. 44 is provided. In particular, the second electrode 42 and the fourth electrode 44 are each formed in a straight line and have a pattern connected in the horizontal direction, and are further provided with a protrusion 45 that covers a part of the register adjacent to each other in the transfer direction.

  Next, as shown in FIG. 18, on the fourth electrode 44, a linear portion that is linear like the fourth electrode 44, and a protruding portion that covers the region of “V3a” of the vertical transfer register from this linear portion And the sub third electrodes 43b provided with protrusions that cover the “V3b” region of the vertical transfer register from the straight line portion.

  Next, as shown in FIG. 19, on the second electrode 42, a linear portion that is linear like the second electrode 42, and a protruding portion that covers the region of “V1a” of the vertical transfer register from this linear portion The main first electrodes 41a provided with the first and second sub-electrodes 41b provided with protrusions that cover the “V1b” region of the vertical transfer register from the straight line portions are alternately provided.

  In particular, the main first electrode 41a is provided with a protruding portion that crosses over the main third electrode 43a and covers the region "V1a", thereby sandwiching the main first electrode 41a across the register V4 to which the fourth vertical drive signal Vφ4 is applied. A register V1a to which one vertical drive signal Vφ1a is applied and a register V3a to which the main third vertical drive signal Vφ3a is applied are arranged.

  17 to 19 are explanatory diagrams for explaining the arrangement of the main first electrode 41a, the sub first electrode 41b, the second electrode 42, the main third electrode 43a, the sub third electrode 43b, and the fourth electrode 44. However, it does not indicate the relationship between the wiring widths, and the wiring widths constituting each electrode may be appropriate. Of course, in the present embodiment, the lowermost wiring layer in which the second electrode 42 and the fourth electrode 44 are provided, and the intermediate layer wiring in which the main third electrode 43a and the sub third electrode 43b are provided. An insulating layer is provided between each layer and the uppermost wiring layer on which the main first electrode 41a and the sub first electrode 41b are provided, and the order of stacking the wiring layers is limited to this. Instead, they may be laminated in an appropriate order.

  FIG. 20 shows an operation state of the first vertical transfer register 34-1 based on the timing chart shown in FIG. 16 in the case of such a configuration, and FIG. 21 shows an operation state of the second vertical transfer register 34-2. It is clear that color mixing is prevented at the timing of t2.

  As another embodiment, each register is not composed of three layers of electrodes as described above, but each register is composed of two layers of electrodes, and color mixing is performed by adjusting the register arrangement and transfer timing. It is also possible to prevent the occurrence.

  Here, in this embodiment, instead of providing the main third electrode 23a and the sub third electrode 23b described above, the second electrode among the second electrode and the fourth electrode 54 provided alternately as shown in FIG. The main second electrodes 52a and the sub second electrodes 52b are alternately arranged.

  Accordingly, the vertical transfer register includes a register V1a to which a bias based on the main first vertical drive signal Vφ1a is applied, a register V1b to which a bias is applied based on the sub first vertical drive signal Vφ1b, and a main second vertical drive signal Vφ2a. A register V2a to which a bias is applied based on the above, a register V2b to which a bias is applied based on the sub-second vertical drive signal Vφ2b, a register V3 to which a bias is applied based on the third vertical drive signal Vφ3, and a fourth vertical drive The first vertical transfer register is composed of V4 → V1a → V2a → V3 → V4 → V1b → V2b → along the signal charge transfer direction. Registers are arranged in the order of V3-> V4-> V1a-> V2a-> V3-> ... The second vertical transfer register is V4-> V1a-> V2a-> V3-> V4-> V1b along the signal charge transfer direction → V2b → V3 → V Registers are arranged in the order of 4 → V1a → V2a → V3 →.

  As shown in FIG. 22, first, a fourth electrode 54 is provided on the semiconductor substrate so as to cover the “V4” region of the vertical transfer register, and the main electrode so as to cover the “V2a” region of the vertical transfer register. The second electrode 52a is provided, and further, the sub second electrode 52b is provided so as to cover the "V2b" region of the direct transfer register. In particular, the main second electrode 52a, the sub second electrode 52b, and the fourth electrode 54 are provided. Are respectively formed in a straight line and connected in the horizontal direction, and are further provided with projecting portions 55 projecting in the transfer direction of the vertical transfer register.

  Next, as shown in FIG. 23, on the fourth electrode 54, a straight line portion that is linear like the fourth electrode 54, and a protruding portion that covers the “V3” region of the vertical transfer register from this straight line portion A third electrode 53 is provided.

  Further, on the main second electrode 52a, a linear portion that is linear like the main second electrode 52a and a protrusion that covers the “V1a” region of the vertical transfer register from the straight portion are provided. 1 electrode 51a is provided, and on the sub-second electrode 52b, a straight line portion that is linear like the sub-second electrode 52b and a projecting portion that covers the area of “V1b” of the vertical transfer register from the straight line portion. The provided sub first electrode 41b is provided.

  FIG. 22 and FIG. 23 explain the arrangement of the main first electrode 51a, the sub first electrode 51b, the main second electrode 52a, the sub second electrode 52b, the third electrode 53, and the fourth electrode 54. It is a figure and does not show the relationship of the wiring width, and the wiring width constituting each electrode may be appropriate. Of course, in the present embodiment, the wiring layer in which the main second electrode 52a, the sub second electrode 52b, and the fourth electrode 44 are provided, the third electrode 43, the main first electrode 41a, and the sub first electrode 41b. An insulating layer is provided between the wiring layer and the wiring layer.

  Here, the length of the protruding portion 55 provided on the main second electrode 52a, the sub second electrode 52b, and the fourth electrode 54, and the protruding portion of the third electrode 53 from the side edge of the fourth electrode 54 are extended. The length of the protrusion of the main first electrode 51a from the side edge of the main second electrode 52a, the length of the protrusion of the sub second electrode 52b from the side edge of the sub second electrode 52b It is desirable that each of them be equal.

  FIG. 25 shows the operation state of the first vertical transfer register based on the timing chart shown in FIG. 24, and FIG. 26 shows the operation state of the second vertical transfer register based on the timing chart shown in FIG. It is clear that color mixing is prevented at the timing of t2.

  That is, in the present embodiment, in the first field, reading is performed by V1a and V2a of the vertical transfer register. In this case, if a read voltage is applied simultaneously to V1a of the vertical transfer register and V2a of the vertical transfer register, Since the separation of the R signal charge and the B signal charge and the separation of the Gb signal charge and the Gr signal charge cannot be performed by the vertical transfer register V2a, color mixing occurs.

  Therefore, first, a read voltage is applied to V1a of the vertical transfer register at the timing of t1, the Gb signal charge is read to the first vertical transfer register, and the R signal charge is read to the second vertical transfer register. At this time, by applying no read voltage to V1b of the vertical transfer register, the charge for Gb signal and the charge for R signal located next to V1b of the vertical transfer register are not read.

  Next, a vertical transfer cycle of four layers is performed, and the Gb signal charge read to the first vertical transfer register is transferred to the gates of V1b and V2b of the vertical transfer register and read to the second vertical transfer register. The outputted R signal charge is transferred under the gates of V1b and V2b of the vertical transfer register.

  In this state, a read voltage is applied to V2a of the vertical transfer register, the Gr signal charge is read to the first vertical transfer register, and the B signal charge is read to the second vertical transfer register. At this time, that is, at the timing of t1, as shown in the timing chart of FIG. 24, the third vertical drive signal Vφ3 applied to V3 of the vertical transfer register and the fourth vertical drive signal Vφ4 applied to V4 of the vertical transfer register are set. By setting “Low”, it is possible to prevent color mixing of the Gb signal charge and the Gr signal charge in the first vertical transfer register, and the R signal charge and the B signal charge in the second vertical transfer register. Can be prevented from occurring.

  After each signal charge is read in this way, each signal charge is transferred to a required horizontal transfer register by the first vertical transfer register or the second vertical transfer register. Therefore, a signal generated from signal charges based on filters of the same color can be output from the same horizontal transfer register while preventing color mixture of signal charges.

  In the second field, reading is performed by V1b and V2b of the vertical transfer register, and the same horizontal transfer register is used as a filter of the same color while preventing color mixture of signal charges in the same manner as described above. A signal generated from the signal charge based thereon can be output.

It is a schematic block diagram of the solid-state imaging device concerning this embodiment. It is explanatory drawing of the solid-state image sensor concerning this embodiment, Comprising: (a) is the read-out state of the 1st field, (b) is the read-out state of the 2nd field. It is explanatory drawing of the solid-state image sensor which concerns on this embodiment, Comprising: (a) is the read-out state of the 1st field, (b) is the read-out state of the 2nd field. It is explanatory drawing of the electrode formation method for vertical transfer. It is explanatory drawing of the modification of the solid-state image sensor which concerns on this embodiment. It is explanatory drawing of the modification of the solid-state image sensor which concerns on this embodiment. It is explanatory drawing in the case of a 2x4 complementary color filter. It is explanatory drawing in the case of a 2x4 complementary color filter. It is explanatory drawing in the case of a 2x8 complementary color filter. It is explanatory drawing of the modification of the solid-state image sensor which concerns on this embodiment. It is explanatory drawing of the modification of the solid-state image sensor which concerns on this embodiment. It is explanatory drawing of the electrode formation for the vertical transfer in the solid-state image sensor of a modification. It is a timing chart for the vertical transfer in the solid-state image sensor of a modification. It is a potential diagram of the 1st vertical transfer register in the solid-state image sensor of a modification. It is a potential diagram of the 2nd vertical transfer register in the solid-state image sensing device of a modification. It is a timing chart for the vertical transfer in the solid-state image sensor of a modification. It is explanatory drawing of the electrode formation for the vertical transfer in the solid-state image sensor of a modification. It is explanatory drawing of the electrode formation for the vertical transfer in the solid-state image sensor of a modification. It is explanatory drawing of the electrode formation for the vertical transfer in the solid-state image sensor of a modification. It is a potential diagram of the 1st vertical transfer register in the solid-state image sensor of a modification. It is a potential diagram of the 2nd vertical transfer register in the solid-state image sensing device of a modification. It is explanatory drawing of the electrode formation for the vertical transfer in the solid-state image sensor of a modification. It is explanatory drawing of the electrode formation for the vertical transfer in the solid-state image sensor of a modification. It is a timing chart for the vertical transfer in the solid-state image sensor of a modification. It is a potential diagram of the 1st vertical transfer register in the solid-state image sensor of a modification. It is a potential diagram of the 2nd vertical transfer register in the solid-state image sensing device of a modification. It is explanatory drawing of the conventional solid-state image sensor.

Explanation of symbols

A Solid-state imaging device
10 Solid-state image sensor
20 Timing generator
11 Light receiving element
12 Imaging area
13a First horizontal transfer register
13b Second horizontal transfer register
14a First vertical transfer register
14b Second vertical transfer register
15a First output amplifier circuit
15b Second output amplifier circuit
16 channel stop

Claims (7)

A plurality of light receiving elements provided in an imaging region of the semiconductor substrate;
A plurality of color filters that are provided on the light receiving element and perform filtering by a predetermined color;
Light that is disposed adjacent to the light receiving element and provided on one side of the light receiving elements arranged in a line in the vertical direction and filtered by the color filter of any one of the color filters. A first vertical transmission path from which charges accumulated in the light receiving element are read out,
Located adjacent to the light receiving element and provided on the other side of the light receiving elements arranged in a line in the vertical direction, out of the color filters of the plurality of colors, the charge read out by the first vertical transmission path is accumulated. A second vertical transmission path from which charges accumulated in the light receiving element are read based on light filtered by the color filter of a color other than the color filter provided on the light receiving element;
A channel stop provided between the light receiving elements arranged in a line in the vertical direction and the first vertical transmission path, and between the light receiving elements arranged in a line in the vertical direction and the second vertical transmission path; I have a,
The channel stop is
The light receiving element from which charges are read by the first vertical transmission path is provided on the second vertical transmission path side, and the light receiving elements from which charges are read by the second vertical transmission path is provided on the first vertical transmission path side. A solid-state imaging device connected between the predetermined light receiving elements. A plurality of horizontal transmission lines connected to the first vertical transmission line or the second vertical transmission line;
The solid-state imaging device according to claim 1 , wherein a signal based on the electric charge accumulated in the light receiving element based on light transmitted through the same color filter in the color filter is output on the same horizontal transmission path. . The solid-state imaging device according to claim 1 or 2 , wherein the transmission path is a transfer register that transfers charges . The color filter is configured to constructed by arranging Shi Kurikae basic unit of each color filter is arranged in a predetermined pattern, according to claim 1 in the basic unit, characterized in that a same color filter two or more The solid-state imaging device according to any one of 3 . The plurality of horizontal transmission paths are at least two horizontal transmission paths sandwiching the imaging region,
Each of the first vertical transmission path and the second vertical transmission path is connected to one horizontal transmission path ;
5. The solid-state imaging according to claim 4 , wherein electrical charges accumulated in the light receiving elements filtered by the filters of the same color in the basic unit in the color filter are read out to the same vertical transmission path. 6. element. The solid-state imaging device according to claim 4, wherein the basic unit is a Bayer array, and the same color is green. A plurality of light receiving elements provided in an imaging region of the semiconductor substrate;
A plurality of color filters that are provided on the light receiving element and perform filtering by a predetermined color;
Light that is disposed adjacent to the light receiving element and provided on one side of the light receiving elements arranged in a line in the vertical direction and filtered by the color filter of any one of the color filters. A first vertical transmission path from which charges accumulated in the light receiving element are read out,
Located adjacent to the light receiving element and provided on the other side of the light receiving elements arranged in a line in the vertical direction, out of the color filters of the plurality of colors, the charge read out by the first vertical transmission path is accumulated. A second vertical transmission path from which charges accumulated in the light receiving element are read based on light filtered by the color filter of a color other than the color filter provided on the light receiving element;
A channel stop provided between the light receiving elements arranged in a line in the vertical direction and the first vertical transmission path, and between the light receiving elements arranged in a line in the vertical direction and the second vertical transmission path; In a solid-state imaging device including a solid-state imaging device having:
The channel stop is
The light receiving element from which charges are read by the first vertical transmission path is provided on the second vertical transmission path side, and the light receiving elements from which charges are read by the second vertical transmission path is provided on the first vertical transmission path side. A solid-state imaging device connected between the predetermined light receiving elements .

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