JP4978373B2 - Programmable controller and its CPU module - Google Patents

Description

  The present invention relates to a programmable controller and its CPU module.

Prior art will be described with reference to FIGS.
A programmable controller (hereinafter referred to as a PLC) executes an application described in a program language standardized by, for example, IEC61131-3. It is generally known that an application can have multiple levels of tasks (multitask) depending on execution priority. FIG. 18 shows the state of this multitask execution.

  In the example shown in FIG. 18, there are three types, a 0-level task, a 1-level task, and a default task, which have a relationship of “0-level task> 1-level task> default task” (that is, the 0-level task has the highest execution priority). high).

  In the illustrated example, the default task is normally executed, but the execution of the default task is interrupted every time the execution timing of the 0 level task (2 ms cycle) or the execution timing of the 1 level task (5 ms cycle) A 0 level task or a 1 level task is executed. Although not shown in the figure, when the execution timing of the 0 level task is reached during the execution of the 1 level task, the execution of the 1 level task is interrupted and the 0 level task is executed.

FIG. 19 shows an example of the internal and external configurations of a conventional PLC.
In the PLC configuration example shown in FIG. 19, a plurality of I / O modules 104 and a plurality of CPU modules 110 are connected to the I / O bus 103 and communicate with each other. The plurality of CPU modules 110 are also connected to the shared memory bus 102, and each CPU module 110 accesses the shared memory 101 via the shared memory bus 102.

Each CPU module 110 includes a microcomputer 111, a ROM 112, a RAM 113, a bus interface 114, an I / O interface 115, and an RDY control unit 116.
The I / O interface 115 is connected to the I / O bus 103 and performs communication control with other modules. The bus interface 114 is connected to the shared memory bus 102 and controls access to the shared memory 101.

  The microcomputer 111 reads an application program stored in the RAM 113 or the ROM 112 and executes instructions. If shared memory access processing occurs during execution of this application program, the application calls up system software. This system software is firmware created in advance by the PLC manufacturer, and executes shared memory access processing. On the other hand, the application program is created by the customer. On the customer side, when creating a new application program, for example, it is not necessary to describe the process of accessing the shared memory step by step, and it is only necessary to call the system software prepared in advance. That is, the system software is like a subroutine called by an application.

  The system software executes the shared memory access process via the bus interface 114. However, until the process is completed, the system software enters a WAIT state for an RDY signal described later and does not return to the application. For this reason, there arises a problem that the task cannot be executed even when the upper level task is executed. Details will be described later.

The execution of the shared memory access process will be described below.
The system software of the microcomputer 111 accesses the shared memory 101 on the shared memory bus 102 via the bus interface 114.

  The shared memory 101 is accessible from all the CPU modules 110 connected to the shared memory bus 102, and determines the access person by excluding a plurality of access persons by the arbitration function. As described above, in the shared memory access, as viewed from the microcomputer 111, the access time to the bus interface 114, the bus arbitration by the bus interface 114, and the access time to the shared memory 101 are referred to the internal ROM 112, RAM 113, and the like. It takes longer time than access time. Furthermore, if the loss is caused by the arbitration, the shared memory access right finally turns around after waiting for the shared memory access by the other CPU modules 110 to be completed, so it takes more time.

  FIG. 20 shows a configuration example of the conventional bus interface 114. FIG. 21 shows an example of a shared memory access timing chart (in the case of read processing) by the conventional bus interface 114.

  The bus interface 114 and the microcomputer 111 are connected to the data bus, address bus, select (* CS), read / write (RD / * WT), and ready (RDY) signal lines. When the “internal control signal and RDY generation unit” 131 in the bus interface 114 recognizes an access request to the shared memory 101 based on a select * CS signal and an address signal transmitted from the microcomputer 111, the ready (RDY) signal is waited for. The microcomputer 111 is set in the WAIT state by setting the state to “L” (Low), and an access request is issued to the bus access control unit 132. As shown in FIG. 21, the ready (RDY) signal means WAIT when ‘L’, and RDY (WAIT cancellation) when ‘H’.

  The bus access control unit 132 accesses the shared memory 101 in response to this access request. Note that a data bus and an address bus are connected to the bus access control unit 132, and an access address to the shared memory 101 is input via the address bus. If the read / write (RD / * WT) signal is a write request * WT, write data to the shared memory 101 is input via the data bus, and the bus access control unit 132 stores the data in the shared memory 101. Is written in the area of the access address. On the other hand, if the read / write (RD / * WT) signal is a read request RD, the bus access control unit 132 reads data from the area of the access address of the shared memory 101 and outputs the read data to the data bus. To do. Of course, the destination of these inputs / outputs is the microcomputer 111.

Since FIG. 21 is an example in the case of read, it is assumed here that read access to the shared memory 101 is performed in response to a read request RD.
When the read access on the shared memory bus 102 is completed, the bus access control unit 132 outputs the read data on the data bus as described above, and the access to the “internal control signal and RDY generation unit” 131 is completed. To be notified. Upon receiving this notification, the “internal control signal and RDY generator” 131 changes the ready (RDY) signal from the WAIT state “L” to the RDY state “H” as shown in FIG. Thereby, the microcomputer 111 acquires read data.

As a result, the microcomputer 111 completes the execution of the shared memory access instruction and proceeds to the next instruction execution on the application program. However, as shown in FIG. 21, until the read access to the shared memory 101 by the bus interface 114 is completed, the ready (RDY) signal is in the WAIT state, and the microcomputer 111 is kept waiting for this time. . And as mentioned above, this waiting time is long, and when it is lost by mediation, it becomes very long.

As a method for shortening the waiting time when accessing a low-speed device, for example, a method described in Patent Document 1 is known.
In this method, when the master accesses the slave, the master is released from the wait when the command is once received in the buffer provided in the slave.
Japanese Patent Laid-Open No. 11-296210

The problems of the prior art described above will be described below.
(Problem 1)
In the PLC, a plurality of processes such as application execution and communication with a loader are executed by one microcomputer 111 for each CPU module 110. In the PLC, access to the I / O module 104 and memory sharing with the plurality of CPU modules 110 still exist, but the access time to a low-speed device such as this shared memory is the operating speed of the microcomputer 111 and the RAM 113. Since the access time to the ROM 112 is overwhelmingly long, the processing that must be performed by the microcomputer 111 has become seriously hindered and delayed by low-speed device access. In particular, since the access time to the shared memory is very long compared to the operation speed of the microcomputer 111, the CPU continues to be in the WAIT state until the shared memory access is completed as described in the prior art. This greatly hinders the processing that the microcomputer must perform.

In recent years, it is thought that PLCs are also required to connect to higher-speed networks, and countermeasures against deterioration in processing performance of the microcomputer 111 are becoming increasingly important.
It is required to solve the problem of deterioration in processing performance of the microcomputer 111 accompanying access to such a low-speed device such as a shared memory.

  Here, in particular, when the microcomputer 111 performs multitask execution as shown in FIG. 18, for example, as shown in FIG. 22, shared memory access is performed while a low level task (default task or the like) is being executed. If there is a high-level task (for example, 0-level task) during the WAIT, the microcomputer 111 is in the WAIT state, so an interrupt is not accepted and a high-level task (for example, 0-level task) Can't move on. Of course, as shown in the figure, when the WAIT state is released, a high-level task can be executed, but it is necessary to wait until the WAIT state is released. For this reason, when response performance is required (a high-level task is usually required to be executed at a predetermined execution timing), it becomes a serious problem.

  In addition, there is a situation where communication processing is frequently performed because the PLC is connected to the network (not particularly shown, for example, the CPU module is connected to the LAN, and with the external information processing apparatus etc. via the LAN. For example, when it is necessary to communicate frequently), a long-term WAIT state causes a decrease in throughput and a buffer underrun.

  As described above, even when the microcomputer accesses a low-speed device with a long access time during execution of an application program, the microcomputer can be released from the WAIT state to perform other processing (especially high-level task processing). It is this issue to make it possible to accept interrupts.

Note that the application program in the PLC includes “sequential processing” in which, for example, as shown in a ladder diagram in FIG. 23, sequential instruction execution is performed and the immediately preceding instruction execution result is obtained and the next instruction execution is started. Also, for example, there is a “determination process” in which a certain execution is performed when a certain condition is satisfied, as expressed in an FBD (Function Block Diagram) or ST (Structured Text) language defined in IEC61131-3.

  As described above, as a programming language, it is desirable that the access function has an optimum interface corresponding to the application. In other words, if it is applied with a memory access instruction, if it is a ladder diagram, I want the execution to move to the next instruction after the memory access is completed. On the other hand, even if the memory access is not completed with FBD, only the memory access request is issued for the time being and the next instruction is executed, and it is determined whether the memory access is completed in the next scan. It only needs to be able to process.

(Problem 2)
In the case of the FBD or ST language, the application program includes a plurality of memory access instructions instead of only one. Since the timing at which each access instruction is executed is determined by the flow of program processing, a plurality of shared memory access requests can be generated in one scan. For example, as shown in FIG. 25, there are many FBs (function blocks) in one task, and instructions of 100 FBs FB1 to FB100 are executed in one scan shown in the figure, and this FB1 When all of the FBs 100 generate shared memory access requests, 100 shared memory access requests can be generated in one scan. Even in such a case, the task is to sequentially access in the order in which the access requests are generated. Note that execution of a plurality of instructions in one task from the beginning to the end is called one scan.

(Problem 3)
As shown in FIG. 19, a loader 120 may be connected to the PLC. The loader 120 is generally connected to monitor application variables, rewrite variables, download programs, and the like.

  When it is desired to monitor a variable in the shared memory during execution of the application, a monitor command is issued from the loader 120, the microcomputer 111 receives the monitor command, interrupts the application, or scans end (a state in which the application is not executed) ), The system software accesses the shared memory.

  As already described, since WAIT is applied to the microcomputer 111 during the shared memory access, no application is executed during the shared memory access according to the monitor command from the loader 120 as shown in FIG. That is, the default task is interrupted, and is not executed because the interrupt is not accepted even when the execution timing of the periodic task such as the 0-level task and the 1-level task is reached.

  As described above, when there is a monitor request from the loader 120, there is a problem that the execution of the application is not performed or the execution is delayed, and it is possible to execute the application without being affected by the request from the loader 120. It is a problem.

  Further, the conventional technique described in Patent Document 1 is a story between the CPU module 110 (corresponding to the master) and the I / O module 104 (corresponding to the slave) in FIG. Yes, this is a technique equivalent to immediately returning a wait signal to the CPU module 110 before the I / O module 104 writes to the peripheral memory connected to the I / O module 104, and is not about shared memory access. . That is, in Patent Document 1, since it is a bus to which a plurality of slaves are connected, it is meaningful to immediately release the bus. However, in the case of a shared memory, even if the bus is released even if access has not been completed. has no meaning.

  Furthermore, in Patent Document 1, it takes time to transmit and receive data between the master and the slave via the bus. Further, Patent Document 1 cannot deal with the problem in multitasking as described in Problem 1 above, and cannot cope with a case where a large number of access instructions are generated in one scan as in Problem 2. The same applies to the problem 3.

  The problem of the present invention is that when a microcomputer accesses a device (low speed device) having a long access time such as a shared memory, other processing can be executed or an interrupt can be accepted without waiting for completion of access execution. In particular, it is possible to cope with a case where the microcomputer can execute a task of a plurality of levels, or even if a plurality of FBs generate an access request in the task, the requests are sequentially processed in the order in which the requests are generated. Or a programmable controller CPU module that enables an application to be executed without being affected by a low-speed device access caused by a request from the outside of the CPU module (or outside the PLC) such as a monitor request, and the like Etc. is to provide.

The CPU module of the programmable controller of the present invention is a CPU module having a processing unit for executing a task at a plurality of levels and an interface unit for accessing a low-speed device in response to a request from the processing unit. A plurality of access channels corresponding to each of the plurality of levels, and when the access request to the low-speed device is generated while executing the task at any level, the processing unit is set to the level of the task. An access processing unit that requests execution of the low-speed device access process for the corresponding access channel, and the interface unit executes the low-speed device access process when reception of the request from the access processing unit is completed. WAIT state with the request of Releasing the said WAIT state of the processing unit, thereafter, it executes the access to the low-speed device based on the request.

  In the CPU module, when accessing any low-speed device outside the CPU module, the interface unit executes low-speed device access processing in response to a request from the processing unit. Release the WAIT status of the processing unit. Therefore, the processing unit can execute other processes and can accept interrupts.

In particular, in the above configuration, the interface unit has a plurality of access channels corresponding to each of a plurality of levels.
Thereby, for example, the processing unit can execute a task at a higher level than the task for which the access request has been generated by releasing the WAIT state, and the access processing means can execute the task at the higher level. When an access request to the low-speed device is generated, it is possible to request the access channel corresponding to the task level to execute low-speed device access processing.

  Also, for example, when the application of the task executes sequential processing, the access processing means may request the execution of the low-speed device access processing for the access channel in response to execution of an arbitrary instruction in the application. The access channel is periodically polled and the completion of the low-speed device access processing is awaited.

The application that executes the sequential process is a process that sequentially executes instructions, obtains the previous instruction execution result, and shifts to the next instruction execution as shown in a ladder diagram, for example. In this case, since the next instruction cannot be executed unless the immediately preceding instruction execution is completed, the polling is performed and the completion of the execution is awaited. However, when an upper level task is interrupted, the upper level task can be executed.

  Also, for example, when the application of the task is to execute a determination process, the access processing means, after executing an arbitrary instruction in the application, requests execution of a low-speed device access process for the access channel, Move on to execution.

  An application that executes the above determination processing is an application that can move to the next instruction without waiting for completion of execution of the previous instruction, such as an application expressed in FBD. For this reason, it is possible to immediately return to the application without executing polling and execute the next instruction.

However, when the determination process is executed, a plurality of shared memory access requests can be generated in one scan. In order to deal with this, for example, the following configuration is added. That is, for example,
When the application of the task is to execute a determination process, the processing unit further includes a storage unit corresponding to each level, and the access processing unit accesses a low-speed device according to execution of an arbitrary instruction in the application. Each time a request occurs, the request is stored in the storage means corresponding to the level of the application, and each time the low-speed device access processing is completed on the interface unit side, the request stored in the storage means The oldest request is taken out, and the interface unit is requested to perform low-speed device access processing.

  In addition, for example, the interface unit further includes a system access channel, and the access processing means performs a low-speed device access process on the system access channel when a low-speed device access request is generated by an application other than the task application. The interface unit releases the WAIT state of the processing unit when the request to the access channel is completed, and the system access channel sends the processing unit to the processing unit when the low-speed device access processing is completed. An access completion interrupt is output.

  With the above configuration, it is possible to cope with a bus access request caused by other than the task application. Furthermore, there is no need to perform polling after the request, and for example, read data can be fetched by a completion interrupt, so that the processing capability of the processing unit can be used without waste.

  According to the CPU module of the programmable controller of the present invention, the programmable controller, etc., when the microcomputer accesses a device (low speed device) having a long access time such as a shared memory, other processing is performed without waiting for completion of access execution. It can be executed or can accept interrupts, especially when the microcomputer can execute multiple levels of tasks. Also, it is possible to provide access means for interfaces and specifications according to applications, such as for ladder diagrams and FBDs. Furthermore, even if multiple FBs generate access requests within a task, the requests can be processed sequentially in the order of request generation. Alternatively, the application can be executed without being affected even when a low-speed device access caused by a request from the outside of the CPU module (or outside the PLC) such as a monitor request is performed.

Embodiments of the present invention will be described below with reference to the drawings.
In this example, for example, a PLC capable of executing tasks of three levels of 0 level, 1 level, and default task is assumed.

FIG. 1 shows a configuration example of the bus interface in the first and second embodiments.
FIG. 2 shows the overall configuration of the programmable controller of this example. The overall configuration itself is the same as the conventional one. That is, a plurality of I / O modules 4 and a plurality of CPU modules 10 are connected to the I / O bus 3 and communicate with each other. The plurality of CPU modules 10 are also connected to the shared memory bus 2, and each CPU module 10 accesses the shared memory 1 via the shared memory bus 2.

Each CPU module 10 includes a microcomputer 21, a ROM 22, a RAM 23, a bus interface 10, an I / O interface 25, and an RDY control unit 26.
The I / O interface 25 is connected to the I / O bus 3 and performs communication control with other modules. The bus interface 10 is connected to the shared memory bus 2 and controls access to the shared memory 1.

  However, the configuration / operation of the bus interface 10 is different from the conventional one, and the operation of the microcomputer 21 is also different from the conventional one. That is, in brief, the bus interface 10 includes a plurality of access channels corresponding to each task level for receiving an access request to the shared memory 1. On the other hand, the system software installed in the microcomputer 21 executes a bus access procedure different from the conventional bus access procedure. The bus access procedure of this example is not a procedure for directly accessing the shared memory 1 as in the prior art, but is a procedure for performing read / write to the access channel. An example is shown in FIG. 5 and will be described later.

  As shown in FIG. 2, the CPU module 20 is configured by blocks of a RAM 23, a ROM 22, a bus interface 10, an I / O interface 25, and an RDY control unit 26 with a microcomputer 21 as a center. A shared memory 1 that can be accessed from a plurality of CPU modules 20 exists on the shared memory bus 2, and the shared memory 1 is positioned as a low-speed device in this embodiment.

  Although not shown, the RDY control unit 26 has a configuration for centrally managing and controlling RDY signals from not only the bus interface 10 but also other configurations (I / O interface 25 and the like). Therefore, the RDY control unit 26 will not be described in particular and will be described assuming that the RDY signal is directly exchanged between the microcomputer 21 and the bus interface 10.

  Here, the bus interface 10 shown in FIG. 1 will be described. The bus interface 10 has as many access channels as the number of application task levels that can be executed by the PLC. In this example, as described above, a PLC capable of executing a three-level task is taken as an example. As shown in FIG. 1, the bus interface 10 has three levels for level 0, level 1, and default task. Access channels 11, 12, and 13 are provided. Each of these access channels includes a register group that can be read and written from the microcomputer 21. One access channel can accept only one access request at a time. Therefore, requests for tasks at the same level are not accepted until the previous request is completed.

  In the example shown, each access channel has 5 registers each. Here, taking the level 0 access channel 11 as an example, it comprises five registers: a command register a, an access address register b, a write data register c, a read data register d, and a status register e. The other access channels 12 and 13 have the same configuration. Therefore, the bus interface 10 has a total of 15 registers for three channels.

When the microcomputer 21 writes an access request to the access channel, the bus interface 10 side performs bus access (shared memory access) independently of the microcomputer 21 thereafter. That is, the access channel in which the access request is written accumulates the request command and the like in the access request queue 14. The bus access control unit 15 takes out a request command from the access request queue 14 and starts executing access to the shared memory 1. When this access execution is completed, the completion bit of the status register e in the access channel from which the request is issued is set.

  When an access request is newly written to another access channel during access execution, the request command or the like is loaded in the access request queue 14. After the completion of the previous access, the next access request loaded in the sequential queue 14 is executed. In this way, access to the shared memory is performed without interruption.

Specifically, the access channel is a digital circuit realized by, for example, a gate array, a PLD (Programmable Logic Device), or the like.
This will be described in more detail below.

  In preparation for a case where an interrupt by a higher-level task occurs on the microcomputer 21 side during a shared memory access in response to a request from a lower-level application task, and a shared-memory access request is generated while this higher-level application task is being executed. As described above, the same number (three in this case) of access channels as the number of application task levels are prepared in the bus interface 10. However, higher-level task requests are not preferentially processed. However, for example, when a level 0 task is executed after a default task issues an access request and a level 1 task executed thereafter also issues an access request, the level 0 task is executed immediately without waiting. A task with a higher level is more effective in this respect because it is required to be executed at a determined timing without breaking the periodicity.

  For example, the microcomputer 21 requests access to the level 0 access channel 11 for a shared memory access request from a level 0 task, and accesses the level 1 access channel 12 for a shared memory access request from a level 1 task. Request.

  When shared memory access is performed via an access channel in this way, it takes extra time to write a request to the access channel compared to direct shared memory access. Since the shared memory access time by the unit 15 is long, the time taken to complete the access as a whole is only slightly increased. In exchange, the microcomputer 21 can execute another process (for example, a higher-level task or another instruction in the same task) for a long time until the access is completed. Interrupts are accepted without problems.

  FIG. 3 shows a register map of these various registers. As shown in FIG. 3, each address in a memory (not shown) of the bus interface 10 is assigned as the various registers. The microcomputer 21 stores this register map. For example, when a read / write request to the shared memory 1 is generated by executing a level 1 task, for example, the address “+6” shown in the figure is output to the address bus, and the shared memory 1 is accessed to the data bus. By outputting the address, the access address to the shared memory 1 is set in the access address register b of the access channel 12.

FIG. 4 shows a configuration example of the various registers.
As shown in FIG. 4, the command register a uses only two bits, a read access request bit and a write access request bit. For example, when there is a read access request, the read access request bit is “1”, and when there is a write access request, the write access request bit is “1”.

  As described above, the access address to the shared memory 1 designated by the microcomputer 21 is set in the access address register b. The read data register c stores read data read from the shared memory 1 in response to a read access request. The write data register d stores the write data to the shared memory 1 output from the microcomputer 21 in response to the write access request.

  The status register e uses only one bit (completion bit) indicating access completion / non-completion. Here, it is assumed that when the completion bit is “0”, access is not completed, and when the completion bit is “1”, access is completed. When an arbitrary access request is received from the microcomputer 21, the completion bit is reset to "0". When a response to this request is received from the bus access control unit 15, the completion bit is set to "1".

Here, the operation of the configuration of FIG. 1 will be described.
As described above, when an access request is written, each of the access channels 11 to 13 accumulates the request command or the like in the access request queue 14. Here, the access request written by the microcomputer 21 includes the request command indicating whether it is a read access request or a write access request, an access address to the shared memory 1, and if it is a write access request, the shared memory 1 Write data is also included. The request command is set in the command register a, the access address is stored in the access address register b, and the write data is stored in the write data register c.

The access channel in which the access request is written is the request command and its own identification information (information indicating whether it is level 0, level 1 or default. Stored in each access channel in advance). Are stored in the access request queue 14 (hereinafter collectively referred to as access request data). The access request queue 14 is a FIFO (Fast In
Fast Out) structure. Therefore, access is executed in the order of request generation.

  The bus access control unit 15 takes out new access request data from the access request queue 14 every time read access processing or write access processing to the shared memory 1 in response to an arbitrary access request is completed. At this time, the identification information is directly input to the address selector 17, the write data selector 18, and the channel selector 19, and becomes a selection signal for these selectors. That is, each of these selectors selects an access channel corresponding to this identification information. Therefore, the bus access control unit 15 acquires data from the register of the requesting access channel or writes data to the register via these selectors.

  That is, the bus access control unit 15 reads the data stored in the access address register b of the request source access channel via the address selector 17 regardless of the read / write request. If the request is a write request, the data stored in the write data register c of the request source access channel is further read out via the write data selector 18. Then, access processing for the shared memory 1 is executed based on the retrieved request command and the read data. When the access processing is completed, the processing result is written to the requesting access channel via the channel selector 19. In the case of a read request, the read data obtained as a processing result is stored in the read data register d, and the completion bit of the status register e is set to ‘1’. In the case of a write request, the completion bit of the status register e is set to “1”.

Then, the bus access control unit 15 takes out the next access request data from the access request queue 14 and executes the same processing as described above.
Note that the above processing is merely an example. For example, the bus access control unit 15 may extract the access request data from the access request queue 14, acquire both the command and the identification information, and control each of the selectors based on the identification information.

  As described above, the microcomputer 21 stores data in each register of the access channel. This will be described with reference to FIG. FIG. 5 is an access timing chart in the case of a read request.

  First, as shown in FIG. 1, the “internal control signal and RDY generator” 16 is connected to the address bus and receives an arbitrary address output from the microcomputer 21. As described above, this address is an address of an arbitrary register of an arbitrary access channel, and is different from an access address to the shared memory 1. The “internal control signal and RDY generator” 16 receives a select signal (* CS) and a read / write signal (RD / * WT) output from the microcomputer 21.

  The “internal control signal and RDY generator” 16 stores the data in the register at the address when the select signal (* CS) is valid (“L”) and the read / write signal (RD / * WT) is “0”. Write data that is input via the bus. The “internal control signal and RDY generator” 16 is stored in the address register when the select signal (* CS) is valid (“L”) and the read / write signal (RD / * WT) is “1”. The output data is output to the microcomputer 21 via the data bus. That is, in the read / write signal (RD / * WT), “0” means write and “1” means read. The microcomputer 21 makes the select signal (* CS) valid ('L') when the address output to the address bus is one of the addresses in the registers a to d.

  The “internal control signal and RDY generation unit” 16 transmits an RDY signal “H” to the microcomputer 21 every time access to the register according to an instruction from the microcomputer 21 is completed. Since only reading / writing to the register is performed, the RDY signal “H” is returned to the microcomputer in a short time.

  Since the example shown in FIG. 5 is a read request as described above, the system software that executes the processing of FIG. 6 in the microcomputer 21 first outputs the address of the access address register b to the address bus and shares it to the data bus. The access address for the memory 1 is output. Of course, at that time, the microcomputer 21 sets the select signal (* CS) to valid (“L”) and sets the read / write signal (RD / * WT) to “0”. Accordingly, the “internal control signal and RDY generation unit” 16 performs write control to the access address register. Then, the RDY signal 'H' is returned.

  Subsequently, the microcomputer 21 outputs the address of the command register a to the address bus and also outputs a request command indicating that it is a read access request to the data bus. Since the read / write signal (RD / * WT) is “0”, the “internal control signal and RDY generator” 16 controls the writing to the command register a. Then, the RDY signal 'H' is returned.

  After that, if the order comes according to the access request queue 14, the bus access control unit 15 performs read operation control on the shared memory 1. When the read is completed, the read data read from the shared memory 1 is stored in the read data register d of the access channel of the request issuing source, and “access complete” is set in the status register (the “completion bit” is “1”). 'Become).

  The system software polls the “complete bit” of the status register e after writing the request command to the command register a. That is, as shown in FIG. 5, by periodically outputting the address of the status register e to the address bus and setting the read / write signal (RD / * WT) to “1” (read request), the status register e Read the data. Naturally, the completion bit is “0” (incomplete) until the access to the shared memory 1 is completed. Of course, the RDY signal 'H' is returned immediately each time (since the WAIT state is canceled), the waiting time of the microcomputer 21 can be very short. Then, as shown on the right side of FIG. 5, when the completion bit of the status register e is set to “1” and is read out, the microcomputer 21 knows that the access has been completed, which is not shown in FIG. The read data from the shared memory 1 is acquired by outputting the address of the read data register d to the address bus and setting the read / write signal (RD / * WT) to “1” (read request). Thus, the shared memory read sequence is completed.

  In the case of a write request to the shared memory 1, after the access address is written, the write data to the shared memory 1 is set in the write data register c, and a request command indicating the write request is written in the command register a.

  The microcomputer 21 then waits while polling the status register e until the access is completed, as in the case of the read request. Of course, if an upper-task interrupt occurs during that time, the upper-task processing is executed, so polling is interrupted. When the processing of the upper task is completed, polling is resumed.

  Here, as an example of an application program in the PLC, there is a sequential process as shown in a ladder diagram shown in FIG. 23, in which sequential instruction execution is performed, the immediately preceding instruction execution result is obtained, and the next instruction execution is started. Alternatively, there is an application command in the FBD as shown in FIG.

  First, the processing of the system software in the case of a ladder diagram will be described below. Here, using the example shown in FIG. 23, a process when a contact instruction is first executed and then a coil instruction is executed will be described.

In the microcomputer 21, the application calls the system software when it executes each instruction shown in the drawing and needs to access the shared memory 1.
The system software executes the process of FIG. 6 in the case of a read process for the shared memory 1, and executes the process of FIG. 7 in the case of a write process. That is, as described above, the system software exists as a subroutine called by the application, but there are a plurality of types of subroutines. In the case of read processing, the subroutine for executing the processing of FIG. In the case of the write process, a subroutine for executing the process of FIG. 7 is called. The same applies to the processing of other processing flowcharts to be described later.

Here, it is assumed that the process related to the contact command is a read process, and the process related to the coil command is a write process.
The processing shown in FIGS. 6 and 7 has already been described in the description of FIG. 5 and will be briefly described here.

The process shown in FIG. 6 is a process of a data read request from the shared memory, and the process shown in FIG. 7 is a process of a data write request to the shared memory.
In the process shown in FIG. 6, first, a process of writing an access address to the shared memory 1 in the access address register b of the access channel corresponding to the level of the contact instruction (step S
11) and a process of setting the read access request bit of the command register a to “1” (step S12). Thereafter, the polling is performed. That is, the status register e of the access channel to which the above request has been written is periodically read (step S13), and if the completion bit is '1' (completed) (step S14, YES), the read data register of this access channel Data is read out from d and transferred to the application (step S15). Upon receiving this, the application subsequently executes a coil command. Thereby, the process of FIG. 7 is executed. Note that the read data from the shared memory is the input value of the coil command. Therefore, the coil command cannot be executed until the contact command execution is completed.

  In the process of FIG. 7, first, a process of writing an access address to the shared memory in the access address register b for the access channel corresponding to the level of the coil instruction (step S21), and the write data register c to the shared memory Is executed (step S22), and the command register write access request bit is set to '1' (step S23).

  Thereafter, the polling is performed. That is, the status register e of the access channel is periodically read (step S24), and if the completion bit is ‘1’ (completion) (step S25, YES), the application is notified of completion and the process returns to the application.

  In the above description, “according to the level of the contact command” and “according to the level of the coil command” are described, but in the example shown in FIG. 23, the level is not different between the contact command and the coil command. All of the series of instructions in the same task are at the same level. This is the same in the case of FBD. For example, all instructions (FB) in one task shown in FIG. 25 are at the same level (the level of this task).

  In the processing described with reference to FIGS. 6 and 7, after issuing a request to the access channel, the processing of the system software is continued without returning to the application (polling is repeated). Therefore, execution of subsequent instructions in the ladder diagram does not proceed until read data is obtained from the shared memory 1 if it is a read request, or until data write to the shared memory 1 is completed if it is a write request. This is because, as described above, the ladder diagram is a sequential process in which instruction execution is performed sequentially, the previous instruction execution result is obtained, and the process proceeds to the next instruction execution. Therefore, polling is performed in the system software layer for both the coil command and the contact command, and the access is completed to return to the application. However, since interrupts can be accepted, transition to a higher level task is possible as described above.

FIGS. 8A and 8B show specific examples of application instructions expressed in FBD.
The basic concept of FB is defined and explained in the international standard IEC61131-3.
FIG. 8A shows an example of READ_WORD (read FB), and FIG. 8B shows WRITE_WORD (write FB). Note that the notation shown in FIG. 8 is simply according to IEC61131-3, and is not limited to this example.

  The instruction (READ_WORD) shown in FIG. 8A includes RQ (access request) and AD (access address) at the input terminal, and DONE (complete) and RD (read data) at the output terminal. When DONE becomes “1”, the subsequent instruction knows the completion of execution of this instruction (READ_WORD), and newly executes the instruction using data (shared memory read data).

Data input from the input terminal, output data information from the output terminal, and internal state information (EX bit, XRQ bit, E_DONE bit) are stored and held in a memory area called an instance that is assigned to one FB. Is done.

The command (WRITE_WORD) shown in FIG. 8B includes RQ (access request), AD (access address), WD (write data) at the input terminal, and DONE (complete) at the output terminal.
8A and 8B, this processing is executed when an access address to the shared memory is input to AD (access address).

FIG. 9A shows the data structure of the READ_WORD instance in the first embodiment.
In the illustrated instance 80, the EX bit 81 is a bit indicating that access is being executed. XRQ bit 82 is the value input to the RQ terminal during the previous scan, RQ bit 83 is the value input to the RQ terminal during the current scan, and XRQ bit 82 is '0' and RQ bit 83 is '1' , "There is a new request" is determined (YES in step S97 described later). The DONE bit 84 is output data of the DONE terminal, and “1” means complete and “0” means not completed.

  Further, the address lower address 85 and the address upper address 86 store access addresses to the shared memory 1. The read data lower 87 and the read data upper 88 store data read from the shared memory 1. As shown in the figure, the lower address 85, the upper address 86, the lower read data 87, and the upper read data 88 are stored in the addresses +2, +3, +4, and +5 from the start address of the instance 80, respectively.

FIG. 9B shows a process flowchart of the system software called by the READ_WORD.
In FIG. 9, first, the DONE bit is cleared (not completed) (step S91). Then, it is determined whether or not access is being executed (step S92). This refers to the READ_WORD instance 80 of the caller, and if the EX bit 81 = '1', it is determined that access is being executed.

  If the access is being executed (step S92, YES), the status register e of the access channel corresponding to the READ_WORD level is read (step S93), and if the completion bit is “1” (completed) ( In step S94, YES), data is read from the read data register d of the access channel, and stored in the +4 and +5 addresses of the instance 80 (lower read data 87, higher read data 88) (step S95).

  Then, the EX bit 81 is cleared (1 → 0), and the DONE bit 84 is set (0 → 1) (step S96). Then, the process proceeds to step S101. If the access is being executed and is not completed (step S94, NO), the process proceeds to step S101 as it is.

In step S101, the value of the RQ bit 83 is copied to the XRQ bit 82. This process ends and returns to the application. On the other hand, if the EX bit = '0' (no access is executed) (step S92, NO), whether or not a new access request is generated for this READ_WORD. Determine. As described above, when the XRQ bit 82 is “0” and the RQ bit 83 is “1”, that is, when the RQ rises from 0 to 1, it is determined that there is a “new request” (step S1). S97, YES). In the case of “with new request”, first, the data (address lower 85, address upper 86) and the request command (read or write) stored in the addresses +2 and +3 of the instance 80 are respectively read into the READ_WORD. Are set in the access address register b and command register a of the access channel corresponding to the level (steps S98 and S99). Then, the EX bit 81 is set (0 → 1) (step S100), and the process proceeds to step S101. The access channel has a circuit configuration for performing an operation of storing the request command and the identification information in the access request queue 14 when a request command is set in the command register a.

When there is no new request (step S97, NO), the process proceeds to step S101 as it is.
FIG. 10 shows an access timing chart of the processing of FIG.
In FIG. 10, the vertical dotted line in the figure indicates the processing execution cycle. That is, the process of FIG. 9 is executed at each timing indicated by a vertical dotted line.

  Here, it is assumed that access is not being executed, and as shown on the left side of the figure, by detecting the rising edge of RQ (0 → 1) (YES in step S97), a new request is issued to the access channel. Become. That is, the address and the request command are written in the access channel register by the processing in steps S98 and S99. Further, the EX bit (EX flag) is set in step S100.

  When a request command is set in the command register a, the access channel stores the request command and the like in the access request queue 14 as described above, and thereafter, an access operation (read here) to the shared memory 1 is performed. Will be started. When the access is completed, the completion bit of the access channel is set to “1”. As a result, as shown on the right side of FIG. 10, the read data is read, the EX flag is cleared, and the DONE bit is set (steps S95 and S96) during the next process shown in FIG. As shown in FIG. 10, the DONE bit is set until the DONE bit is cleared by the next execution of the processing of FIG. 9 (by the processing of step S91), during which the application is set with the DONE bit = 1. Because of this, read completion is recognized and read data (87, 88) is used.

  Note that the processing of the system software called by WRITE_WORD shown in FIG. 8B is not particularly shown, but in the instance shown in FIG. 9A, the read data lower 87 and the read data upper 88 are located at addresses +4 and +5. Instead, the lower and upper write data are stored. Further, in the flowchart shown in FIG. 9B, after the processing of step S98, “write data stored in +4 and +5 of the instance (lower and higher) are stored. Is added to the write data register of the access channel. Furthermore, since the process of step S95 is not necessary, it is deleted.

  In the processing of FIG. 9 and the like, unlike the processing of FIG. 6 and FIG. 7, after issuing a request, polling is not performed, and the processing immediately returns to the application. This is because, as described above, in a program expressed in FBD or ST language, even if the memory access is not completed, only the memory access request is issued and the next instruction is executed. This is because it is sufficient to determine whether or not the memory access is completed in each of the scans. Compared to the case where contact instructions and coil instructions cannot execute instructions for tasks at the same level or lower while the shared memory is being accessed, all levels of tasks can be executed without leaving the time until access completion.

  Note that “next instruction execution” means that, for example, if FB1 issues a memory access request in FIG. 25, FB2 is executed even if the memory access is not completed. However, even if FB101, which is a subsequent instruction of FB1, has a specification that can be executed using the output before accessing FB1 even if the memory access is not completed, the memory access is not completed. However, the FB 101 can be executed.

In addition, when an upper-level task (not shown) is interrupted during execution of each instruction (FB) of the task shown in FIG. 25, this higher-level task is executed. The command execution is interrupted.

  By the way, when FB2 is executed in a state where memory access is not completed for FB1 as in the above example, there is a possibility that a memory access request may be generated in FB2. Since FB1 and FB2 are the same task, the level is naturally the same and the access channel of the request destination is the same, so that the request of FB2 cannot be received. In particular, since the order of execution within one task is determined as FB1 → FB2 →... FB100, the request of FB1 is accepted with the highest priority, so it is quite a request for other FBs after FB2. Cannot be accepted, and in particular, the last FB 100 can be in a situation where almost no requests are accepted. This is a problem related to the above problem 2. Therefore, it is necessary to accept the requests in the order in which the requests are generated.

Example 2 is proposed for this problem.
Example 2 will be described below. The second embodiment solves the problem 2 described above.
As described in Problem 2 (and as described above), in a program expressed in FBD or ST language, a plurality of access requests may occur within one task. The microcomputer side 21 has a request buffer for storing a shared memory access request. Prepare as many request buffers as there are application task levels.

  FIG. 12A shows the data structure of an instance of READ_WORD in the second embodiment. In the illustrated instance 40, the EX bit 41 is a bit indicating that the access is being executed, the XRQ bit 42 is a value input to the RQ terminal at the time of the previous scan, and E_DONE 44 is a bit indicating whether the access channel access is completed or not (ON ( Completed in '1'). The DONE bit 45 is output data from the DONE terminal. The RQ bit 43 is a value input to the RQ terminal at the time of the current scan, and when the XRQ bit 42 is ‘0’ and the RQ bit 43 is ‘1’, it is determined that “there is a new request”.

  Further, in the lower address 46 and the upper address 47, access addresses to the shared memory are stored. The read data lower 48 and the read data upper 49 store data read from the shared memory.

  FIG. 15A shows the data structure of the WRITE_WORD instance 60 in the second embodiment. As shown in the figure, the EX bit 41 to the upper address 47 are the same as the READ_WORD instance 40, and are therefore given the same reference numerals. The instance 60 includes a write data lower order 61 and a write data upper order 62 instead of the read data lower order 48 and the read data upper order 49.

FIG. 12B shows an example of the request buffer.
The request buffer 50 shown in FIG. 12B can store request queues as many as the number of instances in one task (that is, the number of FBs; the request buffer 50 is used for both reading and writing). It has a storage capacity (in the example shown, there are N FBs, and N request queues from request queue 1 to request queue N can be stored), and it is used as a ring buffer. Each request queue includes a start address 51 and request command data 52 of an instance of the request source FB. The data format of the request command data 52 is the same as that of the command register a in the access channel (in order to be able to read from the request queue and write to the command register a as it is).

  The request queue that is the current processing target is designated by the illustrated read pointer Rp or write pointer Wp. The read pointer Rp is a pointer for issuing a request to the access channel, and the write pointer Wp is used when an access request is accumulated in the internal processing of the FB.

  As software processing, the internal processing of the FB that accesses the shared memory (system software called by the FB) performs completion / incomplete processing of the access channel, stacking of new access requests in a queue, and issuing requests to the access channel. Like that.

  FIG. 11 shows a process flowchart of the system software called by the FB (READ_WORD). Further, a detailed flow of step S32 shown in FIG. 11 is shown in FIG. 13, and a detailed flow of step S36 is shown in FIG.

The process of FIG. 11 will be described below with reference to the detailed flow.
The access channel in the following description is naturally an access channel according to the level of the FB (READ_WORD). However, as described above, the levels of all FBs in the same task are the same.

  In FIG. 11, first, the DONE bit is cleared (not completed) (step S31). And the process which confirms the present condition is performed with respect to an access channel (step S32). The detailed flow of step S32 is shown in FIG.

  In FIG. 13, first, the status register e of the access channel is read (step S51). If the current completion bit state is “incomplete” (step S52, NO), there is no request at present. Or processing for any request is being executed, the command register a of the access channel is read and confirmed (step S60). As a result, if any of the read access request bit and the write access request bit is “1” (step S61, YES), “1” is set to the variable BUSY (step S62). On the other hand, if the access channel is currently not accepting any request (step S61, NO), the process proceeds to step S59, and '0' is set to the variable BUSY.

  On the other hand, when the status indicated by the completion bit of the status register e is “completed” (YES in step S52), the start address 51 of the request source instance from the request queue at the position pointed to by the read pointer Rp. And request command data 52 are read (steps S53 and S54). That is, it identifies the instance of the request source FB of the access request currently requested to the access channel and determines whether the request command is “read” or “write”. Note that the call source FB of this process (hereinafter referred to as the own FB or the own instance) is not necessarily the access request source FB. For example, in the above example, if this process is called as FB1 is executed and the current request source is FB2, the processes of steps S56 and S57 are performed on the instance of FB2. .

  If the request command is read (step S55, YES), data is read from the read data register d of the access channel, and this is read from the start address of the instance of the request source FB in +4 and +5 areas (read data lower 48, read data). It is stored in the upper 49) (step S56). Then, the process proceeds to step S57. On the other hand, if the request command is write (step S55, NO), the process proceeds to step S57 as it is.

  In step S57, the E_DONE bit 44 of the instance 40 of the request source FB is turned ON. Further, the access channel completion bit is cleared (step S58). Then, “0” is set in the variable BUSY (step S59), the process ends, and the process proceeds to the process of step S33 in FIG.

In step S33, it is determined whether access is being executed. This refers to the EX bit 41 of the own instance, and if the EX bit = '1', it is determined that the access is being executed. If access is being executed (step S33, YES), it is subsequently determined whether or not the E_DONE bit 44 of the local instance is '1' (ON) (step S34). As described above, the E_DONE bit 44 is turned ON in the process of step S57. However, as described above, this is not always turned ON by the process by the own FB, and may be turned ON by the process by another FB. obtain.

  If the E_DONE bit 44 = '1' (step S34, YES), the EX bit 41 of the local instance is cleared (1 → 0), the DONE bit 45 is set (0 → 1), and the E_DONE bit 44 is cleared. (1 → 0) (step S35). Then, the process proceeds to step S36. If the access requested by the own FB is being executed and is not completed (NO in step S34), the process directly proceeds to step S36.

  On the other hand, if the EX bit of the own instance is “0” (no access execution) (NO in step S33), if a new access request is generated in the instance of the own FB, the request can be issued. is there. Therefore, the XRQ bit 42 and the RQ bit 43 of the own instance are checked. If there is a new request (YES in step S38), the write pointer Wp indicates the start address of the instance and the request command data (read). The request queue is set at the indicated position (steps S39 and S40). The start address of the own instance is stacked because the instance is unique given to each FB. However, the use of the head address is merely an example. For example, if a separate ID exists by the PLC system, it may be used.

  Then, the position of the write pointer Wp is advanced by one (step S41). Finally, the EX bit 41 of the own instance is set (0 → 1) (step S42), and the process proceeds to step S36. If there is no new request (step S38, NO), the process proceeds to step S36.

A detailed flow of the process in step S36 is shown in FIG.
First, the read pointer Rp and the write pointer Wp are referred to (step S71). If the position of the read pointer Rp and the position of the write pointer Wp are the same (step S72, YES), there is no unprocessed request. (Of course, the initial positions of Rp and Wp are the same), and this process is terminated without issuing a new request for the access channel. The same applies to the case where the variable BUSY is “1” (when processing for the request queue at the position indicated by Rp is being executed on the bus interface side) (step S73, YES).

When there is an unprocessed request in the request buffer 50 (step S72, NO) and the variable BUSY is “0” (step S73, NO), a new request issue process to the bus interface is performed. That is, first, the start address 51 and request command data 52 of the request source instance (not necessarily the own instance) are acquired from the request queue at the position indicated by Rp (step S74). Then, the access address to the shared memory 1 is acquired from the areas +2 and +3 (lower address 46 and upper address 47) from the start address of the acquired request source instance, and this is obtained as the access address register of the access channel of the bus interface. b is set (step S75). Furthermore, if the acquired request command data 52 is a write request (YES in step S76), areas +4 and +5 from the start address of the request source instance (in this case, the lower write data 61 and the upper write data 62). Write data to the shared memory 1 is acquired and set to the write data register c in the access channel of the bus interface (step S77). Then, by setting the acquired request command data 52 to the command register a in the access channel (step S78), the new request issue processing to the bus interface is completed, and finally Rp is advanced by one (step S79). .

When the process of step S36 described above is completed, the value of the RQ bit 43 is finally copied to the XRQ bit 42 (step S37), and the process shown in FIG.
FIG. 15B shows a process flowchart of the system software called by the FB (WRITE_WORD).

  In the processing of FIG. 15B, the same processing as that of FIG. 11 is given the same step number, and the description thereof is omitted. The process of FIG. 15B is different from that of FIG. 11 only in that the process of step S81 shown in the figure is executed instead of the process of step S40 of FIG. In other words, in the setting to the request buffer, the request command data is only a write request.

Next, Example 3 will be described. The third embodiment solves the above-mentioned problem 3.
FIG. 16 shows a configuration diagram of the bus interface 70 in the third embodiment.
In the configuration illustrated in FIG. 16, the same configuration as the configuration illustrated in FIG. 1 is denoted by the same reference numeral, and the description thereof is omitted. That is, a system access channel 71 is provided in addition to the configuration shown in FIG.

  While each of the access channels 11 to 13 corresponds to a periodic task, the system access channel 71 corresponds to, for example, a monitor request from the loader 30 or message communication between CPU modules. Specifically, an access request to a low-speed device (in this case, indicates the shared memory 1 or the like) by a monitor command from the loader 30 and exchange of messages between the CPU modules 20 for application execution support (here, the shared memory) 1 is used). These correspond to a shared memory access request other than the access request generated by the application of the task due to an interrupt from the outside of an arbitrary CPU module.

  The system access channel 71 has an access completion notification function by interruption. That is, the completion of the bus access (shared memory access) is notified to the microcomputer 21 by the interrupt signal INT shown in FIG. The system access channel 71 activates (turns on) the INT signal when the “completion bit” in the status register of the system becomes “1”. As a result, a completion interrupt is input to the microcomputer 21, and the system software executes an interrupt process (not shown). If a read request is issued, the system software fetches the read data from the read data register in the interrupt processing, and then clears the completion bit in the status register shown in FIG. 17 to end the interrupt processing. And continue the suspended processing. The system access channel 71 turns off the INT signal by clearing this zero.

  As described above, in the third embodiment, the microcomputer 21 is the same as in the first embodiment after issuing a bus access request caused by a request from the outside of the CPU module (or outside the PLC) such as a monitor request. In addition to being able to return to the periodic task application immediately, there is no need to perform subsequent polling, and read data can be fetched by a completion interrupt, so that the processing power of the microcomputer can be used without waste.

The “polling” here is different from the polling that is performed as it is in the system software layer as in the ladder diagram described above. In this example, when the access request is completed, you can return to the scheduled task application immediately, but of course, you need to return the access result to the loader when the access is completed. It becomes necessary to interrupt the periodic task application and check whether the access is completed. This is the meaning of polling in this example. However, in this method, as described above, it is not necessary to perform polling.

  In this embodiment, the access target is a shared memory. However, the present invention is not limited to this example, and the application uses devices with slow responses such as RS232 and serial EEPROM (collectively referred to as low-speed devices). The present invention can also be applied to.

It is a figure which shows the structural example of the bus interface in Example 1,2. It is a figure which shows the structural example of the whole programmable controller of this example. It is a register map of various registers. It is an example of composition of various registers. It is an access timing chart in the case of a read request. It is a process flowchart figure of the system software in the case of a read request. It is a process flowchart figure of the system software in the case of a write request. (A), (b) is a figure which shows the specific example of the application command expressed by FBD. (A) is the data structure figure of the instance of READ_WORD in execution example 1, (b) is the processing flowchart figure of the system software which READ_WORD calls. 10 is an access timing chart of the process of FIG. 9. It is a process flowchart figure of the system software which READ_WORD calls. (A) is the data structure figure of the instance of READ_WORD in execution example 2, (b) is the figure which shows one example of request buffer. It is a detailed flowchart figure of step S32 shown in FIG. It is a detailed flowchart figure of step S36 shown in FIG. (A) is the data structure figure of the instance 60 of WRITE_WORD in Example 2, (b) is a process flowchart figure of the system software which WRITE_WORD calls. FIG. 10 is a configuration diagram of a bus interface in the third embodiment. FIG. 10 is a diagram for explaining a completion bit of a status register in the third embodiment. It is a figure which shows an example of multitask execution. It is a figure which shows the internal and external structural example of the conventional PLC. It is a structural example of the conventional bus interface. It is a timing chart (in the case of read processing) of shared memory access by a conventional bus interface. It is FIG. (1) for demonstrating the conventional problem. It is a figure which shows an example of a ladder diagram. It is FIG. (2) for demonstrating the conventional problem. FIG. 10 is a diagram for explaining an example of problem 2;

Explanation of symbols

1 Shared Memory 2 Shared Memory Bus 3 I / O Bus 4 I / O Module 10 Bus Interface 11 Access Channel (for Level 0)
12 Access channel (for level 1)
13 Access channel (for default)
a command register b access address register c write data register d read data register e status register 14 access request queue 15 bus access control unit 16 internal control signal and RDY generation unit 17 address selector 18 write data selector 19 channel selector 20 CPU module 21 microcomputer 22 ROM
23 RAM
25 I / O interface 26 RDY control unit 30 Loader 40 Instance 41 EX bit 42 XRQ bit 43 RQ bit 44 E_DONE
45 DONE bit 46 Address low 47 Address high 48 Read data low 49 Read data high 50 Request buffer 51 Request source instance start address 52 Request command data 60 Instance 61 Write data low 62 Write data high 70 Bus interface 71 System access channel 80 Instance 81 EX bit 82 XRQ bit 83 RQ bit 84 DONE bit 85 Address low 86 Address high 87 Read data low 88 Read data high

Claims (8)

A CPU module having a processing unit for executing a multi-level task and an interface unit for accessing a low-speed device in response to a request from the processing unit;
The interface unit has a plurality of access channels corresponding to each of the plurality of levels,
When an access request to the low-speed device is generated during execution of the task at any level, the processing unit requests the access channel according to the task level to execute low-speed device access processing. Having access processing means;
Wherein the interface unit is at the time of the reception completion of the request from the access processing means, said releasing the WAIT state of the processing unit and WAIT state with the request for execution of the low-speed device access process, the subsequent A CPU module of a programmable controller that executes access to the low-speed device based on the request.   The processing unit can execute a task at a higher level than the task for which the access request has been generated by releasing the WAIT state, and the access processing means can execute the task at the lower speed device while executing the higher level task. 2. The CPU module of a programmable controller according to claim 1, wherein when an access request is generated, the access channel according to the task level is requested to execute low-speed device access processing. 3.   2. The interface unit according to claim 1, further comprising access control means for executing access to the low-speed device in the order in which the request is received when the low-speed device access processing is requested to the plurality of access channels. Or a CPU module of the programmable controller according to 2;   When the application of the task executes sequential processing, the access processing means, after executing an arbitrary instruction in the application, requests execution of low-speed device access processing for the access channel, The programmable controller CPU module according to claim 1, wherein the CPU module of the programmable controller according to claim 1 is configured to wait for completion of execution of the low-speed device access processing by performing periodic polling.   If the application of the task is to execute a determination process, the access processing means moves to the next instruction execution after requesting execution of the low-speed device access process for the access channel in accordance with execution of an arbitrary instruction in the application. The CPU module of the programmable controller according to any one of claims 1 to 3. When the application of the task is to execute a determination process, the processing unit further includes storage means corresponding to each level,
The access processing means stores the request in the storage means corresponding to the level of the application every time a low-speed device access request is generated as a result of execution of an arbitrary instruction in the application, and the low-speed device access is performed on the interface unit side. 2. The method according to claim 1, wherein each time processing is completed, the oldest request among the requests stored in the storage unit is extracted, and the interface unit is requested to perform low-speed device access processing. Programmable controller CPU module. The interface unit further comprises a system access channel;
The access processing means requests a low-speed device access process to the access channel for the system when a low-speed device access request other than the application of the task occurs,
When the interface unit completes the request to the access channel, it releases the WAIT state of the processing unit,
The CPU module of the programmable controller according to claim 1, wherein the system access channel outputs an access completion interrupt to the processing unit when the low-speed device access processing is completed.   A programmable controller comprising the CPU module according to claim 1.

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