JP4978809B2 - Image processing device - Google Patents

Description

  The present invention relates to an image processing apparatus, and more specifically, an original reading unit that generates an original image by optical reading of an original, an image reduction unit that generates a reduced image by reducing the original image, and displays the reduced image. The present invention relates to an improvement of an image processing apparatus having an image display unit.

  As a memory that temporarily stores pixel data during image processing, a frame memory that holds pixel data in units of one image is often used (for example, Patent Documents 1 to 3). The frame memory is composed of a DRAM, but in recent years, various improvements have been made to increase the speed and reduce the power consumption. For example, the number of memory accesses is reduced by devising burst access by the memory controller. In addition, a memory that can perform burst access in the vertical scanning direction as well as the horizontal scanning direction with respect to arbitrary pixel data in the same block, or a memory cell group arranged in a matrix, and a pixel by a row decoder and a column decoder A memory capable of accessing data simultaneously has been proposed.

Such a method using a frame memory has a margin in memory access timing, and can be easily performed even in image processing performed using a plurality of pixel columns adjacent in the vertical direction as processing units. This is more advantageous than using a line memory that holds pixel data in units of pixel columns in the scanning direction. However, the frame memory has a problem that the manufacturing cost increases because the memory access control is more complicated than the line memory.
JP 2001-197365 A JP 61-281672 A JP 2005-117501 A

  The present invention has been made in view of the above circumstances, and provides an image processing apparatus capable of reducing manufacturing costs by using a line memory as a memory for temporarily storing pixel data during image processing. Objective. In particular, an object of the present invention is to provide an image processing apparatus that can reduce the storage capacity of a line memory that holds pixel data when an original image generated by optical reading of a document is reduced. It is another object of the present invention to provide an image processing apparatus that can reduce the time required for original image reduction processing.

  An image processing apparatus according to a first aspect of the present invention includes an original reading unit that generates an original image by optical reading of an original and sequentially outputs pixel data; and the original image is horizontally 1 / N (N is 2 or more). And an image reduction unit that generates a reduced image by reducing it to 1 / M (M is an integer of 2 or more) in the vertical direction, and an image display unit that displays the reduced image. The image reduction unit averages the N pixel data and generates horizontal reduced pixel data every time N pieces of pixel data adjacent in the horizontal direction are input from the document reading unit. A gain adjustment unit that generates a gain adjustment value by obtaining a quotient obtained by dividing the horizontal reduction pixel data by a predetermined value, a line memory that holds the gain adjustment value, and a gain adjustment value that is obtained by the gain adjustment unit. Generated Each time the gain adjustment value is repeatedly added to the corresponding gain adjustment value on the line memory, the M pieces of pixel data adjacent in the vertical direction are input from the document reading unit. And a vertical reduction unit that generates vertical reduction pixel data obtained by averaging the pixel data.

  In this image processing apparatus, every time N pieces of pixel data adjacent in the horizontal direction are input from the document reading unit, the N pieces of pixel data are averaged to generate horizontally reduced pixel data. A gain adjustment value is generated as a quotient divided by the value. Each time a gain adjustment value is generated by the gain adjustment unit, the gain adjustment value is repeatedly added to the corresponding gain adjustment value on the line memory, and M pixel data adjacent in the vertical direction from the document reading unit Each time is input, vertical reduced pixel data is generated by averaging the M pixel data. According to such a configuration, when the original image generated by optical reading of the original is reduced, only the line memory is used as the memory for temporarily storing the pixel data, so that the pixel data is held in units of one image. The manufacturing cost can be reduced compared to the case of using a frame memory. In particular, since the gain adjustment value obtained from the horizontally reduced pixel data obtained by averaging the N pixel data adjacent in the horizontal direction is held in the line memory, the pixel data input from the document reading unit is held as it is. Thus, the storage capacity of the line memory can be reduced. In addition, since the gain adjustment value generated as a quotient obtained by dividing the horizontally reduced pixel data by the predetermined value is held, it is possible to suppress an increase in the bit width of the data storage area in the line memory.

  In addition to the above-described configuration, the image processing apparatus according to a second aspect of the present invention includes a register in which the horizontal reduction unit holds the pixel data, an adder that adds two or more pixel data adjacent in the horizontal direction, and a bit A shifter that shifts the position to obtain a quotient obtained by dividing the addition result of N pixel data by the adder by N and outputs the result as the horizontally reduced pixel data is configured. According to such a configuration, since the N pixel data adjacent in the horizontal direction are added and then divided by the shifter, the average of the pixel data is larger than when the plurality of pixel data are added after dividing by the shifter. The error due to the conversion can be suppressed.

  According to a third aspect of the present invention, in addition to the above-described configuration, the line memory includes a first line memory and a second line memory, and the vertical reduction unit includes any of the first line memory and the second line memory. While the reduced image is read from one of the line memories and output to the image display unit, the vertically reduced pixel data is generated using the other line memory. According to such a configuration, while the reduced image is read from one line memory, vertical reduced pixel data is generated using the other line memory, and during the period when the reduced image is read from the line memory. Since the generation of the vertically reduced pixel data does not need to be stopped, the time required for the original image reduction process can be shortened.

  An image processing apparatus according to a fourth aspect of the present invention includes an original reading unit that generates an original image by optical reading of an original and sequentially outputs binary pixel data; An image reduction unit that generates a reduced image by reducing the image to 1 / M (M is an integer of 2 or more) in the vertical direction, and an image display unit that displays the reduced image. In the image processing device, the image reduction unit generates horizontal reduced pixel data obtained by adding the N pixel data every time the N pixel data adjacent in the horizontal direction are input from the document reading unit. A horizontal reduction unit that generates a gain adjustment value by multiplying the horizontal reduction pixel data by a predetermined value corresponding to N, M, and the bit width of the output pixel data, and the gain adjustment value. Line memo to hold Each time a gain adjustment value is generated by the gain adjustment unit, the gain adjustment value is repeatedly added to the corresponding gain adjustment value on the line memory, and M pieces of M adjacent adjacently in the vertical direction from the document reading unit are repeated. And a vertical reduction unit that generates vertical reduction pixel data by averaging the M pixel data each time the pixel data is input.

  In this image processing apparatus, every time N pieces of pixel data adjacent in the horizontal direction are input from the document reading unit, the N pieces of pixel data are added to generate horizontal reduced pixel data, and the horizontal reduced pixel data is predetermined. The value is multiplied to generate a gain adjustment value. Each time a gain adjustment value is generated by the gain adjustment unit, the gain adjustment value is repeatedly added to the corresponding gain adjustment value on the line memory, and M pixel data adjacent in the vertical direction from the document reading unit Each time is input, vertical reduced pixel data is generated by averaging the M pixel data. According to such a configuration, when the original image generated by optical reading of the original is reduced, only the line memory is used as the memory for temporarily storing the pixel data, so that the pixel data is held in units of one image. The manufacturing cost can be reduced compared to the case of using a frame memory. In particular, since the gain adjustment value obtained from the horizontally reduced pixel data obtained by adding N pieces of pixel data adjacent in the horizontal direction is held in the line memory, the pixel data input from the document reading unit is held as it is. The storage capacity of the line memory can be reduced.

  According to the image processing apparatus of the present invention, when reducing an original image generated by optical reading of an original, a line memory is used as a memory for temporarily storing pixel data, so that pixel data is held in units of one image. The manufacturing cost can be reduced compared to the use of the frame memory. In particular, the gain adjustment value obtained from the horizontally reduced pixel data averaged for N pieces of pixel data adjacent in the horizontal direction is held in the line memory, so that the pixel data input from the document reading unit is held as it is. Thus, the storage capacity of the line memory can be reduced. In addition, since the gain adjustment value generated as a quotient obtained by dividing the horizontally reduced pixel data by the predetermined value is held, it is possible to suppress an increase in the bit width of the data storage area in the line memory.

  In addition, while the reduced image is read from one line memory, vertical reduced pixel data is generated using the other line memory, and during the period when the reduced image is read from the line memory, the vertical reduced pixel data is generated. Since it is not necessary to stop the generation, the time required for the original image reduction process can be shortened.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing an example of a schematic configuration of an image processing apparatus according to Embodiment 1 of the present invention. The image processing apparatus 1 includes an image scanner 2, an image reduction unit 3, and an image display unit 4, and performs an operation of reducing an original image read by the image scanner 2 and displaying it on the LCD 13.

  The image scanner 2 is a document reading unit that generates an original image by optical reading of a document and sequentially outputs pixel data. The image scanner 2 receives a light source device that irradiates light on the document and reflected light from the document to obtain a received light amount. It comprises an image sensor that generates corresponding pixel data, a scanning device that scans the reading position in the horizontal direction and the vertical direction, and the like.

  The pixel data is monochrome data having a predetermined bit width, for example, 8 bits (256 gradations), and is output from the image scanner 2 as data for each pixel adjacent in the horizontal scanning direction. Here, the pixel data output from the image scanner 2 is described below as 8-bit monochrome data, but a color image may be output as an original image. When a color image is reduced, it is processed as multi-value data for each RGB.

  The image reduction unit 3 performs an operation of generating a reduced image in which the image size of the original image is reduced by averaging pixel data sequentially input from the image scanner 2. Specifically, the reduced image is generated by reducing 1 / N (N is an integer of 2 or more) in the horizontal direction and 1 / M (M is an integer of 2 or more) in the vertical direction, An operation for sequentially outputting the reduced pixel data is performed.

  The image display unit 4 includes a display memory 11, a display controller 12, and an LCD 13, and performs an operation for displaying a reduced image input from the image reduction unit 3 on the LCD 13. The display memory 11 is a memory, for example, a VRAM that holds bitmap format image data in association with the pixels on the LCD 13, and holds a reduced image input from the image reduction unit 3 in units of one image. .

  The display controller 12 controls the LCD 13 based on the image data on the display memory 11 and performs an operation for displaying a reduced image. The LCD 13 is a panel display in which a large number of pixels are arranged in a matrix.

  Here, the number of pixels A1 in the horizontal direction and the number of pixels B1 in the vertical direction on the LCD 13 are respectively compared with the maximum number of pixels A2 in the horizontal scanning direction and the maximum number of pixels B2 in the vertical scanning direction that can be read by the image scanner 2. It shall be small. For example, while the LCD 13 is a VGA size display with A1 = 640 and B1 = 480, the maximum number of pixels that can be read is about A2 = 2560 and B2 = 1808.

  FIG. 2 is a block diagram illustrating a configuration example of a main part of the image processing apparatus 1 in FIG. 1, and illustrates an example of a functional configuration in the image reduction unit 3. The image reduction unit 3 includes a horizontal reduction unit 20, a gain adjustment unit 30, a vertical reduction unit 40, a first line memory 43, and a second line memory 44.

  The horizontal reduction unit 20 generates horizontal reduced pixel data by averaging N pieces of pixel data adjacent in the horizontal direction for pixel data sequentially input as an original image from the image scanner 2, and outputs the horizontal reduced pixel data to the gain adjustment unit 30. The operation to be performed. The generation of horizontally reduced pixel data by averaging the pixel data is performed on the N pixel data every time N pixel data adjacent in the horizontal direction are input from the image scanner 2.

  Such a horizontal reduction unit 20 includes, for example, a register that holds pixel data input from the image scanner 2, an adder that adds a plurality of pixel data adjacent in the horizontal direction, and the bit position by shifting the bit position. A shifter that obtains a quotient obtained by dividing the addition result of N pieces of pixel data by the adder by N and outputs the result as horizontal reduced pixel data is used.

Here, the horizontal reduction unit 20, the primary shift register 21, a selector 22, made from the adder 23, the shifter 24 and the secondary shift register 25, it is assumed N are integers is represented in the form of ^{2 k.} The primary shift register 21 temporarily stores the pixel data sequentially input from the image scanner 2 for each pixel is the register for outputting in a lump N ₁ pieces of pixel data horizontally adjacent to the adder 23 .

The adder 23 is a circuit element that adds N ₁ pieces of pixel data input from the primary shift register 21 and outputs the addition result to the shifter 24. The shifter 24 is a circuit element that obtains a quotient obtained by dividing the addition result of N ₁ pixel data by N ₁ by shifting the bit position. Here, when the result of adding N ₁ pixel data is divided by N ₁ and a fraction occurs after the decimal point, the fraction after the decimal point is rounded down. Alternatively, processing may be performed so as to round up when the fraction is 0.5 or more and round down when the fraction is less than 0.5. That is, the pixel data output from the shifter 24 is an 8-bit integer value.

The secondary shift register 25 is a register that temporarily stores pixel data sequentially input for each pixel from the shifter 24 and outputs N ₂ pieces of pixel data adjacent in the horizontal direction to the selector 22 at a time.

  The selector 22 is a circuit element disposed between the primary shift register 21 and the adder 23, and is either pixel data input from the primary shift register 21 or pixel data input from the secondary shift register. Is selectively output to the adder 23.

In the adder 23, when N ₁ pieces of pixel data are input from the primary shift register 21, N ₁ pieces of pixel data are added, and the addition result is output to the shifter 24. When N ₂ pieces of pixel data are input, an operation of adding the N ₂ pieces of pixel data and outputting the addition result to the shifter 24 is performed.

Further, the shifter 24, when N ₁ pieces of pixel data are added to obtain the quotient obtained by dividing the addition result of the N ₁ pieces of pixel data in N _1, and outputs the result of operation to the secondary shift registers 25 , N ₂ pieces of pixel data are added, a quotient obtained by dividing the addition result of N ₂ pieces of pixel data by N ₂ is obtained, and the operation result is obtained by N (N = N ₁ × N ₂ ) An operation of outputting the pixel data to the gain adjusting unit 30 as horizontally reduced pixel data obtained by averaging the pieces of pixel data is performed.

The operation of adding N ₂ pixel data and outputting the quotient obtained by dividing the addition result by N ₂ to the gain adjustment unit 30 is to add N ₁ pixel data and divide the addition result by N ₁ . the operation of outputting the quotient to the secondary shift register 25 is performed every time the repeated _twice N.

Here, from the viewpoint of simplifying the configuration of the shifter 24, it is assumed that N ₁ = N ₂ . For example, when N ₁ = N ₂ = 4, the original image is reduced in the horizontal scanning direction at a reduction ratio of 1/16, and horizontal reduced pixel data is generated by averaging 16 pieces of pixel data adjacent in the horizontal direction. .

  In the averaging process, horizontal reduced pixel data may be generated from N pieces of pixel data by calculation using a weighting coefficient. For example, when the horizontal reduction ratio is 1/3, three pixel data may be averaged at a ratio of 1: 2: 1.

  Further, an average value of pixel data of the number of pixels overlapped with the reduced blocks before and after the central reduced block may be calculated according to the horizontal reduction rate to obtain horizontal reduced pixel data. . For example, when the horizontal reduction ratio is 1/4, in addition to the four pixels of the central reduced block, the rear two pixels in the immediately preceding adjacent block and the previous two pixels in the immediately adjacent block are combined. Alternatively, the average value of the pixel data for eight pixels may be calculated and used as the horizontally reduced pixel data.

  The gain adjusting unit 30 is a circuit element that adjusts the gain of the horizontally reduced pixel data input from the horizontal reducing unit 20, and obtains a quotient obtained by dividing the horizontally reduced pixel data by a predetermined value to generate a gain adjustment value. An operation of outputting to the reduction unit 40 is performed. For example, the gain adjusting unit 30 includes a shifter that obtains a quotient obtained by dividing the horizontally reduced pixel data by a predetermined value by shifting the bit position. The predetermined value is determined in advance according to the reduction ratio in the vertical scanning direction and the bit width of the output pixel data.

Here, since the reduction ratio in the vertical scanning direction is 1 / M, the gain adjustment unit 30 obtains a quotient obtained by dividing the horizontal reduction pixel data input from the horizontal reduction unit 20 by M, and uses the vertical as a gain adjustment value. Assume that the data is output to the reduction unit 40. M is an integer represented in the form of 2 ^k .

  The first line memory 43 and the second line memory 44 are both line memories that hold gain adjustment values, and hold image data in units of horizontal pixel columns. These line memories 43 and 44 are constituted by SRAMs or registers.

  The vertical reduction unit 40 includes an adder 41 and a memory controller 42, and generates vertical reduction pixel data by averaging the M pixel data adjacent in the vertical direction with respect to the gain adjustment value input from the gain adjustment unit 30. The operation of outputting the reduced image to the image display unit 4 is performed.

  Specifically, every time the gain adjustment value is generated by the gain adjustment unit 30, an operation of repeatedly adding the gain adjustment value to the corresponding gain adjustment value on the line memories 43 and 44 is performed. Each time M pieces of pixel data adjacent in the vertical direction are input from the image scanner 2, vertical reduced pixel data obtained by averaging the M pieces of pixel data is generated, and the reduced images are stored in the line memories 43 and 44. A write operation is performed.

  The memory controller 42 is a circuit element that reads and writes pixel data from and to the line memories 43 and 44. In this memory controller 42, each time a gain adjustment value is input from the gain adjustment unit 30 for a pixel row in the horizontal scanning direction in the original image, the gain adjustment value is stored in the line memories 43 and 44 while changing the data storage area. The operation of writing to is performed.

  Then, whenever a gain adjustment value is input from the gain adjustment unit 30 to the adder 41 for the next pixel column, the gain adjustment value corresponding to the gain adjustment value is read from the line memories 43 and 44 and sent to the adder 41. The output operation is performed, and the addition result of these gain adjustment values by the adder 41 is written in the line memories 43 and 44 as an accumulated value.

  That is, in the adder 41, the gain adjustment value read from the line memories 43 and 44 by the memory controller 42 every time the gain adjustment value is input from the gain adjustment unit 30 for the next pixel row. The operation of adding the values is performed.

  In the vertical reduction unit 40, while the reduced image is read from one of the first line memory 43 and the second line memory 44 and output to the image display unit 4, the other line memory is used. Generation of vertically reduced pixel data is performed. That is, the vertical reduction unit 40 performs so-called double buffering using the line memories 43 and 44 for writing the gain adjustment value input from the gain adjustment unit 30 and reading the vertical reduction pixel data to the image display unit 4, respectively. Done.

  FIGS. 3A to 3D are diagrams showing an example of the operation of the image reduction unit 3 in FIG. 2, in which pixel data sequentially input from the image scanner 2 is reduced in the horizontal reduction ratio ¼ and the vertical reduction. A state in which vertical reduced pixel data is generated by reducing in the horizontal and vertical directions at a rate of 1/4 is schematically shown.

  In FIG. 3A, horizontal reduced pixel data is generated by averaging four pixel data for the input image data of the k-th line input as an original image from the image scanner 2, and obtained by gain adjustment. A state in which the gain adjustment value is stored in the line memory is shown. The input image data of the k-th line is composed of 2560 pixel data adjacent in the horizontal scanning direction, and is subjected to reduction processing by being divided into reduced blocks composed of continuous four pixel data.

  Here, the pixel line of the k-th line in the original image is called a reduction process start line, the pixel line of the (k + 3) line is called an end line, and the four pixel lines from the start line to the end line are reduced. Reduction processing in the vertical scanning direction is performed as a block.

  Also, in the previous reduced block, that is, the reduced block whose end line is the pixel column of the (k−1) th line, the vertical reduced pixel data is determined, and the vertical reduced pixel data is stored in one line memory (memory). While reading from B) to the output device, that is, the image display unit 4, the memory access is switched to the other line memory (memory A), and the reduction process for the current reduced block is started.

  First, for each input pixel data (8-bit multi-value data) on the k-th line, an averaging process is performed every four pixels at a horizontal reduction ratio of 1/4. Specifically, pixel data of 0, 32, 64, and 96 are averaged for the first reduced block in the horizontal scanning direction, and horizontal reduced data “48” is generated. The horizontal reduction data “48” is divided by 4 of the number of lines for gain adjustment, and a gain adjustment value “12” is generated. Since the pixel line of the k-th line is the start line of the current reduced block, the gain adjustment value “12” is written as it is in the first pixel of the memory A.

  Next, for the second reduced block in the horizontal scanning direction, the pixel data of 128, 160, 192, and 224 are averaged to generate horizontal reduced data “176”. The horizontally reduced data “176” is divided by the number of lines of 4 for gain adjustment, and a gain adjustment value “44” is generated and written to the second pixel of the memory A as it is.

  Such reduction processing in the horizontal scanning direction is repeated up to the last pixel in the pixel line of the k-th line.

  In FIG. 3B, horizontal reduced pixel data is generated by averaging four pixel data for the input image data on the (k + 1) -th line, and the gain adjustment value obtained by gain adjustment is stored in the line memory. The state of doing is shown. For each input pixel data of the (k + 1) th line, an averaging process is performed for every four pixels at a horizontal reduction ratio of 1/4 as in the kth line. Specifically, the pixel data of 224, 0, 32, and 64 are averaged for the first reduced block in the horizontal scanning direction, and horizontal reduced data “80” is generated. The horizontally reduced data “80” is divided by 4 of the number of lines for gain adjustment, and a gain adjustment value “20” is generated. Then, the gain adjustment value “20” and the accumulated value “12” read from the memory A are added, and a new accumulated value “32” is written to the first pixel.

  Next, for the second reduced block in the horizontal scanning direction, the 96, 128, 160, and 192 pixel data are averaged, and horizontal reduced data “144” is generated. This horizontal reduction data “144” is divided by the number of lines of 4 for gain adjustment, and a gain adjustment value “36” is generated. Then, the gain adjustment value “36” and the accumulated value “44” read from the memory A are added, and a new accumulated value “80” is written to the second pixel.

  Such reduction processing in the horizontal scanning direction is repeated up to the last pixel in the pixel column of the (k + 1) th line.

  In FIG. 3C, for the input image data on the (k + 2) -th line, horizontal reduced pixel data is generated by averaging the four pixel data, and the gain adjustment value obtained by gain adjustment is stored in the line memory. The state of doing is shown. Further, in FIG. 3D, horizontal reduced pixel data is generated by averaging four pixel data for the input image data on the (k + 3) line, and the gain adjustment value obtained by gain adjustment is stored in the line memory. Is shown in FIG.

  Similarly to the (k + 1) line, each input pixel data of the (k + 2) line and the (k + 3) line is averaged every four pixels at a horizontal reduction ratio of 1/4 to generate horizontal reduced data. The Then, a gain adjustment value is generated from the horizontal reduced data, and an addition value of the gain adjustment value and the accumulated value read from the memory A is written to the first pixel. Such reduction processing in the horizontal scanning direction is repeated up to the last pixel in the pixel row of the (k + 3) th line.

  With respect to the pixel row of the (k + 3) th line in the original image, the line data of the reduced image is determined when the writing of the cumulative addition value of the gain adjustment value is completed.

  According to the present embodiment, when the original image is reduced, only the line memories 43 and 44 are used as the memory for temporarily storing the pixel data. Therefore, the frame memory that holds the pixel data for each image is used. The manufacturing cost can be reduced compared to the above. Particularly, since the gain adjustment value obtained from the horizontally reduced pixel data obtained by averaging the N pixel data adjacent in the horizontal direction is held in the line memories 43 and 44, the pixel data input from the image scanner 2 is held as it is. Compared to the above, the storage capacity of the line memories 43 and 44 can be reduced. In addition, since the gain adjustment value generated as a quotient obtained by dividing the horizontally reduced pixel data by the predetermined value is held, it is possible to suppress an increase in the bit width of the data storage area in the line memories 43 and 44.

  Further, since N pixel data adjacent in the horizontal direction are added and then divided by the shifter 24, the error due to averaging of pixel data is suppressed as compared with adding a plurality of pixel data after dividing by the shifter. can do. Further, while the reduced image is read from one line memory, vertical reduced pixel data is generated using the other line memory, and during the period when the reduced image is read from the line memory, the vertical reduced pixel data is generated. Since it is not necessary to stop the generation, the time required for the original image reduction process can be shortened.

Embodiment 2. FIG.
In the first embodiment, an example in which a multi-value original image is reduced has been described. In contrast, in the present embodiment, a case where a binary original image is reduced will be described.

  FIG. 4 is a block diagram showing a configuration example of the main part of the image processing apparatus according to the second embodiment of the present invention, and shows an example of a functional configuration in the image reduction unit 50. The image reduction unit 50 includes a horizontal reduction unit 60, a gain adjustment unit 70, a vertical reduction unit 40, a first line memory 43, and a second line memory 44. The vertical reduction unit 40, the first line memory 43, and the second line memory 44 have the same configuration as that in the image reduction unit 3 in FIG.

  The horizontal reduction unit 60 adds N pieces of pixel data adjacent in the horizontal direction to the pixel data sequentially input as a binary original image from the image scanner 2 to generate horizontal reduction pixel data, and a gain adjustment unit The operation of outputting to 70 is performed. Specifically, it is configured by a register 62 that holds pixel data from the image scanner 2 and an adder 61 that adds N pieces of pixel data adjacent in the horizontal direction.

  The gain adjustment unit 70 is a circuit element that adjusts the gain of horizontal reduced pixel data input from the horizontal reduction unit 60, and generates a multi-value gain adjustment value by multiplying the horizontal reduced pixel data by a predetermined value. An operation of outputting to the vertical reduction unit 40 is performed.

  The gain adjusting unit 70 is configured by, for example, a shifter that multiplies the horizontally reduced pixel data by a predetermined value by shifting the bit position. The predetermined value is determined in advance according to each reduction ratio in the horizontal scanning direction and the vertical scanning direction and the bit width of the output pixel data.

For example, when the reduction ratio in the horizontal scanning direction is 1 / N, the reduction ratio in the vertical scanning direction is 1 / M, and the bit width of the output pixel data is k (k is an integer of 2 or more) bits, the horizontal reduction unit 60 The input horizontal reduced pixel data is multiplied by 2 ^k / (N × M), and the multiplication result is output to the vertical reduction unit 40 as a gain adjustment value. Depending on the values of N, M, and k, the predetermined value 2 ^k / (N × M) may be less than 1, and in this case, the horizontal reduced pixel data is (N × M). / 2 ^k the result of division by is the gain adjustment value.

  FIGS. 5A to 5D are diagrams showing an example of the operation of the image reduction unit 50 in FIG. 4. Pixel data sequentially input from the image scanner 2 is reduced in the horizontal reduction ratio 1/4 and the vertical reduction. A state in which vertical reduced pixel data is generated by reducing in the horizontal and vertical directions at a rate of 1/4 is schematically shown.

  FIG. 5A shows a gain obtained by adjusting horizontal reduced pixel data by adding four pieces of pixel data to the input image data of the k-th line input as an original image from the image scanner 2 and performing gain adjustment. A state in which the adjustment value is stored in the line memory is shown. The input image data of the k-th line is composed of 2560 pixel data adjacent in the horizontal scanning direction, and is subjected to reduction processing by being divided into reduced blocks composed of continuous four pixel data.

  First, for each input pixel data (1-bit binary data) on the k-th line, an addition process is performed every four pixels at a horizontal reduction ratio of 1/4. Specifically, pixel data of 0, 0, 0, 0 is added to the first reduced block in the horizontal scanning direction to generate horizontal reduced data “0”. This horizontal reduction data “0” is multiplied by a value 16 obtained by dividing the number of gradations 256 of the output pixel data by the total number of pixels 16 of the reduction block for gain adjustment, and a gain adjustment value “0” is generated. . Since the pixel line of the k-th line is the start line of the current reduced block, the gain adjustment value “0” is directly written into the first pixel of the memory A.

  Next, for the second reduced block in the horizontal scanning direction, the pixel data of 1, 1, 1, 1 are added to generate horizontal reduced data “4”. The horizontal reduction data “4” is multiplied by a value 16 obtained by dividing the number of gradations 256 of the output pixel data by the total number of pixels 16 of the reduction block for gain adjustment, and a gain adjustment value “64” is generated. It is written in the second pixel of the memory A as it is.

  Such reduction processing in the horizontal scanning direction is repeated up to the last pixel in the pixel line of the k-th line.

  In FIG. 5B, horizontal reduced pixel data is generated by adding four pieces of pixel data for the input image data on the (k + 1) th line, and the gain adjustment value obtained by gain adjustment is stored in the line memory. The situation is shown. For each input pixel data of the (k + 1) th line, an addition process is performed every four pixels at a horizontal reduction rate of 1/4 as in the kth line. Specifically, pixel data of 1, 0, 0, 0 is added to the first reduced block in the horizontal scanning direction, and horizontal reduced data “1” is generated. This horizontal reduction data “1” is multiplied by a value 16 obtained by dividing the number of gradations 256 of the output pixel data by the total number of pixels 16 of the reduction block for gain adjustment, and a gain adjustment value “16” is generated. . Then, the gain adjustment value “16” and the accumulated value “0” read from the memory A are added, and a new accumulated value “16” is written to the first pixel.

  Next, pixel data of 0, 1, 1, 1 is added to the second reduced block in the horizontal scanning direction to generate horizontal reduced data “3”. The horizontal reduction data “3” is multiplied by a value 16 obtained by dividing the number of gradations 256 of the output pixel data by the total number of pixels 16 of the reduction block for gain adjustment, and a gain adjustment value “48” is generated. . Then, the gain adjustment value “48” and the accumulated value “64” read from the memory A are added, and a new accumulated value “112” is written to the second pixel.

  Such reduction processing in the horizontal scanning direction is repeated up to the last pixel in the pixel column of the (k + 1) th line.

  In FIG. 5C, horizontal reduced pixel data is generated by adding four pieces of pixel data for the input image data on the (k + 2) -th line, and the gain adjustment value obtained by gain adjustment is stored in the line memory. The situation is shown. Further, in FIG. 5D, for the input image data of the (k + 3) line, horizontal reduced pixel data is generated by adding four pieces of pixel data, and the gain adjustment value obtained by gain adjustment is stored in the line memory. The storage is shown.

  For each input pixel data of the (k + 2) line and the (k + 3) line, addition processing is performed for every four pixels at a horizontal reduction ratio of 1/4 as in the (k + 1) line, and horizontal reduced data is generated. . Then, a gain adjustment value is generated from the horizontal reduced data, and an addition value of the gain adjustment value and the accumulated value read from the memory A is written to the first pixel. Such reduction processing in the horizontal scanning direction is repeated up to the last pixel in the pixel row of the (k + 3) th line.

  For the pixel column of the (k + 3) -th line in the original image, the line data of the reduced image is determined when the writing of the cumulative addition value of the gain adjustment value is completed.

  Even with such a configuration, the gain adjustment value obtained from the horizontally reduced pixel data obtained by adding the N pixel data adjacent in the horizontal direction is held in the line memories 43 and 44, so that the pixel data input from the image scanner 2 is stored. As compared with the case where the line memory 43 is held as it is, the storage capacity of the line memories 43 and 44 can be reduced.

1 is a block diagram showing an example of a schematic configuration of an image processing apparatus according to Embodiment 1 of the present invention. FIG. 2 is a block diagram illustrating a configuration example of a main part of the image processing apparatus 1 in FIG. 1, in which an example of a functional configuration in the image reduction unit 3 is illustrated. FIG. 3 is a diagram illustrating an example of the operation of the image reduction unit 3 in FIG. 2, schematically illustrating how vertical reduced pixel data is generated by reducing pixel data in the horizontal and vertical directions. FIG. 5 is a block diagram showing an example of the configuration of the main part of an image processing apparatus according to Embodiment 2 of the present invention, in which an example of a functional configuration in the image reduction unit 50 is shown. FIG. 5 is a diagram illustrating an example of the operation of the image reducing unit 50 in FIG. 4, schematically illustrating how vertical reduced pixel data is generated by reducing pixel data in the horizontal and vertical directions.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image processing apparatus 2 Image scanner 3 Image reduction part 4 Image display part 11 Display memory 12 Display controller 13 LCD
20 horizontal reduction unit 21 primary shift register 22 selector 23 adder 24 shifter 25 secondary shift register 30 gain adjustment unit 40 vertical reduction unit 41 adder 42 memory controller 43 first line memory 44 second line memory 50 image reduction unit 60 Horizontal reduction unit 61 Adder 62 Register 70 Gain adjustment unit

Claims (4)

An original image is generated by optical reading of an original, and an original reading unit that sequentially outputs pixel data, and the original image is reduced to 1 / N (N is an integer of 2 or more) in the horizontal direction and 1 in the vertical direction. / M (M is an integer equal to or greater than 2), an image reduction unit that generates a reduced image and an image display unit that displays the reduced image,
The image reduction unit includes a horizontal reduction unit that generates horizontal reduced pixel data by averaging the N pieces of pixel data every time N pieces of pixel data adjacent in the horizontal direction are input from the document reading unit;
A gain adjustment unit that generates a gain adjustment value by obtaining a quotient obtained by dividing the horizontal reduced pixel data by a predetermined value;
A line memory for holding the gain adjustment value;
Each time the gain adjustment value is generated by the gain adjustment unit, the gain adjustment value is repeatedly added to the corresponding gain adjustment value on the line memory, and the M number of the adjacent ones in the vertical direction from the document reading unit is repeated. An image processing apparatus comprising: a vertical reduction unit that generates vertical reduction pixel data obtained by averaging the M pieces of pixel data each time pixel data is input. A register for holding the pixel data;
An adder for adding two or more pixel data adjacent in the horizontal direction;
2. The shifter according to claim 1, further comprising: a shifter that obtains a quotient obtained by dividing the addition result of N pieces of pixel data by the adder by N by shifting a bit position and outputs the result as the horizontally reduced pixel data. Image processing apparatus. The line memory comprises a first line memory and a second line memory,
While the vertical reduction unit reads the reduced image from one of the first line memory and the second line memory and outputs the reduced image to the image display unit, the other line memory is used to The image processing apparatus according to claim 1, wherein the image processing apparatus generates vertical reduced pixel data. An original image is generated by optically reading an original, and an original reading unit that sequentially outputs binary pixel data; and the original image is reduced to 1 / N (N is an integer of 2 or more) in the horizontal direction and vertically An image processing apparatus having an image reduction unit that generates a reduced image by reducing the image to 1 / M (M is an integer of 2 or more) in a direction, and an image display unit that displays the reduced image.
The image reduction unit includes a horizontal reduction unit that generates horizontal reduced pixel data obtained by adding the N pieces of pixel data each time N pieces of pixel data adjacent in the horizontal direction are input from the document reading unit;
A gain adjustment unit that generates a gain adjustment value by multiplying the horizontal reduced pixel data by a predetermined value determined in accordance with N, M and the bit width of the output pixel data;
A line memory for holding the gain adjustment value;
Each time the gain adjustment value is generated by the gain adjustment unit, the gain adjustment value is repeatedly added to the corresponding gain adjustment value on the line memory, and the M number of the adjacent ones in the vertical direction from the document reading unit is repeated. An image processing apparatus comprising: a vertical reduction unit that generates vertical reduction pixel data obtained by averaging the M pieces of pixel data each time pixel data is input.

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