JP4989074B2 - Semiconductor device - Google Patents

Description

The present invention relates to a MOS structure field effect semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device constituting a semiconductor integrated circuit such as a voltage regulator, a switching regulator, a voltage detector, etc. It relates to a manufacturing method. In addition, the present invention relates to a semiconductor integrated circuit device through which a plurality of voltages are input and output and a manufacturing method thereof.

Conventionally, a plurality of power supply voltages have been applied to a single semiconductor device or a plurality of output voltages have been output. This requires that another semiconductor device having a different process be formed on the same substrate. This complicates the device configuration and process flow of semiconductor devices, increases the number of management elements and processes, and increases production TAT.
(Turn Around Time) increased and production costs increased.

In order to eliminate such harmful effects, it is well known to use a manufacturing method such as dual gate and application of a channel stopper to a high voltage element.

  This manufacturing method will be described below with reference to the drawings.

9 to 11 are schematic sectional views in order of manufacturing steps of a conventional method for manufacturing a semiconductor device.

Pwell 2 and Nwell 16 are formed in the vicinity of the surface of P-type semiconductor substrate 1 (hereinafter referred to as Psub1) using a photo process, an ion implantation process, and a thermal diffusion process, and then a thick oxide film 19 for element isolation, an N-type channel stopper 15 and P Mold channel stopper 14 with LOCOS
The oxide film 20 is formed by thermal oxidation, and a photoresist 5 is formed on the channel region of a region that will be a high-voltage driving element in the future, and wet etching is performed. The thin oxide film in other regions is removed. Thus, the structure of FIG. 9 is obtained.
Subsequently, after removing the photoresist 5, a high voltage thick gate oxide film 22 and a low voltage thin gate oxide film 23 are formed again by thermal oxidation. Thus, the structure of FIG. 10 is obtained.

Here, the thickness of the gate oxide film is such that the electric field applied to the gate oxide film is 4 MV / cm.
Set so as not to exceed.

Next, a Poly-Si gate 3 is formed using a CVD process, a photo process, an etching process, and the like, and an N + source 11, an N + drain 10, and a P + source 1 are provided for each element.
8. P + drain 17 is formed using a photo process, an ion implantation process, and the like. Thus, the structure of FIG. 11 is obtained.

Thereafter, although not shown, an interlayer insulating film, a contact hole, a metal wiring, an external connection PAD, and a protective film are formed using a normal semiconductor manufacturing process. Thus, the conventional semiconductor device is completed.

Further, as a semiconductor device using a dual gate process, there is a non-volatile memory element having a single poly structure.

  This manufacturing method will be described below.

  FIG. 18 is a schematic cross-sectional view of a conventional semiconductor device.

After the Pwell 202 is formed near the surface of the semiconductor substrate 201 using a photo process, an ion implantation process, and a thermal diffusion process, the element isolation oxide film 205 and the channel stopper 20 are formed.
9 is formed using a LOCOS method, an ion implantation process, a photo process, etc., and a tunnel drain region 204 is formed using a photo process, an ion implantation process, and the gate oxide film 20.
6 is formed by thermal oxidation, a photoresist is formed on a channel region other than a region to be a future tunnel oxide film 207, and a future tunnel oxide film 2 is formed by wet etching.
The gate oxide film in the region to be 07 is removed. Subsequently, after removing the photoresist, a tunnel oxide film 207 is formed again by thermal oxidation. Next, the select gate electrode 213 and the floating gate electrode 208 are formed using a CVD process, a photo process, an etching process, etc., and the N + regions 203 are ionized in a self-aligned manner on the select gate electrode 213 and the floating gate electrode 208, respectively. It is formed using an implantation process or the like. Thus, the structure of FIG. 18 is obtained.

Thereafter, although not shown, an interlayer insulating film, a contact hole, a metal wiring, an external connection PAD, and a protective film are formed using a normal semiconductor manufacturing process. Thus, the conventional semiconductor device is completed.

However, in a conventional semiconductor device having a source / drain structure in which a thick element isolation oxide film is arranged at both ends of a gate electrode , a high voltage element uses a channel stopper formed by a LOCOS method and an ion implantation process as a source and drain. Therefore, it has the following structural problems.

As shown in FIGS. 9 to 11, the high-voltage elements 23 and 24 use the source and drain formed by the LOCOS method and the ion implantation process, and thus have a drawback that the element size is structurally increased. Was.

Here, the LOCOS method and the ion implantation process will be described. In general, in the LOCOS method, a nitride film having a high heat-resistant oxidation masking property is formed in a region that will become an active region in the future by using a photo process and an etching process, and an N-type channel stopper and a P-type channel stopper in the future. After forming the impurity regions of the p-type and p-type using the photo process and the ion implantation process, the element isolation thick oxide film and the n-type channel stopper and the p-type channel stopper are thermally oxidized and thermally diffused (for example, 1100 degrees, using about 3 hours thermal oxidation diffusion process) is formed, is that the manufacturing method of forming by removing the oxide film on the element isolation region and the active region and a nitrided layer and the active region.

As described above, when the N-type channel stopper and the P-type channel stopper formed by such a LOCOS method or the like are also used for the source and drain of a high-voltage element, it is difficult to reduce the size of the element structure. As shown in FIG. 11, a thick oxide film 19 that also serves as an element isolation region is required on both sides of the high-voltage thick gate oxide film 22, and the element size including the channel region, the source region, and the drain region is increased. It was difficult to suppress.

Further, in the conventional semiconductor device and the manufacturing method of the semiconductor device, two types of gate oxide films are required according to the applied voltage, and the following manufacturing problems are involved.

Since the high-voltage thick gate oxide film 22 is formed by two thermal oxidation processes, as shown in FIGS. 9 to 11, the variation in film thickness increases. This is because hydrogen peroxide containing ammonia is generally used in the pre-cleaning step of the second thermal oxidation step, and this cleaning solution partially etches and removes the oxide film surface when cleaning the oxide film surface. Therefore, the etching amount varies depending on the state of the cleaning solution, and the underlying oxide film thickness before the second thermal oxidation varies. As a result, the film thickness variation of the high-voltage thick gate oxide film 22 increases. That is. Such a variation causes the threshold voltage and drive current value of the high-voltage element to vary, degrading the characteristics of the semiconductor integrated circuit device, making it difficult to improve the accuracy of the characteristics of the semiconductor integrated circuit device. It was something to be made.

In addition, the nonvolatile memory element has a problem that the controllability of the film thickness is poor in the thick gate oxide film because of the structure in which the tunnel oxide film and the gate oxide film have different thicknesses. .

Therefore, the present invention uses the following means in order to solve the above problems.
A first step of forming a polycrystalline silicon gate near the surface of the P-type semiconductor substrate via a gate insulating film;
A second step of implanting oxygen ions in the vicinity of the surface of the polycrystalline silicon gate and the P-type semiconductor substrate to form an oxygen ion implanted region;
A third step of forming an oxide film by annealing the oxygen ion implantation region at a high temperature;
A fourth step of introducing N-type impurities into the gate electrode in a self-aligned manner to form an N-type impurity region and an N-type impurity introduced at a distance from the gate electrode to form a high-concentration N-type impurity region An insulated gate semiconductor device was formed using the fifth step.

In the first step of the manufacturing method of the insulated gate semiconductor device,
A step of sequentially forming a tungsten silicide and an oxide film on the polycrystalline silicon gate;
Patterning the polycrystalline silicon gate, the tungsten silicide, and the oxide film with the same mask to form the gate electrode;
An insulated gate semiconductor device was formed using

In the second step of the manufacturing method of the insulated gate semiconductor device,
An insulated gate semiconductor device was formed using a step of forming the oxygen ion implantation region in the vicinity of the gate oxide film in the polycrystalline silicon gate.

In the second step of the manufacturing method of the insulated gate semiconductor device,
An insulated gate semiconductor device was formed using a process in which the depth of the oxygen ion implantation region near the surface of the P-type semiconductor substrate was formed to be approximately equal to or less than the depth of the junction position of the N-type impurity region.

Next, a first step of forming a polycrystalline silicon gate near the surface of the P-type semiconductor substrate via a gate insulating film;
A second step of ion-implanting oxygen ions into a P-type semiconductor substrate below the polysilicon gate and into a P-type semiconductor substrate outside the polysilicon gate to form an oxygen ion implantation region;
A third step of forming an oxide film by annealing the oxygen ion implantation region at a high temperature;
A fourth step of introducing N-type impurities into the gate electrode in a self-aligned manner to form an N-type impurity region and an N-type impurity introduced at a distance from the gate electrode to form a high-concentration N-type impurity region An insulated gate semiconductor device was formed using the fifth step.

In the first step of the manufacturing method of the insulated gate semiconductor device,
A step of sequentially forming a tungsten silicide and an oxide film on the polycrystalline silicon gate;
Patterning the polycrystalline silicon gate, the tungsten silicide, and the oxide film with the same mask to form the gate electrode;
An insulated gate semiconductor device was formed using

In the second step of the manufacturing method of the insulated gate semiconductor device,
An insulated gate semiconductor device was formed using the step of forming the oxygen ion implantation region in the vicinity of the gate oxide film in the P-type semiconductor substrate.

In the second step of the manufacturing method of the insulated gate semiconductor device,
An insulated gate semiconductor device was formed using a process in which the depth of the oxygen ion implantation region near the surface of the P-type semiconductor substrate was formed to be equal to or less than the depth of the junction position of the N-type impurity region.

Further, in a MOS FET having a plurality of gate oxide films constituting a semiconductor integrated circuit device for driving a plurality of power supply voltages, both a polycrystalline silicon gate provided through a thick gate oxide film and a polycrystalline silicon gate are provided. Both an oxide film provided in the outer P-type semiconductor substrate, an N-type impurity region provided on the oxide film, a polycrystalline silicon gate provided via a thin gate oxide film, and a polycrystalline silicon gate An insulated gate semiconductor device having an N-type impurity region provided in the vicinity of the outer P-type semiconductor substrate surface was formed.

In the MOSFET, an insulated gate semiconductor device having the thick gate oxide film provided in the vicinity of the surface of the P type semiconductor substrate so as to protrude toward the P type semiconductor substrate was formed.

Also, a first step of selectively forming an oxygen ion implantation region in the vicinity of the surface of the P-type semiconductor substrate via an oxide film, and a second step of forming an oxide film for element isolation by annealing the oxygen ion implantation region at a high temperature. An insulated gate semiconductor device was formed using these steps.

In a MOS type FET having a plurality of conductivity types constituting a semiconductor integrated circuit device, the vicinity of the Pwell surface and the Nwell are formed near the surface of the semiconductor substrate via a gate oxide film.
A gate electrode provided near each surface, an element isolation oxide film provided in an element isolation region from the P-type semiconductor substrate to the vicinity of the P-type semiconductor substrate surface, and Pwell
An N-type impurity region provided in a self-alignment manner with respect to the gate electrode and the element isolation oxide film near the surface, and a P provided in a self-alignment manner with respect to the gate electrode and the element isolation oxide film in the vicinity of the Nwell surface. A semiconductor device having a type impurity region was formed.

According to the present invention, it is possible to fabricate a MOSFET with excellent cost performance. In particular, the present invention is an effective method for diversifying operating voltage voltages, high voltage driving, miniaturization and flattening of element isolation regions, high accuracy of nonvolatile memory elements, etc.

Although the present invention has been described mainly with respect to silicon-based semiconductor devices, it is obvious that the present invention can also be applied to semiconductor devices using other materials such as germanium, silicon carbide, and gallium arsenide. Furthermore, in the present invention, reducing the resistance of the gate electrode also plays an important role. In addition to the silicon gate mainly described in the present invention, a material that can be oxidized by oxygen ion implantation and annealing is used as the gate electrode. Also good. In the embodiment, the manufacturing process of an NMOSFET on a P-type semiconductor substrate has been described. However, for manufacturing a thin film transistor (TFT) using a polycrystalline or single crystal semiconductor film formed on an insulating substrate such as quartz or sapphire. It will also be apparent that the present invention can be applied.

As described so far, in the present invention, the oxygen ion implantation process and the annealing process are applied to the method of manufacturing a semiconductor device, and therefore, the miniaturization and high accuracy of the high voltage element are promoted.

  Embodiments of the present invention will be described below with reference to the drawings.

This embodiment shows a case where the present invention is applied to a high-voltage N-type MOSFET device and a low-voltage N-type MOSFET device formed on the same semiconductor substrate. The manufacturing method of this example is shown in FIG. First, as shown in FIGS. 1 to 4, a Pwell 2, an element isolation thick oxide film 19, and a polycrystalline silicon gate electrode 3 are provided on Psub 1 using a conventional integrated circuit manufacturing method.

The detailed manufacturing method is as follows. Boron ions are implanted near the surface of Psub1 and annealed at 1000 to 1175 ° C. for 3 to 20 hours to diffuse and redistribute boron ions, thereby forming Pwell 2 having an impurity concentration of about 1E16 cm −3. Subsequently, B + ions are implanted into a region patterned with a nitride film or the like, and LOCOS is performed.
The P-type channel stopper 14 and the field insulating film 26 are formed by the method.

Thereafter, ion implantation for controlling the threshold voltage into a desired channel region, formation of a gate oxide film 4 having a thickness of 10 to 30 nm by a thermal oxidation method, and a polysilicon film having a thickness of 100 to 500 nm by a low pressure CVD method or the like. A polysilicon film is formed by forming and ion implantation. Here, a tungsten silicide film having a thickness of about 100 to 200 nm is formed on the polysilicon film by sputtering or the like, and an oxide film having a thickness of about 100 to 300 nm is formed on the tungsten silicide film by low pressure CVD or the like. Sometimes it is done. Polysilicon film is then patterned to form Poly-Si
The gate 3 is formed. Here, there is a case where an oxide film is formed to a thickness of about 10 to 50 nm on the upper portion of the gate electrode 3, the side wall portion, the semiconductor substrate surface portion or the like by using a thermal oxidation method or a low pressure CVD method. The structure shown in FIG. 1 is obtained through the steps up to here.

Thereafter, as shown in FIG. 2, oxygen ion implantation is performed in the region near the gate oxide film 4 of the Poly-Si gate 3 in the region that will be a high-voltage element in the future and outside the both end portions of the Poly-Si gate 3. Then, oxygen ions are selectively ion-implanted into the P well 2 using the photoresist 5 to form an O ion implantation region 21. The acceleration energy of oxygen ion implantation here is set so that an oxygen ion concentration peak occurs in a region near the gate oxide film 4 of the Poly-Si gate 3. Further, the thickness of the Poly-Si gate 3 is such that the depth from the vicinity of the surface of the P well 2 of the O ion implantation region 21 in the P well 2 is P in the N − region 6 to be formed in the future.
It is desirable that the depth is set to be equal to or less than the junction depth from the vicinity of the well 2 surface.

Thereafter, an annealing process at a high temperature is performed. At this time, the O ion implantation region 21 in the Poly-Si gate 3 and the gate oxide film 4 become the same oxide film by annealing and a thick oxide film 20 is formed, and the O ion implantation region 21 in the Pwell 2 becomes an oxide film. Pwell2
Oxide film 7 buried in is formed.

On the other hand, an oxide film is not newly formed in the low voltage element region where oxygen ions are not implanted.

Then, N-regions 6 are formed shallower than the oxide film 7 by implanting N-type impurities into the Poly-Si gate 3 in a self-aligned manner. Also,
An N− region 6 is formed simultaneously in the low voltage element region. However, it is also possible to separate the N− region 6 concentration between the high voltage element and the low voltage element by using another mask.
Thus, the structure of FIG. 3 is obtained.

Next, the N + region 8 is formed by ion implantation of N-type impurities at a high concentration. The N + region 8 is simultaneously formed in both the high voltage element and the low voltage element. In any impurity region, the impurity concentration is about 1E21 cm −3. Thus, the structure of FIG. 4 is obtained.

Finally, although not shown, a phosphorus glass layer is formed as an interlayer insulator as in the case of manufacturing a conventional integrated circuit. For example, a low pressure CVD method may be used to form the phosphorus glass layer. As the material gas, monosilane SiH4, oxygen O2 and phosphine PH3 are used and reacted at 450 ° C.

Thereafter, a hole for forming an electrode is formed in the interlayer insulating film to form an aluminum electrode. Thus, the high-voltage N-type MOSFET device and the low-voltage N-type MOSF are formed on the same semiconductor substrate.
The ET device is completed.

In the semiconductor device thus obtained (FIG. 4), since the oxide film 7 is buried under the N− region 6 of the high voltage element, the N− region 6 used as the drain applies a high voltage to the drain. However, since the depletion layer does not spread downward, the short channel effect that hinders the short channel and high voltage driving of the transistor is suppressed, and a small high voltage driving element can be realized.

Furthermore, if the oxygen ion implantation process is made highly precise, a thick gate oxide film with little variation in film thickness can be formed even when a dual gate is used, and high precision of the semiconductor device can be realized.

Further, FIGS. 6 to 8 show sectional views in order of the manufacturing process of the semiconductor device when the oxygen ion implantation position is set in the vicinity of the gate oxide film 4 of the Pwell 2.

In this case, the semiconductor device of the present invention can be formed using a process similar to the process described in the description of FIGS. However, regarding the setting of the oxygen ion implantation energy, it is necessary to set the oxygen ion concentration peak in the vicinity of the gate oxide film 4 in the Pwell 2.

Up to this point, an N-type MOSFET device has been described, but a P-type MOSFET device can also be formed by a similar manufacturing method with the conductivity type reversed.

Furthermore, for complementary MOSFET devices (CMOS devices), N-type MOSF
It can be formed by combining the manufacturing method of the ET device and the manufacturing method of the P-type MOSFET device.

In the present invention, the oxygen ion implantation process and the annealing process are applied to a method of manufacturing a semiconductor device. So far, the downsizing and high accuracy of the high voltage element have been described. After that, an embodiment in which the present invention is applied to element isolation will be described.

  Embodiments of the present invention will be described below with reference to the drawings.

In this embodiment, an N-type MOSFET device and a P-type MO formed on the same semiconductor substrate.
The case where this invention is used for the element isolation element which isolate | separates each from an SFET apparatus is shown.
The manufacturing method of this example is shown in FIGS. First, as shown in FIG. 12, Pwell 101, N is formed on a P-type semiconductor substrate 100 using a conventional integrated circuit fabrication method.
Well 102 is provided.

The detailed manufacturing method is as follows. Boron ions and phosphorus ions are selectively implanted in the vicinity of the surface of the P-type semiconductor substrate 100 and annealed at 1000 to 1175 ° C. for 3 to 20 hours to diffuse and redistribute boron ions and phosphorus ions.
Pwell 101 and Nwell 102 of about E16 cm −3 are formed. Further, an infrastructure oxide film 113 is formed near the surface of the semiconductor substrate 100.

Thereafter, oxygen ions are implanted into the Pwell 101 and the Nwell 102, which will be the element isolation oxide film 111 in the future, by selectively implanting oxygen ions using a photoresist 109 to form an O ion implantation region 110. To do. The acceleration energy of oxygen ion implantation here is set so that an oxygen ion concentration peak occurs in a region near the surface of Pwell 101 and Nwell 102. Here, the O ion implantation region 11
0 is preferably set so that most (about 3 sigma) O ions are present in the Pwell 101 and the Nwell 102.

Thereafter, an annealing process at a high temperature is performed as shown in FIG. At this time, Pw
O ion implantation region 110 and the planar oxide film 1 in well 101 and Nwell 102
13 and the same oxide film by annealing, Pwell 101, Nwell 102
The O ion implantation region 110 therein becomes an oxide film, and an element isolation oxide film 111 embedded in the surface of the Pwell 101 and the Nwell 102 is formed.
On the other hand, no new oxide film is formed in the region covered with the photoresist 109 not implanted with oxygen ions.

After that, as shown in FIG. 14, the thickness 10 to 10 is formed by ion implantation for controlling the threshold voltage into a desired channel region and the thermal oxidation method after removing the implant oxide film 113.
Formation of 30 nm gate oxide film 112 and a thickness of 100 to 50 by low pressure CVD or the like
A 0 nm polysilicon film is formed and a high impurity concentration polysilicon film is formed by ion implantation or the like. Here, the formation of a tungsten silicide film having a thickness of about 100 to 200 nm by sputtering or the like on the high impurity concentration polysilicon film, and the oxidation of about 100 to 300 nm by the reduced pressure CVD method or the like on the tungsten silicide film. In some cases, a film is formed. Then, the gate electrode 106 is formed by patterning the polysilicon film. Here, an oxide film is formed on the upper portion of the gate electrode 106, the side wall portion, the semiconductor substrate surface portion, etc. by using a thermal oxidation method or a low pressure CVD method.
In some cases, the thickness is about 50 nm. Thereafter, ion implantation is performed in a self-alignment manner on the gate electrode 106, the element isolation oxide film 111, and the photoresist, respectively, so that the P + source region 105, the P + drain region 104, the P + channel stopper 107, and the N + source region 103. , N + drain region 114 and N + channel stopper 108 are selectively formed. The structure shown in FIG. 14 is obtained through the steps up to here.

Thus, an N-type MOSFET device and a P-type MOS formed on the same semiconductor substrate
Since a semiconductor device composed of an FET device and an element isolation element that separates each of them does not perform element isolation by a LOCOS method that has been generally used, the element isolation region can be easily reduced in size.

In the LOCOS method, a film such as Si3N4 having excellent oxidation resistance is selectively formed on a base oxide film, thermally oxidized at a high temperature of about 1000 ° C. to 1100 ° C., and then the oxide resistance film is removed to separate elements. This is a manufacturing method for forming an oxide region for an active region and an active region, but in this case, an end portion of the oxide film for element isolation is formed as a smoothly thinned region called a bird's beak due to oxygen wraparound, This has been an adverse effect on the miniaturization of the element isolation region.

However, according to the present invention, oxygen for supplying an oxide film for element isolation in the future can be supplied by ion implantation, so that the active region is not oxidized by the oxygen wraparound. For this reason, the active region and the element isolation region are steeply divided, and the element isolation region can be easily downsized.

Furthermore, the steep step originally causes a problem in the flattening of the wiring layer and interlayer film to be formed thereafter, but in the present invention, since the steep step is embedded in the semiconductor substrate, There is no step at the top that would be harmful to this process. For this reason, the process increase for planarization is not brought about in the subsequent process.

Although the steps after FIG. 14 are not shown, an interlayer film is formed on the surface portion, a contact region is formed, a metal wiring is formed, a protective film is then formed, and a window for electrical connection is opened. The semiconductor device is completed.

In the following description, since the oxygen ion implantation process and the annealing process are applied to the method for manufacturing a nonvolatile memory type semiconductor device, the nonvolatile memory element is promoted to be downsized and highly accurate.

  Embodiments of the present invention will be described below with reference to the drawings.

In this embodiment, analog and digital signal control M formed on the same semiconductor substrate.
A case where the present invention is used for an OSFET device and a nonvolatile memory MOSFET device will be described. The manufacturing method of the present embodiment is shown in FIGS. First, as shown in FIG. 15, Pwell 202 is formed on a semiconductor substrate 201 using a conventional integrated circuit manufacturing method.
, An isolation oxide film 205, a channel stopper 209, a tunnel oxide film 207, a select gate electrode 213, a floating gate electrode 208, a tunnel drain 204, a photoresist 210 for O ion implantation, and an oxygen ion implantation region 211 are provided. .

The detailed manufacturing method is as follows. Boron ions are implanted in the vicinity of the surface of the semiconductor substrate 201 and annealed at 1000 to 1175 ° C. for 3 to 20 hours to diffuse and redistribute boron ions, thereby forming a Pwell 202 having an impurity concentration of about 1E16 cm −3. Subsequently, B + ions are implanted into a region patterned with a nitride film or the like, and a channel stopper 209 and an element isolation oxide film 205 are formed by a LOCOS method.
Form.

Thereafter, a tunnel oxide film 207 having a thickness of 5 to 12 nm is formed by phosphorus or arsenic ion implantation for forming a tunnel drain into a desired region and thermal oxidation (dilution wet).
A polysilicon film having a thickness of 100 to 500 nm by a low pressure CVD method or the like, and a polysilicon film having conductivity by ion implantation or the like are formed. Here, a tungsten silicide film having a thickness of about 100 to 200 nm is formed on the polysilicon film by sputtering or the like, and a reduced pressure CV is applied to the tungsten silicide film.
In some cases, an oxide film having a thickness of about 100 to 300 nm is formed by the D method or the like. Then, the select gate electrode 213 and the floating gate electrode 208 are formed by patterning the polysilicon film. Here, thermal oxidation method or low pressure CVD
In some cases, an oxide film is formed to a thickness of about 10 to 50 nm on the select gate electrode 213 and the floating gate electrode 208, on the side walls, on the semiconductor substrate surface, and the like. After this, oxygen ion implantation will be performed in the area where tunnel oxide film will be unnecessary (
A region where no tunnel current flows), a region in the vicinity of the tunnel oxide film 207 in the floating gate electrode 208, and the select gate electrode 2
13. In the Pell 202 outside the both ends of the floating gate electrode 208,
O ion implantation regions 211 are formed by selectively implanting oxygen ions using the photoresist 210. The acceleration energy of oxygen ion implantation here is the tunnel oxide film 207 of the select gate electrode 213 and the floating gate electrode 208.
It is set so that an oxygen ion concentration peak occurs in a nearby region. Further, the thickness of the select gate electrode 213 and the floating gate electrode 208 is such that the depth from the surface of the P well 202 of the O ion implantation region 211 in the P well 202 is the same as the junction depth from the vicinity of the surface of the P well 202 of the N + region 203 to be formed in the future. It is desirable to set so as to be formed to a degree or less. The structure shown in FIG. 1 is obtained through the steps up to here.

Thereafter, as shown in FIG. 16, an annealing process at a high temperature is performed. At this time, the O ion implantation region 211 and the tunnel oxide film 207 in the select gate electrode 213 and the floating gate electrode 208 become the same oxide film by the annealing process, and the oxide film 2
12 is formed, and the O ion implantation region 211 in the Pwell 202 becomes an oxide film and P
An oxide film 212 embedded in the well 202 is formed.

On the other hand, no new oxide film is formed in the tunnel oxide film 207 region where oxygen ions are not implanted. N-type impurities are ion-implanted into the select gate electrode 213 and the floating gate electrode 208 in a self-aligned manner to form the N + region 203 shallower than the depth of the oxide film 212. Where N +
The region 203 is simultaneously formed in both the analog and digital signal control MOSFET device (not shown here) and the nonvolatile memory MOSFET device element. Thus, the structure of FIG. 16 is obtained.

Next, as described in FIG. 17, the N + region 203 is simultaneously formed in both the high voltage element and the low voltage element. All impurity regions have an impurity concentration of 1E21 cm @ -3.
To the extent. Thus, the structure of FIG. 17 is obtained.

Finally, although not shown, a phosphorus glass layer is formed as an interlayer insulator as in the case of manufacturing a conventional integrated circuit. For example, a low pressure CVD method may be used to form the phosphorus glass layer. As the material gas, monosilane SiH4, oxygen O2 and phosphine PH3 are used and reacted at 450 ° C.

Thereafter, a hole for forming an electrode is formed in the interlayer insulating film to form an aluminum electrode. Thus, analog and digital signal control MOSFET devices and nonvolatile memory MOSFET devices are completed on the same semiconductor substrate.

The memory element (FIG. 17) thus obtained has a region 214 through which a tunnel current flows and a floating gate electrode 20 as compared with the conventional nonvolatile memory cell (FIG. 18).
Since the oxide film 212 is buried below the select gate electrode 213 and the floating gate electrode 208 other than the region between the gate electrode 8 and the tunnel drain 204 (control gate tunnel oxide film 216), a voltage is applied to the tunnel drain 204. However, since the oxide film 212 is sufficiently thick and no tunnel current is generated, a small nonvolatile memory element can be realized.

Furthermore, if the oxygen ion implantation process is made more precise, a thick gate oxide film with little variation in film thickness can be formed even when the Dual Gate process is used as a memory element.
Since the tunnel oxide film that is not oxygen-implanted maintains high quality, high accuracy of the semiconductor device can be realized.

It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the semiconductor device of this invention. 1 is a schematic cross-sectional view of a semiconductor device of the present invention. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the conventional semiconductor device. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the conventional semiconductor device. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the conventional semiconductor device. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing in order of the manufacturing process of the manufacturing method of the semiconductor device of this invention. It is a schematic sectional drawing of the conventional semiconductor device.

Explanation of symbols

1 Psub
2 Pwell
3 Poly-Si gate 4 Gate oxide film 5 Photoresist 6 N-region 7 Oxide film 8 N + region 9 Depletion layer 10 N + drain 11 N + source 12 N-drain 13 N-source 14 P-type channel stopper 15 N-type channel Stopper 16 Nwell
17 P + drain 18 P + source 19 Thick oxide film 20 Oxide film 21 O ion implantation region 22 High voltage thick gate oxide film 23 Low voltage thin gate oxide film 24 High voltage element 25 Low voltage element 26 Field insulating film 27 Gate Oxide film (silicon oxide)
100 P-type semiconductor substrate 101 Pwell
102 Nwell
103 N + source region 104 P + drain region 105 P + source region 106 Gate electrode 107 P + channel stopper 108 N + channel stopper 109 Photoresist 1100 Ion implantation region 111 Element isolation oxide film 112 Gate oxide film 113 Implant oxide film 114 N + drain region 201 Semiconductor substrate 202 Pwell
203 N + region 204 Tunnel drain 205 Element isolation oxide film 206 Gate oxide film 207 Tunnel oxide film 208 Floating gate 209 Channel stopper 210 Photo resist 211 Oxygen ion implantation area 212 Oxide film 213 Select gate 214 Area through which tunnel current flows 215 Control gate Tunnel oxide film

Claims (1)

A semiconductor device having a high-voltage N-type MOSFET and a low-voltage N-type MOSFET on a semiconductor substrate,
The high-voltage N-type MOSFET is
A first gate electrode made of polysilicon;
The first gate electrode, which is disposed below the first gate electrode, is oxidized by ion-implanted oxygen ions, has a uniform film thickness, and is as large as the first gate electrode on the channel region. A first gate oxide film comprising: a first oxide film having a thickness; and a second oxide film formed by oxidizing the semiconductor substrate disposed under the first oxide film;
A first channel region in the vicinity of the surface of the semiconductor substrate immediately below the first gate electrode;
A first high-concentration source region and a first high-concentration source region disposed in the vicinity of the surface of the semiconductor substrate located below both sides of the first gate electrode and spaced apart from the first gate electrode by a certain distance, respectively; 1 high-concentration drain region;
A first low-concentration source disposed between the first channel region and the first high-concentration source region in the vicinity of the surface of the semiconductor substrate located immediately below both sides of the first gate electrode A first low-concentration drain region disposed between the region, the first channel region and the first high-concentration drain region;
Embedded oxide films respectively disposed only under the first low-concentration source region and the first low-concentration drain region inside the semiconductor substrate;
Have
The low-voltage N-type MOSFET is
A second gate electrode made of polysilicon;
A second gate oxide film made of the second oxide film, which is disposed under the second gate electrode and oxidizes the semiconductor substrate;
A second channel region in the vicinity of the surface of the semiconductor substrate immediately below the second gate electrode;
A second high-concentration source region and a second high-concentration source region disposed in the vicinity of the surface of the semiconductor substrate located below both sides of the second gate electrode and spaced apart from the second gate electrode by a certain distance, respectively; Two high concentration drain regions;
A second low-concentration source disposed between the second channel region and the second high-concentration source region in the vicinity of the surface of the semiconductor substrate located immediately below both sides of the second gate electrode A region, a second lightly doped drain region disposed between the second channel region and the second heavily doped drain region,
A semiconductor device.

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