JP4997035B2 - Image processing apparatus and reference clock supply method - Google Patents

Description

  The present invention relates to an image processing apparatus that performs image processing such as copying, printer, facsimile, and scanning, and more particularly to an image processing apparatus that includes a high-speed serial bus and a reference clock supply method.

  As one of high-speed serial buses, there is PCI Express (registered trademark). Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line. This PCI Express is standardized as a standard expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, packets It has features such as high-performance scalability due to different split transactions and link configurations.

  As an example of the prior art related to PCI Express, for example, when high-speed serial data communication, particularly high-speed serial data communication conforming to the PCI Express standard is applied to an imaging device, an interface function that is advantageous and efficient in terms of cost and power consumption "Serial data transfer device, image output device, image input device and image forming device" (see, for example, Patent Document 1), or when processing a plurality of independent data transfers in parallel, There is a “data transfer system, image forming system, and data transfer program” (see, for example, Patent Document 2) that improves data transfer efficiency by avoiding competition.

JP-A-2005-321921 JP 2005-151448 A

  However, in a device having a conventional PCI Express standard interface as described above, when a reference clock with a spread frequency is input, the PCI Express I / O power supply of the device to which the reference clock is input remains below the operating voltage. If the clock is input, the device may be damaged.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an image processing apparatus and a reference clock supply method capable of operating a device without failure.

An image processing apparatus according to the present invention is an image processing apparatus, and is connected to an engine that performs an image processing operation, a controller that controls the engine, the controller and the engine, and the controller to the engine. An interface employing an embedded clock technology for supplying a reference clock, the engine further comprising a power supply for the interface, and the controller has a voltage of the power supply within a predetermined operating voltage range. after becoming, it characterized by comprising a clock oscillator for starting oscillation of the reference clock.

  According to the present invention, it is possible to operate this device without failure by starting clock oscillation after confirming that the interface power supply voltage of the device to which the reference clock is input is within the operating voltage. It becomes.

The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings.
(Embodiment 1)

  In this embodiment, it is possible to operate the device without failure by starting clock oscillation after confirming that the PCI Express I / O power supply voltage of the device to which the reference clock is input is within the operating voltage. With the goal.

  The configuration of the image processing apparatus according to the present embodiment is shown in FIG. As shown in FIG. 1, the image processing apparatus according to the present embodiment includes an engine 2 that performs image processing operations such as a print operation and a scanner operation, a power source 11 of a controller 1 that controls the engine 2, and a power source of the engine 2. 21 and the controller 1 are mainly provided with a PSU (Power Supply Unit) 4 and a main power source SW3. The controller 1 and the engine 2 are connected by a PCI Express standard bus 5 (hereinafter referred to as “PCI Express 5”).

  The engine 2 mainly includes a power supply 21 that is a PCI Express I / O power supply, a RESET IC 24, a CPU 23, and an ASIC 22. The controller 1 mainly includes a power supply 11, an ASIC 12, a CPU 13, and an SSCG (Spread Spectrum Clock Generator) 14.

  The SSCG 14 is a clock oscillator that oscillates a reference clock (REFCLK) and supplies the reference clock to the engine 2. The SSCG 14 includes a register 14a. The register 14a will be described later. The ASIC 12 is provided with an LTSSM register 14a. The LTSSM register 14a will be described later. The CPU 13 has a timer 13a.

  When the system (image processing apparatus) is started, first, the main power supply 3 is turned on, and power is supplied from the PSU 4 to the controller 1 and the engine 2, respectively. The controller 1 and the engine 2 generate necessary power supplies in each unit.

  Specifically, when the main power supply SW3 is turned on while the AC power supply is off, the 5VE DC power supplied to the controller 1 is turned on, the power supply 11 of the controller is turned on, PONENG is asserted from the ASIC 12, and the PSU4 Is sent out.

When the PSU 4 receives PONENG from the ASIC 12, the 5V DC power supplied to the engine 2 and a part of the controller 1 is turned on. Then, a signal (POKEN: Power OK Engine) indicating that the PCI Express I / O power source (power source 21) of the engine 2 is within the operating voltage is asserted from the RESET IC 24, which is detected by the ASIC 12 of the controller 1. , An instruction is given to supply a reference clock (REFCLK) to an SSCG (Spread Spectrum Clock Generator) 14 via the I ² C bus. As a result, the SSCG 14 starts oscillating the reference clock (REFCLK) and starts supplying the reference clock to the engine 2.

  Further, in the configuration shown in FIG. 1, the supply of the reference clock (REFCLK) is started by an instruction from the ASIC 12, but the PCI Express I / O power supply (power supply 21) of the engine 2 is operated without using the ASIC. The oscillation of the clock may be controlled by inputting a signal (POKENG) indicating that the signal is inside to the output enable terminal of the SSCG 14. A configuration for realizing such an operation is shown in FIG. In FIG. 2, when the signal (POKENG) indicating that the PCI Express I / O power source (power source 21) of the engine 2 is within the operating voltage is asserted from the RESET IC 24, the output of the SSCG 14 of the controller 1 becomes valid. Supply of the reference clock (REFCLK) is started.

As described above, according to the present embodiment, in the image processing apparatus that has the PCI Express interface between the controller and the engine and supplies the reference clock obtained by spreading the PCI Express frequency from the controller, the system It is characterized in that the reference clock starts to oscillate after the PCI Express I / O power supply voltage of the engine falls within the operating voltage at the time of startup. Therefore, by confirming that the PCI Express I / O power supply voltage of the device to which the reference clock is input is within the operating voltage, the device can be operated without failure by starting clock oscillation.
(Embodiment 2)

  In the present embodiment, when the PCI Express I / O power supply of the device to which the reference clock is input becomes lower than the operating voltage for some reason during the system operation, the clock oscillation is stopped to Is intended to be used without failure.

Since the configuration of this embodiment is the same as the configuration shown in FIGS. 1 and 2, the description thereof is omitted here, and only the operation will be described below. When the PCI Express I / O power supply 21 of the engine 2 becomes lower than the operating voltage during the system operation, POKENG is negated. In the case of the configuration of FIG. 1, the ASIC 12 detects this state and stops the oscillation of the SSCG 14. via the I ² C bus commands the one hand, in the configuration shown in FIG. 2, 14 oscillation SSCG stops by the enable terminal of SSCG14 is changed into a disabled.

  As described above, according to the present embodiment, in the image processing apparatus according to the first embodiment, when the I / O power supply voltage for the PCI Express of the engine becomes out of the operating voltage during the system operation, the reference from the controller. The supply of the clock is stopped. Therefore, when the PCI Express I / O power supply of the device to which the reference clock is input for some reason becomes lower than the operating voltage during system operation, this device can be used without failure by stopping clock oscillation. be able to.

(Embodiment 3)
Next, a case where communication by PCI Express is not established when the system is started will be described. When the ASIC 12 of the controller 1 gives an instruction to start oscillation of the reference clock, the timer 13a of the CPU 13 of the controller 1 starts counting. Then, if the ASIC 12 of the controller 1 can communicate with the ASIC 22 of the engine 2 before the timer 13a of the CPU 13 of the controller 1 counts a certain number of times, the system startup process is continued. Before the ASIC 21 of the controller 1 can communicate with the ASIC 22 of the engine 2, if the count of the CPU 13 exceeds a certain number of times, communication is established even if a certain time elapses after the reference clock (REFCLK) is supplied. Judge as not to take action. This action is different between the third embodiment described below and the fourth and subsequent embodiments.

  In the third embodiment, when there is a possibility that the PCI Express interface is in an abnormal state, an object is to immediately stop the oscillation of the reference clock and prevent the device from being damaged.

  The second embodiment is realized by the configuration shown in FIG. 1 and the flow shown in FIG. The operation of the present embodiment will be described with reference to FIGS.

After the system is started and the main power supply 3 is turned on, and the controller 1 and the engine 2 generate the necessary power supply in each unit, the PCI Express I / O power supply (power supply 21) of the engine 2 is within the operating voltage. The RESET IC 24 asserts a signal (POKENG) indicating that it has become (step S1), the ASIC 12 of the controller 1 detects it, and issues an instruction to supply the reference clock (REFCLK) to the SSCG 14 via the I ² C bus. give. As a result, the SSCG 14 starts to supply the reference clock (REFCLK) (step S2).

  When the ASIC 12 of the controller 1 instructs the start of reference clock oscillation, the timer 13a of the CPU 13 of the controller 1 starts counting (step S3).

  If the ASIC 12 of the controller 1 can communicate with the ASIC 22 of the engine 2 (step S5 / YES) before the timer 13a of the CPU 13 of the controller 1 counts a certain number of times (step S4 / NO), the system startup process continues. I do.

  Here, whether or not the ASIC 12 of the controller 1 can communicate with the ASIC 22 of the engine 2 is determined as follows. The ASIC 12 is provided with an LTSSM (Link Training and Status State Machine) register 12a. The LTSSM register 12a is 32 bits long, and the Status Code is stored in the area from 0 to 8 bits from the beginning. This Status Code stores a different value depending on various states, but when the ASIC 12 of the controller 1 has completed link training with the ASIC 22 of the PCI Express 5 engine 2 and can communicate, L0 (value of 0x16) Is stored.

  For this reason, the CPU 13 refers to the LTSSM register 12a of the ASIC 12, and determines whether the ASIC 12 can communicate with the ASIC 22 of the engine 2 based on whether the Status Code is L0. The determination as to whether the ASIC 12 can communicate with the ASIC 22 of the engine 2 is the same in the following embodiments.

  The ASIC 22 of the engine 2 is also provided with an LTSSM register. First, after confirming that the Status Code of the LTSSM register 12a of the ASIC 12 is L0, the Status Code of the LTSSM register of the ASIC 22 of the engine 2 is L0. It may be configured to check whether or not. As a result, it is possible to confirm that transmission / reception is possible between the ASIC 12 of the controller 1 and the ASIC 22 of the engine 2, and it is possible to confirm that the Status Code of the LTSSM register 12a of the ASIC 22 is also L0.

Before the ASIC 21 of the controller 1 can communicate with the ASIC 22 of the engine 2 (step S5 / NO), if the count of the CPU 13 exceeds a certain number (step S4 / YES), the reference clock (REFCLK) is supplied. Then, it is determined that communication is not established even after a certain time has elapsed, and an action is taken to stop the oscillation of the reference clock via the I ² C bus (step S6), and the system is stopped.

As described above, according to the present embodiment, in the image processing apparatus according to the first or second embodiment, when communication is not established even after a predetermined time has elapsed since the reference clock was supplied at the time of system startup, The supply of the clock is stopped. Therefore, when there is a possibility that the PCI Express I / F is in an abnormal state, it is possible to immediately stop the oscillation of the reference clock and prevent the device from malfunctioning.
(Embodiment 4)

  In this embodiment, when communication is not established even after a certain period of time has elapsed since the reference clock with the spread frequency is supplied at the system startup, the communication is established by supplying the reference clock without spreading the frequency. The purpose is to let you.

  The present embodiment is realized by the configuration shown in FIG. 1 and the flow shown in FIG. The operation of the present embodiment will be described with reference to FIGS.

After the system is started and the main power supply 3 is turned on, and the controller 1 and the engine 2 generate the necessary power supply in each unit, the PCI Express I / O power supply (power supply 21) of the engine 2 is within the operating voltage. The RESET IC 24 asserts a signal (POKENG) indicating that it has become (step S11), the ASIC 12 of the controller 1 detects it, and issues an instruction to supply the reference clock (REFCLK) to the SSCG 14 via the I ² C bus. give. As a result, the SSCG 14 starts to supply the reference clock (REFCLK) (step S12).

  When the ASIC 12 of the controller 1 instructs to start oscillation of the reference clock, the timer 13a of the CPU 13 of the controller 1 starts counting (step S13).

  If the ASIC 12 of the controller 1 becomes able to communicate with the ASIC 22 of the engine 2 (step S15 / YES) before the timer 13a of the CPU 13 of the controller 1 counts a certain number of times (step S14 / NO), the system startup process continues. I do.

Before the ASIC 21 of the controller 1 can communicate with the ASIC 22 of the engine 2 (step S15 / NO), the count of the CPU 13 exceeds a certain number (step S14 / YES), and the reference clock (REFCLK) is spread in frequency. If there is no error (step S16 / NO), an action is taken to stop the oscillation of the reference clock via the I ² C bus (step S17), and the system is stopped.

  Here, the presence or absence of frequency spreading of the reference clock (REFCLK) is determined as follows. As described above, the SSCG 14 is provided with the register 14a. This register 14a is used for Bit4 and Bit5 to control the frequency spread of the reference clock (REFCLK), and -4%, -0.25%, -0.1 as the frequency spread width to Bit4 and Bit5. % Ratio or a value indicating OFF can be set. That is, by setting OFF to 2 bits of Bit 4 and Bit 5 (Bit N: indicating the Nth bit from the head) of the register 14a, frequency spreading is not performed, and when the ratio is set to Bit 4 and Bit 5, the ratio is set. It is controlled to perform frequency spreading with a frequency spreading width of. Accordingly, in step S16, the SSCG 14 refers to the register 14a and determines whether or not frequency spreading is performed based on whether or not Bit4 and Bit5 are set to OFF.

When there is frequency spreading of the reference clock (REFCLK) (step S16 / YES), the count of the timer 13a of the CPU 13 is cleared (step S18), and the frequency spreading of the reference clock is stopped via the I ² C bus to reference clock. (REFCLK) is oscillated (step S19), and communication establishment is attempted again.

  Here, in step S19, the SSCG 14 sets a value indicating that OFF is set in Bit4 and Bit5 of the register 14a, thereby stopping frequency spreading and oscillating the reference clock (REFCLK).

As described above, according to the present embodiment, in the image processing apparatus according to any one of the first to third embodiments, communication is not established even after a predetermined time has elapsed since the reference clock was supplied at the time of system startup. In addition, the frequency of the reference clock is supplied without spreading. Therefore, at the time of starting the system, if communication is not established even after a certain time has elapsed after supplying the reference clock with the spread frequency, communication can be established by supplying the reference clock without spreading the frequency. .
(Embodiment 5)

  In this embodiment, when the communication is not established even after a lapse of a certain time after supplying the reference clock with the frequency spread at the time of starting the system, the communication is performed by reducing the frequency spreading width of the reference clock and supplying it. The purpose is to establish.

  The present embodiment is realized by the configuration shown in FIG. 1 and the flow shown in FIG. The operation of the present embodiment will be described with reference to FIGS.

After the system is started and the main power supply 3 is turned on, and the controller 1 and the engine 2 generate the necessary power supply in each unit, the PCI Express I / O power supply (power supply 21) of the engine 2 is within the operating voltage. The RESET IC 24 asserts a signal (POKENG) indicating that it has become (step S21), the ASIC 12 of the controller 1 detects it, and issues an instruction to supply the reference clock (REFCLK) to the SSCG 14 via the I ² C bus. give. As a result, the SSCG 14 starts to supply the reference clock (REFCLK) (step S22).

  When the ASIC 12 of the controller 1 instructs to start oscillation of the reference clock, the timer 13a of the CPU 13 of the controller 1 starts counting (step S23).

  If the ASIC 12 of the controller 1 can communicate with the ASIC 22 of the engine 2 (step S25 / YES) before the timer 13a of the CPU 13 of the controller 1 counts a certain number of times (step S24 / NO), the system startup process continues. I do.

Before the ASIC 21 of the controller 1 can communicate with the ASIC 22 of the engine 2 (step S25 / NO), the count of the CPU 13 exceeds a predetermined number (step S24 / YES), and the frequency of the reference clock (REFCLK) is spread. If the width is 0 (step S26 / YES), an action is taken to stop the oscillation of the reference clock via the I ² C bus (step S27), and the system is stopped.

  Here, whether or not the frequency spread width of the reference clock (REFCLK) is 0 is determined by the SSCG 14 referring to the register 14a based on whether or not Bit4 and Bit5 are set to OFF.

When the frequency spread width of the reference clock (REFCLK) is not 0 (step S26 / NO), the count of the timer 13a of the CPU 13 is cleared (step S28), and the frequency spread width of the reference clock is made constant via the I ² C bus. The reference clock (REFCLK) is oscillated by decreasing the amount (step S29), and the ASIC 12 of the controller 1 again tries to communicate with the ASIC 22 of the engine 2 by PCI Express.

  Here, in step S29, the SSCG 14 sets the frequency spread width of the reference clock by oscillating the reference clock after setting a certain amount smaller than the currently set frequency spread width in the Bit 4 and Bit 5 of the register 14a. Decrease by a certain amount. The processing for decreasing the frequency spread width of the reference clock by a certain amount is the same in the following embodiments.

Thereafter, when the timer 13a of the CPU 13 of the controller 1 counts a certain number of times or more, the frequency spread width of the reference clock is decreased by a certain amount again via the I ² C bus. This is repeated until communication between the ASIC 12 of the controller 1 and the ASIC 22 of the engine 2 is established.

As described above, according to the present embodiment, in the image processing apparatus according to any one of the first to fourth embodiments, communication is not established even after a predetermined time has elapsed since the reference clock was supplied at the time of system startup. In addition, the frequency spreading width of the reference clock is reduced to a value that enables communication. Therefore, at the time of system startup, if communication is not established even after a certain period of time has elapsed since the reference clock with the spread frequency is supplied, communication is established by reducing the frequency spread width of the reference clock and supplying it. Can do.
(Embodiment 6)

  Next, a method of increasing the frequency spread width for PCI Express as much as possible to reduce EMI will be described. In a conventional device having a PCI Express standard interface, if the frequency spread width of the reference clock is too large, communication may not be established. Conversely, if the frequency spread width of the reference clock is too small, the EMI of the device is reduced. There was a problem of getting bigger. An object of the present embodiment is to reduce the EMI of a device by increasing the frequency spread width of a reference clock to a maximum value at which communication is possible at the time of system startup.

  The present embodiment is realized by the configuration shown in FIG. 1 and the flow shown in FIG. The operation of the present embodiment will be described with reference to FIGS.

After the system is started and the main power supply 3 is turned on, and the controller 1 and the engine 2 generate the necessary power supply in each unit, the PCI Express I / O power supply (power supply 21) of the engine 2 is within the operating voltage. The RESET IC 24 asserts a signal (POKENG) indicating that it has become (step S31), the ASIC 12 of the controller 1 detects it, and issues an instruction to supply the reference clock (REFCLK) to the SSCG 14 via the I ² C bus. give. As a result, the SSCG 14 starts to supply the reference clock (REFCLK) (step S32).

  When the ASIC 12 of the controller 1 commands the start of reference clock oscillation, the timer 13a of the CPU 13 of the controller 1 starts counting (step S33).

  If the ASIC 12 of the controller 1 becomes able to communicate with the ASIC 22 of the engine 2 (step S35 / YES) before the timer 13a of the CPU 13 of the controller 1 counts a certain number of times (step S34 / NO), step S40 to be described later Proceed to

Before the ASIC 21 of the controller 1 can communicate with the ASIC 22 of the engine 2 (step S35 / NO), the count of the CPU 13 exceeds a certain number (step S34 / YES), and the reference clock (REFCLK) is spread in frequency. If the width is 0 (step S36 / YES), an action is taken to stop the oscillation of the reference clock via the I ² C bus (step S37), and the system is stopped.

When the frequency spread width of the reference clock (REFCLK) is not 0 (step S36 / NO), the count of the timer 13a of the CPU 13 is cleared (step S38), and the frequency spread width of the reference clock is made constant via the I ² C bus. The reference clock (REFCLK) is oscillated by decreasing the amount (step S39), and the ASIC 12 of the controller 1 tries again to communicate with the ASIC 22 of the engine 2 by PCI Express.

When communication between the ASIC 12 of the controller 1 and the ASIC 22 of the engine 2 is established in step S35 (step S35 / YES), the count of the timer 13a of the CPU 13 is cleared (step S40), and the I ² C bus is used. The reference clock (REFCLK) is oscillated by increasing the frequency spread width of the reference clock by a certain amount (step S41), and communication establishment is attempted. This flow is continued until communication is not established even after a certain period of time has elapsed since the reference clock was supplied. This will be described below.

  Here, in step 41, the SSCG 14 sets a value larger than the currently set frequency spread width in the Bit 4 and Bit 5 of the register 14a and then oscillates the reference clock, thereby reducing the frequency spread width of the reference clock. Increase by a certain amount.

  Counting is started by the timer 13a of the CPU 13 of the controller 1 (step S42).

  If the ASIC 12 of the controller 1 can communicate with the ASIC 22 of the engine 2 (step S44 / YES) before the timer 13a of the CPU 13 of the controller 1 counts a certain number of times (step S43 / NO), the process returns to step S40. .

  Before the ASIC 21 of the controller 1 can communicate with the ASIC 22 of the engine 2 (step S44 / NO), if the count of the CPU 13 exceeds a certain number (step S43 / YES), the frequency spread width is set to the last. Is set to a value obtained when communication is established or a value obtained by adding a predetermined margin to the value obtained when communication is established last, and the reference clock is oscillated (step S45) to start the system.

  Here, every time communication is established, the value of the frequency spread width set in Bit 4 and Bit 5 of the register 14a of the SSCG 14 at that time is stored and updated in a memory or the like. In step S45, the SSCG 14 sets the value of the frequency width at the time when communication is finally established stored in this memory or the value obtained by adding a predetermined margin to the value to Bit4 and Bit5 of the register 14a. Oscillate the reference clock.

  As described above, according to the present embodiment, in the image processing apparatus according to any one of the first to fifth embodiments, after the reference clock is supplied at the time of system startup and communication is established, the frequency spread width of the reference clock is increased. It is characterized in that the communication is increased to the maximum possible value. Therefore, the EMI of the device can be reduced by increasing the frequency spread width of the reference clock to the maximum value at which communication is possible at the time of system startup.

(Embodiment 7)
In the first to sixth embodiments, the oscillation of the reference clock is started after the power supply voltage of the engine 2 falls within a predetermined operating voltage range when the image processing apparatus is started. In the seventh embodiment, The reference clock oscillation is started when the engine and the controller 1 are recovered from the energy saving state in which the power supply of a part of the engine and the controller 1 is stopped.

  Here, the energy saving state is a state in which the 5VE DC power supplied to the controller 1 is ON and the 5V DC power supplied to a part of the engine 2 and the controller 1 is OFF.

  The configuration of the image processing apparatus according to this embodiment is the same as that of the first to sixth embodiments shown in FIG.

First, the process of shifting to an energy saving state will be described. FIG. 7 is a flowchart showing a procedure of processing at the time of transition to the energy saving state. When the image processing apparatus is in the standby state (step S51) and the energy saving state shifts, first, PONENG (Power ON Engine) output from the ASIC 12 is negated (step S52). As a result, the PSU 4 turns off the 5V DC power supplied to the engine 2 and a part of the controller 1 (step S53), and the power source 21 of the engine 2 is turned off (step S54). Then, POKENG from the RESET IC 24 is negated (step S55), and the SSCG 14 stops oscillating the reference clock by a command from the ASIC 12 via the I ² C bus (step S56). Thereby, it transfers to an energy saving state (step S57).

  Next, a description will be given of processing in which the image processing apparatus that has transitioned to the energy saving state returns from the energy saving state. FIG. 8 is a flowchart illustrating a procedure of processing for returning from the energy saving state.

  First, the image processing apparatus is in an energy saving state (step S61). When returning from this state, PONENG from the ASIC 12 is asserted (step S62). As a result, the PSU 4 turns on the 5V DC power supplied to the engine 2 and a part of the controller 1 (step S63). As a result, the power source 21 of the engine 2 is turned on, and POKENG from the RESET IC 24 is asserted. Subsequent reference clock oscillation processing is performed in the same manner as the processing described with reference to FIGS. That is, when returning from the energy saving state, it is determined whether or not the PCI Express I / O power supply voltage of the engine 2 is within the operating voltage. After the operating voltage is within the operating voltage, oscillation of the reference clock is started.

  As described above, in the image processing apparatus according to the seventh embodiment, when the I / O power supply voltage for PCI Express of the engine 2 falls within the operating voltage when returning from the energy saving state and when returning from the energy saving state, the reference clock Since the oscillation of the device starts, it is confirmed that the PCI Express I / O power supply voltage of the device to which the reference clock is input is within the operating voltage and then the clock oscillation is started, so that this device can be operated without failure. be able to.

  It should be noted that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  The present invention can be applied to a device having an interface of the PCI Express standard.

It is a block diagram which shows an example of a structure of the image processing apparatus which concerns on Embodiment 1-6. It is a block diagram which shows an example of a structure of the image processing apparatus which concerns on Embodiment 1-6. 10 is a flowchart illustrating an operation of the image processing apparatus according to the third embodiment. 14 is a flowchart illustrating an operation of the image processing apparatus according to the fourth embodiment. 10 is a flowchart illustrating an operation of the image processing apparatus according to the fifth embodiment. 14 is a flowchart illustrating an operation of the image processing apparatus according to the sixth embodiment. 18 is a flowchart illustrating a processing procedure when the image processing apparatus according to the seventh embodiment shifts to an energy saving state. 18 is a flowchart illustrating a processing procedure when the image processing apparatus according to the seventh embodiment returns from an energy saving state.

Explanation of symbols

1 Controller 2 Engine 3 Main power supply 4 PSU
5 PCI Express
11 Controller 1 PCI Express I / O Power Supply 12 Controller 1 ASIC
13 CPU of controller 1
14 SSCG
21 Engine 2 PCI Express I / O Power Supply 22 Engine 2 ASIC
23 CPU of controller 1
24 RESET IC

Claims (10)

An image processing apparatus,
An engine that performs image processing operations;
A controller for controlling the engine;
An interface that is connected between the controller and the engine and employs an embedded clock technology for supplying a reference clock from the controller to the engine; and
The engine further includes a power source for the interface,
The image processing apparatus according to claim 1, wherein the controller includes a clock oscillator that starts oscillation of the reference clock after the voltage of the power source falls within a predetermined operating voltage range.   2. The clock oscillator according to claim 1, wherein the clock oscillator stops oscillation of the reference clock when the voltage of the power source falls outside the range of the operating voltage during the operation of the image processing apparatus. Image processing device. The controller further includes a determination unit that determines whether communication between the controller and the engine via the interface is established within a predetermined time after the reference clock is supplied,
The clock oscillator, if the determination unit determines that the communication through the interface with the controller and the engine after a certain period of time has not been established, characterized by stopping the oscillation of the reference clock The image processing apparatus according to claim 1. The clock oscillator, if the determination unit determines that the communication through the interface with the controller and the engine after a certain period of time has not been established, to oscillate the reference clock without diffusing the frequency The image processing apparatus according to claim 3 . The clock oscillator, if the determination unit determines that the communication through the interface with the controller and the engine after a certain period of time has not been established, was reduced to a value that enables communications frequency spreading width The image processing apparatus according to claim 3 , wherein the reference clock is oscillated. Said clock oscillator, after the determination unit determines that communication through the interface with the engine and the controller is established, the oscillation of communicating the frequency diffusion width is increased to the maximum possible value the reference clock The image processing apparatus according to claim 5 , wherein:   The image processing apparatus according to claim 1, wherein the clock oscillator starts oscillation of the reference clock when the image processing apparatus is activated.   The clock oscillator stops the power supply to the engine and starts oscillating the reference clock when returning from an energy saving state in which a part of the power is supplied to the controller. The image processing apparatus according to claim 1. The interface is an image processing apparatus according to any one of claims 1-8, characterized in that an in-tough Esu of PCI Express standard. A reference clock supply method executed in a device,
The device includes an engine, a controller that controls the engine, an interface that is connected between the controller and the engine, and that employs embedded clock technology for supplying a reference clock from the controller to the engine; The engine further includes a power supply for the interface,
A method of supplying a reference clock, comprising: starting oscillation of the reference clock after the voltage of the power source falls within an operating voltage range.

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