JP4998295B2 - Solid-state imaging device and mixed noise suppression method for solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device using a threshold modulation type imaging device (hereinafter referred to as VMIS) as a MOS-type solid-state imaging device constituting a pixel, and a mixed noise suppression method for the solid-state imaging device.

  Conventionally, in a solid-state imaging device, a predetermined number of pixels are used according to the size of the screen, and VMIS is known as one of the MOS type solid-state imaging devices that constitute these pixels. This VMIS uses the substrate modulation effect of a MOS transistor to read out by converting the charge corresponding to the amount of light into a voltage. More specifically, the boundary gate voltage threshold when the MOS transistor is switched from off to on with the charge generated by light reception is changed, and the change in the threshold is output as a pixel signal. At this time, a bias voltage is applied to the gate side and the drain side of the MOS transistor, and the pixel signal is read out as a follower circuit from the source side.

  The pixel in the solid-state imaging device is composed of an insulated gate MOS transistor for detecting an image signal and a photodiode. In the case of a VMIS pixel, the cathode side of the photodiode is connected to the drain side on the substrate, and the anode side is the back gate side. Connected. The MOS transistor portion here has a high-concentration buried layer that accumulates photogenerated charges generated by light irradiation with a photodiode provided in the well region under the gate electrode in the vicinity of the source region. Is stored in the high concentration buried layer to modulate the threshold voltage and detect the pixel signal. As all the pixels, a predetermined number of pixels are arranged in a matrix in the row direction and the column direction to form a light receiving unit.

  In the light receiving portion, the gate line in the row direction is a common connection of the gate electrode sides of the MOS transistors in the horizontal pixels, and a scanning signal for turning on the gate electrode of the MOS transistor is supplied during the pixel signal detection period. The pixel signal can be read out by controlling the voltage applied to the gate line sequentially by the vertical scanning circuit that outputs each line. The drain line is commonly connected to the drain electrode side of the MOS transistor and the cathode side of the photodiode in the horizontal pixel, but is electrically connected to all the pixels and applied to the drain line by the drive circuit. By controlling the driving voltage, it is possible to store an optical signal and read out a pixel signal.

The source line in the column direction commonly connects the MOS transistor source electrode sides of the vertical pixels, and stores and holds the pixel signal from the pixel to which the scanning signal is output or the noise component charge immediately after the pixel is reset. Is connected to one end of a line memory group consisting of a plurality of capacitive elements, and resets the pixel by applying a reset voltage to the pixel by a reset circuit when resetting the pixel, and controls the vertical scanning circuit to read the pixel signal to the line memory group when reading the pixel signal Is transmitted. Incidentally, the other end side of each capacitive element here is connected to ground.
In addition, the well-known technique relevant to such a solid-state imaging device (solid-state image sensor) and the pixel structure used for it is disclosed by patent document 1 or patent document 2, for example.
Japanese Patent Laid-Open No. 11-195778 JP 2001-230973 A

In the case of a solid-state imaging device using VMIS in the above-described conventional pixel configuration, there is a problem in that the horizontal streak image generated by affecting the pixels in the horizontal direction due to noise mixing in the gate line of the light receiving unit cannot be sufficiently suppressed.
More specifically, if channel length modulation is ignored when reading a pixel signal, the drain current Id, the gate voltage Vg, and the source voltage Vs in the MOS transistor in the saturation region are expressed by the relationship of the following equation (1).
Id = 0.5 μCox (W / L) · {Vg−Vs−Vth (Φ)} ^0.5 (1)

Here, μ is mobility, Cox is gate capacitance, W is gate width, L is gate length, and Vth (Φ) is a threshold voltage expressed as a function of light quantity Φ. When the output voltage Vs of the pixel signal is obtained from the equation (1),
Vs = Vg−Vth (Φ) − (2Id / μCox) ^0.5 · (L / W) ^0.5 (2)
It becomes. The gate voltage Vg at the time of reading is a DC high level control voltage Vpgh input to the vertical scanning circuit. The gate voltage Vg when noise is mixed in the gate line vpgn is added, and the noise voltage Vnoise is added to the control voltage Vpgh. In this case, the gate voltage Vg is
Vg = (Vpgh + Vnoise) −Vth (Φ) − (2Id / μCox) ^0.5 · (L / W) ^0.5 (3)
It becomes. Since the high level control voltage Vpgh is commonly applied to the pixels in the horizontal direction of the light receiving unit, the noise voltage Vnoise is superimposed on all the pixel outputs in one row. As a result, it appears as horizontal stripes on the image. Since human eyes are sensitive to streak noise, even if the noise voltage Vnoise is about 1 mV, it is recognized as a horizontal streak image. As a countermeasure, even if an attempt is made to set the high-level control voltage Vpgh to 1 mV or less, since inevitable noise from the outside such as power supply noise is actually mixed, it is technically difficult.
Therefore, the technical problem of the present invention is to provide a solid-state imaging device and a mixed-noise suppression method for a solid-state imaging device that can suppress a horizontal streak image generated by affecting the pixels in the horizontal direction due to noise mixing in the gate line of the light receiving unit. It is to provide.

In order to solve the above technical problem, the first invention is:
A pixel (for example, a pixel shown in FIG. 1) having a configuration in which a MOS transistor as a VMIS and a photodiode are connected, the cathode side of the photodiode is connected to the drain side, and the anode side is connected to the back gate side. A light receiving unit (for example, the light receiving unit 1 in FIG. 1) arranged in a predetermined number of rows in the column direction,
A scanning line for turning on the gate electrode of the MOS transistor during the pixel signal detection period is a gate line formed by commonly connecting the gate electrode side of the MOS transistor in the pixel in the horizontal direction of the light receiving unit (for example, FIG. 1 for each row line (for example, vertical scanning circuit 2 in FIG. 1), and vpg1, vpg2 in FIG.
One end side is connected to a source line (for example, vps1, vps2 in FIG. 1) connected in common to the source electrode side of the MOS transistor in the pixel in the vertical direction of the light receiving unit during the pixel signal detection period, and the other A plurality of capacitive elements (for example, the pixel signal storage shown in FIG. 1) that are connected to ground and that store and hold the pixel signal from the pixel to which the scanning signal is output or the noise component charge immediately after resetting the pixel. Line memory group (for example, line memory group 5 in FIG. 1) composed of capacitors c1-1 and c1-2 for use, and noise component storage capacitors c2-1 and c2-2 immediately after resetting the pixels;
Have
The other end side of the plurality of capacitive elements in the line memory group is connected to the same voltage location as the gate voltage of the MOS transistor during the pixel signal detection period.

  With such a configuration, even if a noise voltage Vnoise due to mixed noise is applied to the gate lines of the light receiving unit (for example, the gate lines vpg1 and vpg2 in FIG. 1), the pixel component signals and pixels stored and held in the line memory group are The influence of the noise voltage Vnoise can be eliminated for both the noise component immediately after resetting. As a result, the horizontal streak image does not appear in the image signal of the output voltage Vout obtained by the difference between the pixel component signal and the noise component immediately after resetting the pixel, and a high image quality that is difficult to obtain with conventional devices can be obtained.

Also, the second invention is
The other end side of the plurality of capacitive elements in the line memory group has a high-level control voltage line input to the vertical scanning circuit (for example, a high-level control voltage input to the vertical scanning circuit 2 in FIG. 1). It is characterized by being connected to the Vpgh line).
With such a configuration, even when a noise voltage Vnoise due to mixed noise is applied to the line of the high-level control voltage Vpgh, both the pixel component signal accumulated and held in the line memory group and the noise component immediately after resetting the pixel The influence of the noise voltage Vnoise can be eliminated, and the horizontal streak image does not appear in the image signal as in the case of the first invention, and a high image quality that is difficult to obtain with conventional devices can be obtained. Since it can be implemented only by changing the wiring, it can be realized easily and inexpensively.

Furthermore, the third invention is
A pixel (for example, a pixel shown in FIG. 1) having a configuration in which a MOS transistor as a VMIS and a photodiode are connected, the cathode side of the photodiode is connected to the drain side, and the anode side is connected to the back gate side. A solid-state imaging device mixed noise suppression method including light receiving units (for example, the light receiving unit 1 in FIG. 1) arranged in a matrix in a predetermined number in the column direction,
The ground voltage whose voltage level changes in response to the level fluctuation of the mixed noise is used as one input, and the pixel signal from the pixel in the pixel signal detection period or the noise component charge immediately after resetting the pixel is used as the other input. A plurality of capacitive elements (for example, pixel signals in FIG. 1) via source lines (for example, vps1 and vps2 in FIG. 1) formed by commonly connecting the source electrode sides of the MOS transistors in the pixels in the vertical direction of the light receiving unit. When accumulating and holding the capacitors c1-1 and c1-2 for storage and the noise component storage capacitors c2-1 and c2-2) immediately after resetting the pixels,
One input of the plurality of capacitive elements is connected to the same voltage location as the gate voltage of the MOS transistor during the pixel signal detection period, and the charge of the noise signal immediately after the pixel signal or the pixel is reset This is a mixed noise suppression method for a solid-state imaging device, characterized in that accumulation and holding is performed from the other input.
With such a configuration, the same operational effects as in the case of the first invention can be obtained.

Hereinafter, embodiments of a solid-state imaging device according to the present invention will be described with reference to the drawings.
(Embodiment)
(Constitution)
FIG. 1 is a diagram illustrating a circuit configuration of a solid-state imaging device according to an embodiment of the present invention.
First, the configuration and the function of each part will be described.
This solid-state imaging device includes a light receiving unit 1, a vertical scanning circuit 2, a driving circuit 3, a reset circuit 4, a line memory group 5, a horizontal scanning circuit 6, and a subtraction circuit 7.
Among them, the light receiving unit 1 is composed of an insulated gate MOS transistor for detecting an image signal as a VMIS and a photodiode, the cathode side of the photodiode is connected to the drain side, and the anode side is connected to the back gate side. A predetermined number of pixels (indicated by a dotted frame) are arranged in a matrix in the row direction and the column direction. However, in order to simplify the description in FIG. 1, 2 × 2 pixels are shown, and the reference symbols are also based on this. In this case, the MOS transistor portion also has a high concentration buried layer for accumulating photogenerated charges generated by light irradiation with a photodiode provided in the well region under the gate electrode in the vicinity of the source region. The pixel signal is detected by modulating the threshold voltage by accumulating charges in the high concentration buried layer.

  The vertical scanning circuit 2 is supplied with a low-level control voltage Vpgl and a high-level control voltage Vpgh from an external control voltage generator (not shown), and at the gate electrode side of the MOS transistor in each pixel in the horizontal direction of the light receiving unit 1 Are connected to the gate lines vpg1 and vpg2 that are connected in common, and the gate electrodes of the MOS transistors are turned on during the pixel signal detection period in accordance with the high-level control voltage Vpgh for the gate lines vpg1 and vpg2. A scanning signal is output for each row line. Further, as will be described in detail later, the vertical scanning circuit 2 transmits a pixel signal and a noise component immediately after resetting the pixel to the selected capacitive element of the line memory group 5 by switching control when reading out the pixel.

The drive circuit 3 is connected to a drain line vpd formed by commonly connecting the drain electrode side of the MOS transistor and the cathode side of the photodiode in each pixel in the horizontal direction of the light receiving unit 1, and applies a drive voltage to be applied to each drain line vpd. By controlling, accumulation of optical signals and readout of pixel signals are performed. Note that the drain line vpd itself can be regarded as a configuration electrically connected in common on all pixels.
The reset circuit 4 is connected to source lines vps1 and vps2 formed by commonly connecting the source electrode sides of the MOS transistors in the pixels in the vertical direction of the light receiving unit 1, and is connected to each pixel via the source lines vps1 and vps2 at the time of pixel reset. Apply reset voltage to reset.

The line memory group 5 is connected to the vertical scanning circuit 2 whose one end is connected to the source lines vps1 and vps2 during the pixel signal detection period and whose other end is the same voltage as the gate voltage of the MOS transistor during the pixel signal detection period. As a plurality of capacitive elements that are connected to the input high-level control voltage Vpgh line and store and hold the pixel signal from the pixel from which the scanning signal is output or the noise component charge immediately after resetting the pixel. Capacitor c1-1, c2-1, c1-2, c2-2.
In the case of the conventional line memory group, the other end side of each capacitive element is grounded and maintained at the reference voltage. In the present embodiment, each capacitor c1-1, c2-1, c1-2, c2 The other feature is that the other end side of -2 is connected to the line of the high-level control voltage Vpgh.

  Further, in the case of the line memory group 5 here, the detailed configuration will be described. One end side of a pair of capacitors c1-1 and c2-1 and another pair of capacitors c1-2 and c2-2 is Each is connected in parallel to the source lines vps1 and vps2 via a switch. Therefore, the vertical scanning circuit 2 separately switches the two systems of switching signals to the one side group or the other side group of the paired switches and sends them. At the time of the first pixel readout, the pixel signal is transmitted to the first line memory group composed of the capacitors c1-1 and c1-2 on one side of the pair configuration, and the charges of the pixel signal are transferred to the capacitors c1-1 and c1-2. Accumulate and hold. At the time of reading the next pixel immediately after the reset, the noise component immediately after resetting the pixel is transmitted to the second line memory group consisting of the capacitors c2-1 and c2-2 on the other side, and the capacitors c2-1 and c2- In 2, the charge of the noise component immediately after resetting the pixel is accumulated and held.

  The horizontal scanning circuit 6 includes another pair of switch sets connected to one end side of a pair of capacitors c1-1 and c2-1 and another pair of capacitors c1-2 and c2-2. Is transmitted to each switch and is stored in the capacitors c1-1 and c1-2 of the first line memory group by switching and closing each switch. The charge of the noise component immediately after resetting the pixels accumulated in the capacitors c1-2 and c2-2 of the second line memory group to the positive line connected to the positive side of the subtraction circuit 7 Are respectively transmitted to the negative electrode line connected to the negative electrode side of the subtraction circuit 7.

The subtracting circuit 7 includes the charge of the pixel component signal accumulated in the capacitors c1-1 and c1-2 of the first line memory group and the pixel accumulated in the capacitors c1-2 and c2-2 of the second line memory group. The difference from the charge of the noise component immediately after resetting is sequentially output as an image signal of the output voltage Vout.
The line memory group 5 including the connection configuration of each switch described here is divided into a first line memory group and a second line memory group, and pixel component signals and pixels are further extracted from these line memory groups. The detailed configuration of the horizontal scanning circuit 6 including the connection configuration of each switch for reading out the noise component immediately after resetting is within the scope of well-known technology. In addition, the storage and holding function of each capacitive element according to the present embodiment is changed, the capacitors c2-1 and c2-2 store and hold the charge of the pixel signal, and the capacitors c1-1 and c1-2 reset the pixel. A configuration may be adopted in which the charge of the immediately following noise component is inverted and stored.

(Operation)
Next, the operation will be described.
FIG. 2 is a timing chart of signals in the respective units during the operation process according to the solid-state imaging device shown in FIG.
In the operation processing related to the solid-state imaging device shown in FIG. 2, a T0 period preceding one horizontal period 1H is an exposure period, and is a period in which photocharges received by the photodiodes of each pixel of the light receiving unit 1 are accumulated. After the exposure period T0, the period changes to one horizontal period 1H. One horizontal period 1H is divided into a blanking period T1 to T3 and a subsequent horizontal scanning period / exposure period T4.
The initial blanking period T1 is an initial pixel reading period, and is a period in which a pixel signal corresponding to the amount of light received before that is read.

  Here, the case where the pixel in the first row in the horizontal direction is the readout row and the second row is a non-selected row will be described. For example, the gate line vpg1 in the first row is set to the high level control voltage Vpgh (= 2.5 V). By setting the drain line vpd to 3.3 V, pixel signals corresponding to the amount of light are output to the source lines vps1 and vps2. The source lines vps1 and vps2 are connected to the pixels in the vertical direction in common, but the source line vps2 in the non-selected row is the highest because a low level control voltage Vpgl (= 1V) is applied. The pixel signal of the readout row, which is the source voltage, is output to the source lines vps1 and vps2, and is connected to the capacitors c1-1 and c1-2 of the first line memory group connected via the switch by the switching control of the vertical scanning circuit 2. Accumulated and retained.

  The middle blanking period T2 is a period during which the pixels are reset. Here, for example, when the gate line vpg1 of the readout row is set to high impedance HiZ and a voltage of 5 V is applied to the source lines vps1 and vps2, the gate line vpg1 is high impedance HiZ, so the source voltage of the source lines vps1 and vps2 The voltage of the gate line vpg1 further increases to 6V due to the capacitance between the gate and the source. As a result, the pixel connected to the gate line vpg1 has a channel having a high voltage of 5 V, so that the photocharge accumulated in the pixel is discharged and the pixel is reset. Since the gate line vpg2 of the non-selected row is given a low voltage of a low level control voltage Vpgl (= 1V) and the MOS transistor of the pixel is in the off state even when the source lines vps1 and vps2 are 5V, the pixel Is not reset.

The latter blanking period T3 is a next pixel readout period, and is a period in which a noise component immediately after resetting a pixel that is a pixel output immediately after reset is read out.
Here, as in the case of the initial blanking period T1, the pixels in the first row in the horizontal direction are read out, the second row is set as a non-selected row, and the gate line vpg1 in the first row is set to the high level control voltage Vpgh ( = 2.5V), when the drain line vpd is 3.3V, the noise component immediately after resetting the pixel in the readout row, which is the highest source voltage, is output to the source lines vps1 and vps2, and is connected via a switch. Stored in the capacitors c2-1 and c2-2 of the second line memory group.

  The horizontal scanning period / exposure period T4 is a period in which signals accumulated in the line memory group 5 are output. The line memory is sequentially selected via a switch by switching control of the horizontal scanning circuit 6, and the initial blanking period T1. And the pixel component signals accumulated and held in the capacitors c1-1 and c1-2 in the first line memory group and the capacitors c2-1 and c2-2 in the second line memory group in the second blanking period T3. The noise component immediately after resetting the pixel is output to the positive line and the negative line of the subtraction circuit 7, respectively. The subtraction circuit 7 sequentially outputs the difference between the pixel component signal in the initial blanking period T1 and the noise component immediately after resetting the pixels in the later blanking period T3 as an image signal of the output voltage Vout. The pixel signal accumulated in the initial blanking period T1 includes a pixel offset component and low-frequency noise, but a difference from the noise component immediately after resetting the pixel read in the late blanking period T3 is taken. Thus, an image output having an image quality with the noise component canceled is obtained. In the horizontal scanning period / exposure period T4, the process proceeds to the next exposure period following the output of the waveform level of the image signal.

  In the case of the solid-state imaging device according to the present embodiment, the other end side of each capacitive element (each line memory) is respectively connected to a line of a high level control voltage Vpgh which is the same voltage location as the gate voltage of the MOS transistor during the pixel signal detection period. Since they are connected, the pixel component signals accumulated and held in the capacitors c1-1 and c1-2 of the first line memory group in the initial blanking period T1 and the second line memory group in the later blanking period T3 Even if the noise voltage Vnoise due to mixed noise is mixed in the high-level control voltage Vpgh line with respect to both the noise component immediately after resetting the pixels stored and held in the capacitors c2-1 and c2-2, It can be considered that the influence of the noise voltage Vnoise is eliminated.

That is, in the configuration in which the other end side of each line memory is connected to the line of the high-level control voltage Vpgh, the capacitors c1-1 and c1-2 of the first line memory group and the latter period in the initial blanking period T1. The charge Q accumulated in the capacitors c2-1 and c2-2 of the second line memory group during the blanking period T3 is related to the capacitance value C of the line memory (single unit), and the above equation (3) is used. For example, it is expressed as follows.
Q = C · {(Vpgh + Vnoise) −Vth (Φ) − (2Id / μCox) ^0.5 · (L / W) ^0.5 − (Vpgh + Vnoise)} = C · {−Vth (Φ) − (2Id / μCox) ^0.5 · ( L / W) ^0.5 } (4)

From equation (4), it can be seen that even if a noise voltage Vnoise due to mixed noise is applied to the line of the high-level control voltage Vpgh, the influence of the noise voltage Vnoise is eliminated.
Therefore, the waveform of the image signal output from the subtraction circuit 7 of the solid-state imaging device according to the present embodiment is not affected by the mixed noise at the voltage level, and is horizontal due to the noise mixed in the gate line of the light receiving unit 1 in the conventional device. The horizontal streak image generated by affecting the pixels in the direction can be accurately suppressed.

  As described above, in the solid-state imaging device according to the present embodiment, the other end sides of the capacitors c1-1, c2-1, c1-2, and c2-2 constituting the line memory group 5 are controlled at a high level. By connecting to the voltage Vpgh line, even if the noise voltage Vnoise due to mixed noise is applied to the high-level control voltage Vpgh line (of course, the noise voltage Vnoise is applied to the gate lines vpg1 and vpg2 of the light receiving unit 1). This also applies to the pixel component signal accumulated and held in the capacitors c1-1 and c1-2 of the first line memory group and the capacitors c2-1 and c2-2 of the second line memory group. The influence of the noise voltage Vnoise can be eliminated with respect to both the noise component immediately after resetting the pixel to be reset. As a result, a horizontal streak image does not appear in the image signal of the output voltage Vout obtained by the difference between the pixel component signal and the noise component immediately after resetting the pixel, and a high image quality that is difficult to obtain with conventional devices can be obtained. In addition, the solid-state imaging device according to the present embodiment has a special advantage that it can be realized easily and inexpensively because it can be configured only by changing wiring without requiring a special circuit or device.

(Application 1)
In the case of the solid-state imaging device according to the above-described embodiment, the line of the high-level control voltage Vpgh and the gate line vpg1 can be regarded as being almost in the same potential state, and thus the capacitors c1-1 and c2 constituting the line memory group 5 are used. Even when the other end sides of -1, c1-2, and c2-2 are connected to the gate line vpg1, respectively, the same effect can be obtained.

(Application example 2)
The technical gist for canceling the mixed noise in the solid-state imaging device described above is also established as a mixed noise suppression method for the solid-state imaging device.
Specifically, as a mixed noise suppression method for a solid-state imaging device including the light receiving unit 1 similar to the above embodiment,
The ground voltage whose voltage level changes corresponding to the level fluctuation of the mixed noise is set as one input, and the pixel signal from the pixel in the pixel signal detection period or the charge of the noise component immediately after resetting the pixel is set as the other input, Capacitors c1-1 and c1-2 for storing pixel signals, which are each capacitive element, are connected via source lines (vps1, vps2) formed by commonly connecting the source electrodes of MOS transistors in pixels in the vertical direction of the light receiving unit 1. When storing and holding in the noise component storage capacitors c2-1 and c2-2 immediately after resetting, the one input of each capacitive element is connected to the same voltage location as the gate voltage of the MOS transistor during the pixel signal detection period, respectively. In addition, the charge of the noise component immediately after resetting the pixel signal or the pixel is accumulated and held from the other input.
Thereby, there exists an effect similar to the case of the said embodiment.

It is the figure which illustrated the circuit configuration of the solid-state imaging device concerning the embodiment of the present invention. 3 is a timing chart of signals in respective units during operation processing according to the solid-state imaging device shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Light-receiving part, 2 Vertical scanning circuit, 3 Drive circuit, 4 Reset circuit, 5 Line memory group, 6 Horizontal scanning circuit, 7 Subtraction circuit, c1-1, c1-2, c2-1, c2-2 Capacitor

Claims (3)

The pixel is composed of a MOS transistor and a photodiode as a threshold modulation type image pickup device, and the cathode side of the photodiode is connected to the drain side and the anode side is connected to the back gate side in the row direction and the column direction, respectively. A light receiving section arranged in a matrix of a predetermined number;
A scanning signal for turning on the gate electrode of the MOS transistor during a pixel signal detection period is applied to a gate line formed by commonly connecting the gate electrode side of the MOS transistor in the pixel in the horizontal direction of the light receiving unit. A vertical scanning circuit for outputting each row line;
One end side is connected to the source line formed by commonly connecting the source electrode sides of the MOS transistors in the pixels in the vertical direction of the light receiving unit in the pixel signal detection period, and the other end side is connected to the ground. A line memory group consisting of a plurality of capacitive elements that accumulate and hold the charge of the noise signal immediately after resetting the pixel signal or the pixel from the pixel from which the scanning signal is output;
Have
The other end side of the plurality of capacitive elements in the line memory group is connected to the same voltage location as the gate voltage of the MOS transistor during the pixel signal detection period.   2. The solid-state imaging device according to claim 1, wherein the other end side of the plurality of capacitive elements in the line memory group is connected to a high-level control voltage line input to the vertical scanning circuit. The pixel is composed of a MOS transistor and a photodiode as a threshold modulation type image pickup device, and the cathode side of the photodiode is connected to the drain side and the anode side is connected to the back gate side in the row direction and the column direction, respectively. A mixed noise suppression method for a solid-state imaging device including light receiving units arranged in a matrix of a predetermined number,
The ground voltage whose voltage level changes in response to the level fluctuation of the mixed noise is used as one input, and the pixel signal from the pixel in the pixel signal detection period or the noise component charge immediately after resetting the pixel is used as the other input. , When accumulating and holding in a plurality of capacitive elements via a source line formed by commonly connecting the source electrode side of the MOS transistor in the pixel in the vertical direction of the light receiving unit,
One input of the plurality of capacitive elements is connected to the same voltage location as the gate voltage of the MOS transistor during the pixel signal detection period, and the charge of the noise signal immediately after the pixel signal or the pixel is reset A method for suppressing mixed noise for a solid-state imaging device, wherein accumulation and holding is performed from the other input.

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