JP5000248B2 - Information processing apparatus and information processing method - Google Patents

Description

  The present invention relates to an information processing apparatus capable of register renaming in an information processing apparatus that performs various operations using a register capable of storing a plurality of data, and more particularly to a register even when executing a masked operation. -It relates to an information processing apparatus capable of renaming.

  Conventionally, as described in Patent Document 1, there is a technique for improving instruction execution performance in an information processing apparatus by register renaming.

  Note that register renaming refers to register contention by regarding another register as virtually the same register when data is read from or written to the same register when executing multiple instructions. This is a technique for avoiding

Japanese Patent Laid-Open No. 9-311788

  However, when register renaming is executed based on the prior art in an information processing apparatus that executes an operation using a register capable of storing a plurality of data, the following problems occur.

  If register renaming is performed in an instruction that executes an operation with a mask, data corruption occurs.

  This is because when registering a logical register and a physical register by register renaming, the physical register number and the WP (write pointer) or RP (read pointer) used for designating the data storage position are synthesized, and the logical register This is because a pointer for designating the data storage position is generated. Since all the data storage positions of the physical register are associated with the data storage position of the logical register using the physical register number, it can be associated with the logical register only in physical register units. In other words, when a physical register associated with a logical register is changed to another physical register by register renaming, the logical register associated with each data storage location of the physical register before register renaming All of the data storage positions are changed to the data storage positions of the new logical register, and the logical register and other physical registers are associated with each other. Specifically:

  Assume that physical registers No. 1 and No. 1 can store four data, and each data storage location is “00”, “01”, “10”, “11” (2-bit binary number) by WP or RP. ). When the logical register and the physical register 0 are associated with each other, the physical register number “0” and the WP or RP “00”, “01”, “10”, “11” are combined, and “000”, The data storage position of the logical register represented by “001”, “010”, and “011” is associated with the data storage position of physical register 0. If the logical register and physical register number 1 are then associated by register renaming, the physical register numbers “1”, “00”, “01”, “10”, and “11” are combined, and “100” ”,“ 101 ”,“ 110 ”,“ 111 ”, the data storage position of the logical register and the data storage position of the physical register 1 are associated with each other. As described above, according to the conventional technique, all the data storage positions of the logical registers associated with the physical registers are changed by register renaming. That is, for each physical register, the data storage position of the logical register associated by register renaming is fixed.

  Therefore, if register renaming is performed when an instruction with a mask is executed, the contents of the physical register are replaced, including the data storage position where data writing should not be executed. As described above, in the conventional technique, it is necessary to suppress register renaming when executing an operation with a mask, which hinders improvement in instruction execution performance.

  The present invention has been made in view of the above problems, and an object of the present invention is to enable register renaming for a register capable of storing a plurality of data even when a masked instruction is executed.

  In order to solve the above problems, an information processing apparatus according to the present invention includes a plurality of first storage areas including a plurality of first storage areas for storing data, and a plurality of second storage areas for storing the data. A second storage area in which the second storage area is designated by position designation information, first data used for designation of the first storage area, and designation by the first data And a controller that synthesizes the second data corresponding to the first storage area thus generated to generate the position designation information.

  The present invention combines the first data used for designating the first storage area of the first storage area and the second data corresponding to the first storage area designated by the first data. Thus, by generating position designation information for designating the second storage area, it becomes possible to designate the second storage area to be associated for each first storage area. Therefore, even when register renaming is performed during execution of an operation with a mask, it is possible to specify only a storage area where data writing is required and perform association by register renaming. As described above, according to the present invention, it is possible to perform register renaming for a register capable of storing a plurality of data even when executing an operation with a mask, thereby effectively improving instruction execution performance. The special effect of being able to do is obtained.

  Next, an embodiment of the present invention will be described. In the following description, a vector register is used as an example of a register capable of storing a plurality of data. However, the present invention is not limited to the vector register, and the present invention can be applied to a register in which a plurality of storage areas (entries) for storing data are provided.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIG.

  Referring to FIG. 1, an information processing device 13 according to the first embodiment of the present invention includes a vector register 1, a WD register 2, an RD register 3, a WP register 4, an RP register 5, a mask unit 6, a register management unit 7, An extension bit unit 8, a pointer synthesis unit 9, a WE register 10, a WE control unit 11, and a register control unit 12 are included.

  The vector register 1 is accessed as a logical vector register from the program. The vector register 1 is given a logical vector register number. The logical vector register number is an identifier (for example, a variable) when accessing the vector register 1 by a program. From the program, the vector register 1 is accessed based on the logical vector register number.

  The vector register 1 is constituted by a physical vector register. A physical vector register is a physical storage location of data to be operated.

  The vector register 1 has an entry for storing data used for calculation. The physical vector register also has an entry for storing data used for calculation.

  The logical vector register and the physical vector register are associated by register renaming. The position of each entry of the logical vector register and the physical vector register is designated by using a pointer. The present invention associates a logical vector register and a physical vector register for each entry in register renaming. An extension bit associated with each entry of the physical vector register is provided, and the pointer synthesis unit 9 synthesizes the extension bit and a pointer for designating the entry position of the physical vector register, and designates the entry of the logical vector register Create a pointer to That is, for each entry in the physical vector register, a pointer corresponding to the entry in the logical vector register is created. This makes it possible to associate the entry of the logical vector register into which data is written for each entry of the physical vector register when executing the operation.

  Next, each configuration shown in FIG. 1 will be described.

  The vector register 1 stores a series of ordered vector data to be operated. The vector register 1 has a plurality of entries, and vector data is stored for each entry. The vector data is composed of a plurality of words (hereinafter referred to as elements). A word is a unit of data. Therefore, each entry of the vector register 1 stores vector data elements. The number of elements specified by the instruction is read out one element per machine cycle from the entry of the vector register 1 specified by the pointer. Further, the vector data of the operation result is sequentially stored in the entry of the vector register 1 designated by the pointer. The vector register 1 is composed of a logical vector register having a predetermined number of elements. That is, the logical vector register is accessed in units of a predetermined number of elements. The logical vector register is given a logical vector register number, and the vector register 1 is accessed from the program by the logical vector register number. That is, the vector register 1 is a virtual register that is accessed from the program in units of a predetermined number of elements. The logical vector register is configured by entries corresponding to a predetermined number of elements among the entries of the vector register 1. The vector register 1 includes a predetermined number of physical vector registers. Therefore, an element read / written to / from the entry of the vector register 1 by the program is physically read / written from / to the corresponding entry of the physical vector register. That is, the logical vector register entry and the physical vector register entry have a one-to-one correspondence. A physical vector register number is assigned to the physical vector register, and the physical vector register is designated by the number.

  The WD register 2 temporarily stores elements of vector data to be written to the vector register 1. The WD is read as “write data”.

  The RD register 3 temporarily stores elements of vector data read from the vector register 1. The RD is read as “read data”.

  The WP register 4 stores a WP corresponding to each entry of the physical vector register. The WP register 4 adds 1 to the value of WP in synchronization with the writing to the vector register 1. The WP register 4 notifies the WP to the extension bit unit 8 and the pointer synthesis unit 9 via the path 40. Note that WP reads “write pointer”.

  The RP register 5 stores an RP corresponding to each entry of the physical vector register. The RP register 5 adds 1 to the value of RP in synchronization with reading from the vector register 1. The RP register 5 notifies the extension bit unit 8 and the pointer synthesis unit 9 via the path 50. RP is read as “read pointer”.

  The mask unit 6 is composed of the same number of bits as the number of elements of the logical vector register. This means that the number of bits is the same as the number of elements of the physical vector register. The mask unit 6 has a mask register in which each bit corresponds to each entry of the logical vector register in which the element is stored. Each bit of the mask register also corresponds to each entry of the physical vector register in which the element is stored. The mask unit 6 specifies, for each entry in which an element is stored, whether or not to write the operation result to the logical vector register specified by the instruction when an operation with a mask is executed by setting the mask register. . The mask unit 6 sets “1” to a bit of a mask register corresponding to an element (hereinafter referred to as a valid element) stored in an entry to be written. Further, the mask unit 6 sets “0” to a bit of a mask register corresponding to an element (hereinafter referred to as an invalid element) stored in an entry to which writing is not performed. Whether the mask unit 6 uses the 1 bit of the contents of the mask register corresponding to the entry to be written and the value of the mask register, via the path 60, with respect to the extension bit unit 8 and the WE control unit 11 Is notified as mask information.

  The register management unit 7 controls the correspondence between the logical vector register and the physical vector register when register renaming is performed. The register management unit 7 manages a physical vector register number in which writing is executed as a write physical vector register number and a physical vector register number in which reading is executed as a read physical vector register number. The register management unit 7 notifies the extension bit unit 8 via the path 70 of the write physical vector register number. The register management unit 7 notifies the extension bit unit 8 of the read physical vector register number via the path 71. The write physical vector register number and the read physical vector register number are transmitted in binary numbers. The register management unit 7 has a flag indicating whether or not the element of the vector data in the entry is in use for each entry of the vector register 1. This means that, at the same time, the register management unit 7 manages whether or not the element of the vector data in the entry is in use for each entry of the logical vector register. In use means a state in which the element cannot be overwritten with another element. The flag may be configured to have a value of 1 bit, for example, “1” if an element in the entry is in use, and “0” otherwise. The register management unit 7 transmits flags for all entries to the pointer synthesis unit 9 via the path 72. Note that the register management unit 7 transmits flags for all entries to the pointer synthesis unit 9 via the path 72 every time the contents of the flag are updated. The register management unit 7 manages the correspondence for each entry between the logical vector register and the physical vector register after register renaming. That is, the register management unit 7 manages the correspondence for each entry with the physical vector register in units of the number of elements of the logical vector register.

  The extension bit unit 8 receives WP and RP via the path 40 and the path 50, respectively. The extension bit unit 8 receives mask information from the mask unit 6 via the path 60. The extension bit unit 8 receives the write physical vector register number and the read physical vector register number from the register management unit 7 from the path 70 and the path 71, respectively. The extension bit unit 8 generates an extension bit corresponding to each entry of the physical vector register on a one-to-one basis. The extension bit unit 8 generates an extension bit corresponding to the entry specified by the WP, and notifies the pointer synthesis unit 9 via the path 80 as a write extension bit (hereinafter referred to as WEX). The extension bit unit 8 generates an extension bit corresponding to the entry specified by the RP, and notifies the pointer synthesis unit 9 via the path 81 as a read extension bit (hereinafter REX). The extension bit unit 8 includes an extension bit register that stores an extension bit for each corresponding entry. The extension bit unit 8 includes an extension bit register corresponding to each physical vector register.

  The pointer synthesis unit 9 receives WP and RP via the path 40 and the path 50, respectively. WEX and REX are received from the extension bit unit 8 via the path 80 and the path 81, respectively. The pointer synthesis unit 9 generates a write extension pointer for designating an entry for writing vector data to the vector register 1 from WP and WEX. Further, the pointer synthesis unit 9 generates a read extension pointer for designating an entry for reading vector data from the RP and REX to the vector register 1. The pointer synthesis unit 9 transmits the write extension pointer and the read extension pointer to the vector register 1 via the path 90 and the path 91, respectively. The pointer synthesis unit 9 receives a flag indicating whether or not the entry can be used from the register management unit 7 via the path 72. The pointer synthesizer 9 determines whether or not the entry of the vector register 1 corresponding to the write extension pointer generated from WEX can be used using the flag received from the register manager 7. When the entry corresponding to the write extension pointer is unusable, the pointer synthesis unit 9 changes the value of WEX received via the path 80 and generates a new write extension pointer. The pointer synthesis unit 9 transmits the generated new write extension pointer to the extension bit unit 8 via the path 94.

  The WE register 10 instructs the vector register 1 on the write operation timing. The WE register 10 stores “1” when valid write data exists in the WD register 2 and “0” when there is no valid write data. The WE register 10 notifies the WE control unit 11 of the value stored in itself. WE is read as “write enable”.

  The WE control unit 11 receives the value of the WE register 10 and the mask information from the mask unit 6 via the path 60. When it is notified by the mask information that the value of the mask register is to be used, the WE control unit 11 calculates the logical product of the mask bit and the value of the WE register 10 and transmits it to the vector register 1 as a WE signal. When it is notified by the mask information that the value of the mask register is not used, the value of the WE register 10 is transmitted as it is to the vector register 1 as a WE signal. In the vector register 1, writing is executed when the WE signal is “1”, and writing is not executed when it is “0”.

  The register control unit 12 controls the operation timing of the WP register 4 and the RP register 5, the operation timing of the extension bit register in the extension bit unit 8, and the operation timing of the WE register 10 using the instruction issuance as a trigger.

  In the following, the vector register 1 is composed of one logical vector register (logical vector register No. 0) having 4 elements, and has two physical vector registers (physical vector registers 0 and 1). The first embodiment will be described in more detail. It is assumed that the number of elements of each physical vector register is four.

  First, the association between each entry in the logical vector register and the entry in the physical vector register will be described.

  FIG. 2 shows a correspondence table of association between each entry in the physical vector register and each entry in the logical vector register. The association with respect to the physical vector register No. 0 will be described with reference to FIG. In FIG. 2, the association is described using the value of the WP register 4, but the association can also be performed using the value of the RP register 5.

  For the association, an extension bit stored in an extension bit register (hereinafter, physical 0 extension bit register) corresponding to the physical vector register 0 is used.

  The physical vector register 0 entry 00 (the binary number “00” represents the entry number) corresponds to the WP register 4 value “00” (binary number) and the WP register 4 value “00”. The value of the physical 0 extension bit register is used to associate with the entry in the logical vector register. When the value of the physical 0 extension bit register is “0”, the write extension pointer generated by combining the value and the value “00” of the WP register 4 is “000” (binary number), and the entry of the vector register 1 Associated with e0 (ie, entry 0 in the logical vector register). When the value of the physical 0 extension bit register is “1”, the physical vector register No. 0 has a write extension pointer of “100” and is associated with the entry e4 of the vector register 1 (that is, entry 0 of the logical vector register). The physical vector register 1 is also associated in the same manner using the value of the physical 1 extension bit register. In this way, the association is executed based on the correspondence table shown in FIG. However, FIG. 2 is an example and is not limited to the association by the correspondence table shown in FIG.

  The association will be specifically described with reference to FIG.

  The vector register 1 has entries e0 to e7. As described above, the vector register 1 is composed of a logical vector register having four elements. That is, at the time of instruction execution, four of the eight entries (e0 to e7) of the vector register 1 constitute a logical vector register. The physical vector registers No. 0 and No. 1 have entries fe0 to fe3, respectively. Assume that the contents of e0 to e7 of the vector register 1 are A, B, C, D, E, K, initial values (-), and H. When the contents of the physical 0 extension bit register are 0101, the corresponding values of the WP register 4 and the respective values of the physical 0 extension bit register are synthesized, and the entries fe0 to fe3 of the physical vector register 0 are respectively set to e0. , E5, e2, e7. In FIG. 3, they are represented as fe0 (e0), fe1 (e5), fe2 (e2), and fe3 (e7). The contents of the physical vector register No. 0 are A, K, C, and H. Thus, the four entries of the logical vector register are associated with e0, e5, e2, and e7 of the vector register 1, respectively.

  When the contents of the physical 1 extension bit register are 1001, the corresponding values of the WP register 4 and the respective values of the physical 1 extension bit register are synthesized, and the entries fe0 to fe3 of the physical vector register 1 are respectively e4. , E1, e2, e7. In FIG. 3, they are represented as fe0 (e4), fe1 (e1), fe2 (e2), and fe3 (e7). The contents of the physical vector register 1 are E, B, C, and H. Thus, the four entries of the logical vector register are associated with e4, e1, e2, e7 of the vector register 1, respectively.

  As described above, each entry in the physical vector register and each entry in the logical vector register are associated with each entry.

  Next, the extension bit unit 8 will be described in detail with reference to FIGS. 4 and 5.

  The extension bit unit 8 includes a physical 0 extension bit register 82 and a physical 1 extension bit register 83 respectively corresponding to the physical vector register 0 and the physical vector register 1. The extension bit unit 8 includes an update unit 84, a read selector 85, and an extension bit register control unit 86.

  The physical 0 extension bit register 82 stores a 1-bit value corresponding to each entry of the physical vector register 0. The value stored in the physical 0 extension bit register 82 is used to extend the number of bits of each value of WP and RP by 1 bit.

  The physical 1 extension bit register 83 stores a 1-bit value corresponding to each entry of the physical vector register 1. The value stored in the physical 1 extension bit register 83 is used to extend the number of bits of each value of WP and RP by 1 bit.

  The physical 0 extension bit register 82, the physical 1 extension bit register 83, and the update unit 84 are connected via a path 820 and a path 830, respectively.

  The physical 0 extension bit register 82, the physical 1 extension bit register 83, and the read selector 85 are connected through a path 821 and a path 831, respectively.

  The update unit 84 receives a 1-bit value from the physical 0 extension bit register 82 via the path 820. In addition, the update unit 84 receives a 1-bit value from the physical 1 extension bit register 83 via the path 830. The update unit 84 receives the write physical vector register number via the path 70 and receives mask information via the path 60. The update unit 84 generates a new value and WEX for updating the contents of the physical 0 extension bit register 82 or the physical 1 extension bit register 83. The update unit 84 updates the contents of the physical 0 extension bit register via the path 844. In addition, the update unit 84 updates the contents of the physical 1 extension bit register via the path 845.

  The read selector 85 receives a 1-bit value from the physical 0 extension bit register 82 via the path 821. The read selector 85 receives a 1-bit value from the physical 1 extension bit register 83 via the path 831. The read selector 85 receives the read physical vector register number via the path 71. The read selector 85 selects one of the 1-bit values received from the physical 0 extension bit register 82 and the physical 1 extension bit register 83 based on the read physical vector register number. When the read physical vector register number specifies physical vector register 0, the read selector 85 selects the path 821 and selects the value received from the physical 0 extension bit register. When the read physical vector register designates the physical vector register 1, the read selector 85 selects the path 831 and selects the value received from the physical 1 extension bit register.

  The extension bit register control unit 86 controls the physical 0 extension bit register 82 and the physical 1 extension bit register 83 according to an instruction from the register control unit 12. That is, the extension bit register control unit 86 controls the operation timing of the physical 0 extension bit register 82 and the physical 1 extension bit register 83.

  The physical 0 extension bit register 82 holds a value of 1 bit of the number of entries of the physical vector register 0, that is, the number of elements stored in the physical vector register 0. Each value held by the physical 0 extension bit register 82 has a one-to-one correspondence with each entry of the physical vector register 0. The value of the physical 0 extension bit register 82 corresponding to the entry of the physical vector register 0 is read by WP and RP. This is because WP and RP have a one-to-one correspondence with each entry in the physical vector register.

  The value read by the WP is transmitted to the update unit 84 via the path 820. The value read by the RP is transmitted to the read selector 85 via the path 821.

  The physical 0 extension bit register 82 updates the contents of the entry of the corresponding physical 0 extension bit register 82 via the path 844 according to an instruction from the update unit 84.

  The value stored in the physical 0 extension bit register 82 is the most significant bit of the read extension pointer or write extension pointer (both binary numbers) generated by the pointer synthesis unit 9.

  The physical 1 extension bit register 83 holds a value of 1 bit of the number of entries of the physical vector register 1, that is, the number of elements stored in the physical vector register 1. Each value held by the physical 1 extension bit register 83 corresponds to each entry of the physical vector register 1 on a one-to-one basis. The value of the physical 1 extension bit register 83 corresponding to the entry of the physical vector register 1 is read by WP and RP. This is because WP and RP have a one-to-one correspondence with each entry in the physical vector register.

  The value read by the WP is transmitted to the update unit 84 via the path 830. The value read by the RP is transmitted to the read selector 85 via the path 831.

  The physical 1 extension bit register 83 updates the contents of the corresponding entry of the physical 1 extension bit register 83 according to an instruction from the update unit 84 via the path 845.

  The value stored in the physical 1 extension bit register 83 is the most significant bit of the read extension pointer or write extension pointer (both binary numbers) generated by the pointer synthesis unit 9.

  Referring to FIG. 5, the update unit 84 includes a write selector 840, a mask identification circuit 841, an arithmetic circuit 842, and an update determination circuit 843.

  The write selector 840 selects either the path 820 or the path 830 according to the write physical vector register number received via the path 70. The write selector 840 transmits the 1-bit value received from the selected path to the arithmetic circuit 842.

  The mask identification circuit 841 receives the mask information via the path 60. When an instruction with a mask is executed, that is, when the mask information specifies that the value of the mask register is to be used, the value stored in the mask register corresponding to the entry of the physical vector register is used as the arithmetic circuit 842. Output for. When a normal instruction is executed, that is, when the mask information specifies that the value of the mask register is not used, 1-bit “1” is always output to the arithmetic circuit 842.

  The arithmetic circuit 842 calculates the exclusive OR (hereinafter referred to as XOR) of the value received from the write selector 840 and the value received from the mask identification circuit 841 to generate WEX. The arithmetic circuit 842 transmits the generated WEX to the pointer synthesis unit 9 via the path 80. The arithmetic circuit 842 also transmits the generated WEX to the update determination circuit 843. Since only the XOR operation is executed, the configuration of the operation circuit can be simplified, and register renaming can be realized even during execution of the masked operation while suppressing an increase in the amount of HW compared to the prior art.

  The update determination circuit 843 selects either the path 844 or the path 845 according to the write physical vector register number received via the path 70. The update determination circuit 843 selects the path 844 when the write physical vector register number is 0, and selects the path 845 when the write physical vector register number is 1. The update determination circuit 843 transmits the WEX and update instruction received from the arithmetic circuit 842 to the physical extension bit register via the selected path.

  When the write physical vector register number is 0, the write selector 840 selects the value of the physical 1 extension bit register 83 transmitted via the path 830 and outputs it to the arithmetic circuit 842. Further, when the write physical vector register number is 1, the write selector 840 selects the value of the physical 0 extension bit register 82 transmitted via the path 820 and outputs it to the arithmetic circuit 842.

  Next, the pointer composition unit 9 will be described in detail with reference to FIG.

  The pointer synthesis unit 9 has a WP synthesis circuit 92 and an RP synthesis circuit 93.

  The WP synthesis circuit 92 receives WP from the WP register 4 via the path 40. Further, the WP combining circuit 92 receives WEX from the arithmetic circuit 842 via the path 80. The WP synthesis circuit 92 synthesizes the values received from the respective paths and generates a write extension pointer. The WP synthesis circuit 92 synthesizes WEX and WP so that WEX becomes the most significant bit of the write extension pointer in the synthesis. Since WEX is 1 bit and WP is 2 bits, the write extension pointer is 3 bits. As shown in the table of FIG. 2, when WEX is “0”, the write extension pointer is associated with entries e0 to e3 (hereinafter referred to as the first half) of the vector register 1. When WEX is “1”, the write extension pointer is associated with entries e4 to e7 (hereinafter referred to as the latter half) of the vector register 1. The write extension pointer is notified to the vector register 1 via the path 90 as information for determining the entry of the vector register 1 (that is, the entry of the vector register 1 corresponding to the entry of the logical vector register).

  The RP synthesis circuit 93 receives the RP from the RP register 5 via the path 50. Further, the RP synthesis circuit 93 receives REX from the read selector 85 via the path 81. The RP synthesis circuit 93 synthesizes the values received from the respective paths and generates a read extension pointer. The RP synthesis circuit 93 synthesizes REX and RP so that REX is the most significant bit of the read extension pointer in the synthesis. Since REX is 1 bit and RP is 2 bits, the read extension pointer is 3 bits. When REX is “0”, the read extension pointer is associated with entries e0 to e3 (hereinafter referred to as the first half) of the vector register 1. When REX is “1”, the read extension pointer is associated with entries e4 to e7 (hereinafter referred to as the latter half) of the vector register 1. The read extension pointer is notified to the vector register 1 via the path 91 as information for determining the entry of the vector register 1 (that is, the entry of the vector register 1 corresponding to the entry of the logical vector register).

  The WP synthesis circuit 92 receives a flag indicating whether or not the element of the vector data in the entry of the vector register 1 is in use from the register management unit 7 via the path 72. The WP synthesis circuit 92 confirms the contents of the flag corresponding to the entry of the vector register 1 designated by the generated write extension pointer. If the flag confirms that the element is not in use, the WP synthesis circuit 92 notifies the vector register 1 via the path 90 of the generated write extension pointer.

  When the flag confirms that the element is in use, the WP combining circuit 92 changes the value of WEX received via the path 80. For example, the WP synthesis circuit 92 changes the received WEX value by adding (incrementing) 1 to the received WEX value or subtracting 1 from the received WEX value (decrement). Then, a write extension pointer is generated again, and the contents of the flag corresponding to the entry of the vector register 1 designated by the write extension pointer are reconfirmed. If the flag confirms that the element is not in use, the WP synthesis circuit 92 notifies the regenerated write extension pointer to the vector register 1 via the path 90. At the same time, the WP combining circuit 92 notifies the update determination circuit 843 of the changed WEX value via the path 94. Upon receiving the notification, the update determination circuit 843 changes the value of the corresponding physical extension bit register entry.

  If the element corresponding to the flag is still in use even if the contents of the flag corresponding to the regenerated write extension pointer are reconfirmed, the WP synthesis circuit 92 generates the first WEX received via the path 80. Wait until the element of the entry corresponding to the write extension pointer becomes available. That is, if there is no usable element even if the value of WEX received via path 80 is changed a predetermined number of times, the write extension generated by the first WEX received via path 80 The process waits until the entry element corresponding to the pointer becomes available. If the WEX value reaches the upper limit value or the lower limit value due to the change, the process waits until the entry element corresponding to the write extension pointer generated by the first WEX received via the path 80 becomes usable. It may be.

  By checking whether or not each entry in the vector register 1 is in use, even when register renaming is executed during execution of an operation with a mask, illegal overwriting of the register contents can be prevented and data corruption can be avoided. The effect is obtained.

  Next, in the configuration in which the vector register 1 is composed of one logical vector register (logical vector register No. 0) having four elements and two physical vector registers (physical vector registers No. 1 and No. 1), register renaming A method for associating the logical vector register and the physical vector register for each entry will be described in detail. The vector register 1 is accessed from the program as one logical vector register having 4 elements (4 entries). It is assumed that the number of elements of each physical vector register is four.

  With reference to FIGS. 7A to 7G, a description will be given of a case where three instructions (hereinafter, instruction 0, instruction 1, and instruction 2, respectively), which are normal instructions written in the logical vector register 0, are executed. In FIG. 7, the entries in the vector register 1 are e0 to e7, and the physical vector register entries are fe0 to fe3. Note that any four of the entries e0 to e7 of the vector register 1 are associated with the logical vector register 0th entry. That is, the logical vector register 0 entry associated with the physical vector register entry is any four of the vector register 1 entries.

  FIG. 7A shows an initial state. In an initial state, all values of the physical 0 extension bit register 82 are “0”, and all values of the physical 1 extension bit register 83 are “1”. In principle, each entry of physical vector register 0 is associated with the first half (e0 to e3) of entries e0 to e7 by register renaming, and each entry of physical vector register 1 is an entry (e0 to e7). This is because we want to associate it with the second half (e4 to e7). All entries in the vector register 1, all entries in the physical vector register 0, and all entries in the physical vector register 1 have initial values (-).

  A case where instruction 0 is executed will be described.

  Note that control information is transferred to the mask unit 6, the register management unit 7, and the register control unit 12 by issuing an instruction. Hereinafter, the same applies to the description of instruction execution.

  The logical vector register 0 of the instruction 0 is assumed to be designated as the physical vector register 0 by register renaming in the register management unit 7. Since the instruction 0 is a normal instruction, the output of the mask identification circuit 841 is “1”.

  FIG. 7B shows a state immediately before the vector data is written. Since it is a normal instruction, the outputs of the mask identification circuit 841 corresponding to each entry are all “1”. Since the write physical vector register number is “0” (actually expressed in binary, but displayed in decimal for convenience. The same applies hereinafter), the value of the physical 1 extension bit register 83 is selected by the write selector 840. The Therefore, the arithmetic circuit 842 performs an XOR operation on the output of the mask identification circuit 841 and the value of the physical 1 extension bit register 83 corresponding to the entry to which data is written. The calculation result is written to the corresponding entry of the physical 0 extension bit register 82 via the path 844 by the update determination circuit 843.

  The association between each entry in the physical vector register 0 and each entry in the logical vector register 0 is performed as follows.

  1) The corresponding 1-bit value (from the physical 0 extended bit register 82 and the physical 1 extended bit register 83) by the WP (binary “00”) corresponding to the entry 0 (fe0) of the physical vector register 0 Here, “0” and “1”) are respectively read by the extension bit register control unit 86. The read values are transmitted to the update unit 84 via the path 820 and the path 830, respectively.

  2) The mask identification circuit 841 receives the contents and mask information of the mask register corresponding to the WP from the mask unit 6 via the path 60. Since the instruction 0 is a normal instruction, the mask identification circuit 841 outputs a 1-bit value “1” to the arithmetic circuit 842 based on the mask information.

  3) The write selector 840 receives the write physical vector register number “0” via the path 70. Therefore, the write selector 840 selects the path 830 and transmits “1”, which is the value of the physical 1 extension bit register, to the arithmetic circuit 842.

  4) The arithmetic circuit 842 performs an XOR operation on “1” that is the output value of the mask identification circuit 841 and “1” that is the value received from the write selector 840. The result is “0”, and the arithmetic circuit 842 transmits the arithmetic result to the pointer synthesis unit 9 and the update determination circuit 843 via the path 80. The calculation result is transmitted to the pointer synthesis unit 9 as WEX.

  5) The update determination circuit 843 receives the write physical vector register number “0” via the path 70. In addition, the update determination circuit 843 receives the calculation result of the calculation circuit 842 through the path 80. Since the write physical vector register number is “0”, the update determination circuit 843 transmits the calculation result and the update instruction to the path 844.

  6) The physical 0 extension bit register 82 writes the operation result received from the update determination circuit 843 via the path 844 in the entry corresponding to WP.

  7) The pointer combining unit 9 generates a write extension pointer from the WEX received via the path 80 and the WP received via the path 40 by the WP combining circuit 92. Since WEX is “0” and WP is “00”, the write extension pointer is binary “000”. The write extension pointer “000” indicates e0 of the vector register 1 according to the correspondence table of FIG.

  As described above, entry 0 of logical vector register 0 is associated with e0 of vector register 1 and fe0 of physical vector register 0. Execution of the instruction 0 writes the vector data element to the entry e0 of the vector register 1 designated by the write extension pointer “000”. That is, the element of the vector data written in e0 of the vector register 1 is written in the entry 0 of the logical vector register 0 by the program. Physically, an element of vector data is written in entry fe0 of physical vector register 0 corresponding to entry e0.

  At this time, when valid write data for the vector register 1 exists in the WD register 2, the WE register 10 becomes "1". The WE control unit 11 determines that WE is “1” from the value of the WE register 10 and the mask information received via the path 60, and outputs the result to the vector register 1 as WE. The vector register 1 writes the data of the WD register 2 to the entry specified by the write extension pointer.

  From entry 1 onward of physical vector register 0, WP is incremented by 1 (incremented), and the number of entries of physical vector register 0 is repeated from 1) above. When the WP changes from “00” to “11”, the entries of the vector register 1 associated with the physical vector register No. 0 are e0, e1, e2, and e3, respectively. In FIG. 7C, they are expressed as fe0 (e0), fe1 (e1), fe2 (e2), and fe3 (e4). The four entries of the logical vector register 0 are associated with e0, e1, e2, and e3 of the vector register 1, respectively.

  At this time, a case where reading of data from the physical vector register 0 is requested will be described.

  1) From the physical 0 extension bit register 82 and the physical 1 extension bit register 83, the corresponding 1-bit value (indicated by “00” in binary) corresponding to the entry 0 (fe0) of the physical vector register 0 Here, “0” and “1”) are respectively read by the extension bit register control unit 86. The read values are transmitted to the read selector 85 via the path 821 and the path 831, respectively.

  2) The read selector 85 receives the read physical vector register number via the path 71. Since the read physical vector register number is “0”, the path 821 is selected, and the value of the physical 0 extension bit register 82 (here “0”) is transmitted to the pointer synthesis unit 9 as REX.

  3) The pointer synthesis unit 9 generates a read extension pointer from the REX received via the path 81 and the RP received via the path 50. At this time, since the value of REX is “0” and the value of RP is “00”, the read extension pointer is “000”. The read extension pointer “000” points to the entry e0 of the vector register 1. Therefore, the logical vector register 0 entry 0 is associated with e0 of the vector register 1 and fe0 of the physical vector register 0.

  4) Data is read from entry 0 of logical vector register 0, that is, e0 of vector register 1 (fe0 of physical vector register 0).

  For entry 1 and later, RP is incremented by 1 and the number of entries is repeated from 1).

  FIG. 7C shows a state after the instruction 0 is executed.

  In the physical 0 extension bit register 82, the values of all bits are “0”, and in the physical 1 extension bit register 83, the values of all bits are “1”. A, B, C, and D are stored in e0 to e3 of the vector register 1 (that is, entries 0 to 3 of the logical vector register 0), respectively. At this time, the four entries fe0 to fe3 of the physical vector register 0 correspond to the e0 to e3 of the vector register 1 (that is, the entries 0 to 3 of the logical vector register 0), and their contents are A, B, C, D.

  After execution of the instruction 0, the physical vector register 0 holds the register state after register renaming, and the physical vector register 1 holds the register state before register renaming. Therefore, register renaming by two physical vector registers is correctly performed for one logical vector register number.

  Next, a case where instruction 1 is executed will be described.

  It is assumed that the logical vector register 0 of the instruction 1 is designated as the physical vector register 1 by register renaming in the register management unit 7. Since the instruction 1 is a normal instruction, the output of the mask identification circuit 841 is “1”.

  FIG. 7D shows a state immediately before the vector data is written. Since it is a normal instruction, the outputs of the mask identification circuit 841 corresponding to each entry are all “1”. Since the write physical vector register number is “1”, the value of the physical 0 extension bit register 82 is selected by the write selector 840. Therefore, the arithmetic circuit 842 performs an XOR operation on the output of the mask identification circuit 841 and the value of the physical 0 extension bit register 82 corresponding to the entry to which data is written. The calculation result is written to the corresponding entry of the physical 1 extension bit register 83 via the path 845 by the update determination circuit 843.

  The association between each entry in the physical vector register 1 and each entry in the logical vector register 0 is performed as follows.

  1) The corresponding 1-bit value (from the physical 0 extended bit register 82 and the physical 1 extended bit register 83) by the WP (in binary “00”) corresponding to the entry 0 (fe0) of the physical vector register 1 Here, “0” and “1”) are respectively read by the extension bit register control unit 86. The read values are transmitted to the update unit 84 via the path 820 and the path 830, respectively.

  2) The mask identification circuit 841 receives the contents and mask information of the mask register corresponding to the WP from the mask unit 6 via the path 60. Since the instruction 1 is a normal instruction, the mask identification circuit 841 outputs a 1-bit value “1” to the arithmetic circuit 842 based on the mask information.

  3) The write selector 840 receives the write physical vector register number “1” via the path 70. Therefore, the write selector 840 selects the path 820 and transmits “0”, which is the value of the physical 0 extension bit register, to the arithmetic circuit 842.

  4) The arithmetic circuit 842 performs an XOR operation on “1” that is the output value of the mask identification circuit 841 and “0” that is the value received from the write selector 840. The result is “1”, and the arithmetic circuit 842 transmits the arithmetic result to the pointer synthesis unit 9 and the update determination circuit 843 via the path 80. The calculation result is transmitted to the pointer synthesis unit 9 as WEX.

  5) The update determination circuit 843 receives the write physical vector register number “1” via the path 70. In addition, the update determination circuit 843 receives the calculation result of the calculation circuit 842 through the path 80. Since the write physical vector register number is “1”, the update determination circuit 843 transmits the calculation result and the update instruction to the path 845.

  6) The physical 1 extension bit register 83 writes the operation result received from the update determination circuit 843 via the path 845 in the entry corresponding to WP.

  7) The pointer combining unit 9 generates a write extension pointer from the WEX received via the path 80 and the WP received via the path 40 by the WP combining circuit 92. Since WEX is “1” and WP is “00”, the write extension pointer is binary “100”. The write extension pointer “100” points to e4 of the vector register 1 according to the correspondence table of FIG.

  As described above, the logical vector register 0 entry 0 is associated with e4 of the vector register 1 and fe0 of the physical vector register 1. By the instruction 1, the element of the vector data is written to the entry e4 of the vector register 1 designated by the write extension pointer “100”. That is, the element of the vector data written in e4 of the vector register 1 is written in the entry 0 of the logical vector register 0 by the program. Physically, vector data elements are written in entry fe0 of physical vector register 0 corresponding to entry e4.

  At this time, when valid write data for the vector register 1 exists in the WD register 2, the WE register 10 becomes "1". The WE control unit 11 determines that WE is “1” from the value of the WE register 10 and the mask information received via the path 60, and outputs the result to the vector register 1 as WE. The vector register 1 writes the data of the WD register 2 to the entry specified by the write extension pointer.

  From entry 1 onward for physical vector register 1, WP is incremented by +1 (increment), and the number of entries in physical vector register 1 is repeated from 1) above. When the WP changes from “00” to “11”, the entries of the vector register 1 associated with the physical vector register 1 are e4, e5, e6, and e7, respectively. In FIG. 7 (e), they are expressed as fe0 (e4), fe1 (e5), fe2 (e6), and fe3 (e7). The four entries of the logical vector register 0 are associated with e4, e5, e6, and e7 of the vector register 1, respectively.

  At this time, a case where reading of data from the physical vector register 1 is requested will be described.

  1) From the physical 0 extension bit register 82 and the physical 1 extension bit register 83, the corresponding 1-bit value ((00) in binary) corresponding to the entry 0 (fe0) of the physical vector register 1 Here, “0” and “1”) are respectively read by the extension bit register control unit 86. The read values are transmitted to the read selector 85 via the path 821 and the path 831, respectively.

  2) The read selector 85 receives the read physical vector register number via the path 71. Since the read physical vector register number is “1”, the path 831 is selected, and the value of the physical 1 extension bit register 83 (here, “1”) is transmitted to the pointer synthesis unit 9 as REX.

  3) The pointer synthesis unit 9 generates a read extension pointer from the REX received via the path 81 and the RP received via the path 50. At this time, since the value of REX is “1” and the value of RP is “00”, the read extension pointer is “000”. The read extension pointer “100” points to the entry e4 of the vector register 1. Therefore, entry 0 of logical vector register 0 is associated with e4 of vector register 1 and fe0 of physical vector register 1.

  4) Data is read from entry 0 of the logical vector register, that is, e4 of vector register 1 (fe0 of physical vector register 1).

  For entry 1 and later, RP is incremented by 1 and the number of entries is repeated from 1).

  FIG. 7E shows a state after the execution of the instruction 1.

  In the physical 0 extension bit register 82, the values of all bits are “0”, and in the physical 1 extension bit register 83, the values of all bits are “1”. E4 to e7 of the vector register 1 (that is, entries 0 to 3 of the logical vector register 0) store E, F, G, and H, respectively. At this time, the four entries fe0 to fe3 of the physical vector register 1 correspond to the e4 to e7 of the vector register 1 (that is, the entries 0 to 3 of the logical vector register 0), and their contents are E, F, G, H.

  After execution of the instruction 1, the physical vector register 0 holds the register state before register renaming, and the physical vector register 1 holds the register state after register renaming. Therefore, register renaming by two physical vector registers is correctly performed for one logical vector register number.

  Next, a case where instruction 2 is executed will be described.

  It is assumed that the logical vector register 0 of the instruction 2 is designated as the physical vector register 0 by register renaming in the register management unit 7. Since the instruction 2 is a normal instruction, the output of the mask identification circuit 841 is “1”.

  FIG. 7F shows a state immediately before the vector data is written.

  The association between each entry of the physical vector register 0 and each entry of the logical vector register 0 is the same as that of the instruction 0.

  At this time, the operation when the physical vector register No. 0 is read is the same as when the instruction 0 reads the physical vector register No. 0.

  FIG. 7G shows a state after the execution of the instruction 2.

  In the physical 0 extension bit register 82, the values of all bits are “0”, and in the physical 1 extension bit register 83, the values of all bits are “1”. E0 to e7 of the vector register 1 store I, J, K, L, E, F, G, and H, respectively. At this time, the four entries fe0 to fe3 of the physical vector register No. 0 correspond to the e0 to e3 of the vector register 1 (that is, the entries 0 to 3 of the logical vector register No. 0). J, K, L.

  After execution of the instruction 2, the physical vector register No. 0 holds the register state after register renaming, and the physical vector register No. 1 holds the register state before register renaming. Therefore, register renaming by two physical vector registers is correctly performed for one logical vector register number.

  Next, the case of executing an instruction for performing an operation with a mask will be described with reference to FIG.

  FIGS. 8A to 8E show that instruction 0 to be written to logical vector register 0 and masked instructions to be written to logical vector register 0 are 2 instructions (hereinafter referred to as instruction M1 and instruction M2, respectively). A case where an instruction is executed will be described.

  The case where the instruction 0 is executed from the initial state is the same as the instruction 0 described in FIG. FIG. 8A shows the state of each register after execution of the instruction 0, which is the same as FIG. 7C.

  Next, the case where the instruction M1 for performing the masked operation is executed will be described.

  As for the logical vector register 0 of the instruction M1, it is assumed that the physical vector register 1 is designated by register renaming in the register management unit 7. The value of the mask register of the instruction M1 is 1001 (binary number) corresponding to the entries of the logical vector register 0 and the physical vector register 1 respectively.

  FIG. 8B shows a state immediately before the vector data is written.

  The entry 0 of the logical vector register 0 corresponding to the entry 0 (fe0) of the physical vector register 1 is determined as follows.

  1-0) From the physical 0 extended bit register 82 and the physical 1 extended bit register 83, the corresponding 1 bit of WP (binary number “00”) corresponding to the entry 0 (fe0) of the physical vector register 1 Values (here, “0” and “1”, respectively) are read by the extension bit register control unit 86. The read values are transmitted to the update unit 84 via the path 820 and the path 830, respectively.

  2-0) The mask identification circuit 841 receives the contents of the mask register and the mask information corresponding to the WP from the mask unit 6 via the path 60. Since the instruction M1 is an instruction with a mask, the mask identification circuit 841 outputs the 1-bit value “1” of the corresponding mask register to the arithmetic circuit 842 based on the mask information.

  3-0) The write selector 840 receives the write physical vector register number “1” via the path 70. Therefore, the write selector 840 selects the path 820 and transmits “0” that is the value of the physical 0 extension bit register to the arithmetic circuit 842.

  4-0) The arithmetic circuit 842 performs an XOR operation on “1” that is the output value of the mask identification circuit 841 and “0” that is the value received from the write selector 840. The result is “1”, and the arithmetic circuit 842 transmits the arithmetic result to the pointer synthesis unit 9 and the update determination circuit 843 via the path 80. The calculation result is transmitted to the pointer synthesis unit 9 as WEX.

  5-0) The update determination circuit 843 receives the write physical vector register number “1” via the path 70. In addition, the update determination circuit 843 receives the calculation result of the calculation circuit 842 through the path 80. Since the write physical vector register number is “1”, the update determination circuit 843 transmits the calculation result and the update instruction to the path 845.

  6-0) The physical 1 extension bit register 83 writes the operation result received from the update determination circuit 843 via the path 845 in its own entry corresponding to WP.

  7-0) The pointer synthesis unit 9 generates a write extension pointer from the WEX received via the path 80 and the WP received via the path 40 by the WP synthesis circuit 92. Since WEX is “1” and WP is “00”, the write extension pointer is binary “100”. The write extension pointer “100” points to e4 of the vector register 1 according to the correspondence table of FIG. Therefore, entry 0 of logical vector register 0 is associated with e4 of vector register 1 and fe0 of physical vector register 1.

  The entry 1 of the logical vector register 0 corresponding to the entry 1 of the physical vector register 1 is determined as follows.

  1-1) From the physical 0 extended bit register 82 and the physical 1 extended bit register 83, the corresponding 1 bit of WP corresponding to the entry 1 (fe1) of the physical vector register 1 is output from the physical 0 extended bit register 82 and the physical 1 extended bit register 83. Values (here, “0” and “1”, respectively) are read by the extension bit register control unit 86. The read values are transmitted to the update unit 84 via the path 820 and the path 830, respectively.

  2-1) The mask identification circuit 841 receives the contents and mask information of the mask register corresponding to the WP from the mask unit 6 via the path 60. Since the instruction M1 is an instruction with a mask, the mask identification circuit 841 outputs the 1-bit value “0” of the corresponding mask register to the arithmetic circuit 842 based on the mask information.

  3-1) The write selector 840 receives the write physical vector register number “1” via the path 70. Therefore, the write selector 840 selects the path 820 and transmits “0”, which is the value of the physical 0 extension bit register, to the arithmetic circuit 842.

  4-1) The arithmetic circuit 842 performs an XOR operation on “0” that is the output value of the mask identification circuit 841 and “0” that is the value received from the write selector 840. The result is “0”, and the arithmetic circuit 842 transmits the arithmetic result to the pointer synthesis unit 9 and the update determination circuit 843 via the path 80. The calculation result is transmitted to the pointer synthesis unit 9 as WEX.

  5-1) The update determination circuit 843 receives the write physical vector register number “1” via the path 70. In addition, the update determination circuit 843 receives the calculation result of the calculation circuit 842 through the path 80. Since the write physical vector register number is “1”, the update determination circuit 843 transmits the calculation result and the update instruction to the path 845.

  6-1) The physical 1 extension bit register 83 writes the operation result received from the update determination circuit 843 via the path 845 in its own entry corresponding to WP.

  7-1) The pointer synthesis unit 9 generates a write extension pointer from the WEX received via the path 80 and the WP received via the path 40 by the WP synthesis circuit 92. Since WEX is “0” and WP is “01”, the write extension pointer is binary “001”. The write extension pointer “001” points to e1 of the vector register 1 according to the correspondence table of FIG. Therefore, entry 1 of logical vector register 0 is associated with e1 of vector register 1 and fe1 of physical vector register 1. However, since the mask bit is “0”, writing to the entry e1 of the vector register 1 (that is, the entry 1 of the logical vector register 0) is not executed.

  The entry 2 of the logical vector register 0 corresponding to the entry 2 of the physical vector register 1 is determined as follows.

  1-2) From the physical 0 extended bit register 82 and the physical 1 extended bit register 83, the corresponding 1 bit of WP corresponding to the entry 2 (fe2) of the physical vector register 1 is output from the physical 0 extended bit register 82 and the physical 1 extended bit register 83. Values (here, “0” and “1”, respectively) are read by the extension bit register control unit 86. The read values are transmitted to the update unit 84 via the path 820 and the path 830, respectively.

  2-2) The mask identification circuit 841 receives the contents of the mask register and the mask information corresponding to the WP from the mask unit 6 via the path 60. Since the instruction M1 is an instruction with a mask, the mask identification circuit 841 outputs the 1-bit value “0” of the corresponding mask register to the arithmetic circuit 842 based on the mask information.

  3-2) The write selector 840 receives the write physical vector register number “1” via the path 70. Therefore, the write selector 840 selects the path 820 and transmits “0”, which is the value of the physical 0 extension bit register, to the arithmetic circuit 842.

  4-2) The arithmetic circuit 842 performs an XOR operation between “0” that is the output value of the mask identification circuit 841 and “0” that is the value received from the write selector 840. The result is “0”, and the arithmetic circuit 842 transmits the arithmetic result to the pointer synthesis unit 9 and the update determination circuit 843 via the path 80. The calculation result is transmitted to the pointer synthesis unit 9 as WEX.

  5-2) The update determination circuit 843 receives the write physical vector register number “1” via the path 70. In addition, the update determination circuit 843 receives the calculation result of the calculation circuit 842 through the path 80. Since the write physical vector register number is “1”, the update determination circuit 843 transmits the calculation result and the update instruction to the path 845.

  6-2) The physical 1 extension bit register 83 writes the operation result received from the update determination circuit 843 via the path 845 in its own entry corresponding to the WP.

  7-2) The pointer synthesis unit 9 generates a write extension pointer from the WEX received via the path 80 and the WP received via the path 40 by the WP synthesis circuit 92. Since WEX is “0” and WP is “10”, the write extension pointer is binary “010”. The write extension pointer “010” points to e2 of the vector register 1 according to the correspondence table of FIG. Therefore, entry 2 of logical vector register 0 is associated with e2 of vector register 1 and fe2 of physical vector register 1. However, since the mask bit is “0”, writing to the entry e2 of the vector register 1 (that is, the entry 2 of the logical vector register 0) is not executed.

  The entry 3 of the logical vector register 0 corresponding to the entry 3 of the physical vector register 1 is determined as follows.

  1-3) From the physical 0 extension bit register 82 and the physical 1 extension bit register 83, the corresponding 1 bit of WP corresponding to the entry 3 (fe3) of the physical vector register 1 is output from the physical 0 extension bit register 82 and the physical 1 extension bit register 83. Values (here, “0” and “1”, respectively) are read by the extension bit register control unit 86. The read values are transmitted to the update unit 84 via the path 820 and the path 830, respectively.

  2-3) The mask identification circuit 841 receives the contents and mask information of the mask register corresponding to WP from the mask unit 6 via the path 60. Since the instruction M1 is an instruction with a mask, the mask identification circuit 841 outputs the 1-bit value “1” of the corresponding mask register to the arithmetic circuit 842 based on the mask information.

  3-3) The write selector 840 receives the write physical vector register number “1” via the path 70. Therefore, the write selector 840 selects the path 820 and transmits “0”, which is the value of the physical 0 extension bit register, to the arithmetic circuit 842.

  4-3) The arithmetic circuit 842 performs an XOR operation between “1” that is the output value of the mask identification circuit 841 and “0” that is the value received from the write selector 840. The result is “1”, and the arithmetic circuit 842 transmits the arithmetic result to the pointer synthesis unit 9 and the update determination circuit 843 via the path 80. The calculation result is transmitted to the pointer synthesis unit 9 as WEX.

  5-3) The update determination circuit 843 receives the write physical vector register number “1” via the path 70. In addition, the update determination circuit 843 receives the calculation result of the calculation circuit 842 through the path 80. Since the write physical vector register number is “1”, the update determination circuit 843 transmits the calculation result and the update instruction to the path 845.

  6-3) The physical 1 extension bit register 83 writes the operation result received from the update determination circuit 843 via the path 845 in its own entry corresponding to the WP.

  7-3) The pointer synthesis unit 9 generates a write extension pointer from the WEX received via the path 80 and the WP received via the path 40 by the WP synthesis circuit 92. Since WEX is “1” and WP is “11”, the write extension pointer is binary “111”. The write extension pointer “111” points to e7 of the vector register 1 according to the correspondence table of FIG. Therefore, entry 3 of logical vector register 0 is associated with e7 of vector register 1 and fe3 of physical vector register 1.

  From the above, the entry of the vector register 1 written as the physical vector register 1 (that is, the entry of the logical vector register 0) is e4, no write (e1), no write (e2), and e7, respectively.

  FIG. 8C shows a state after the execution of the instruction M1.

  All the values of the physical 0 extension bit register 82 are “0”, and the values of the physical 1 extension bit register 83 are 1, 0, 0, 1 respectively. E0 to e7 of the vector register 1 store A, B, C, D, E,-,-, H (hyphen (-) is an initial value), respectively. At this time, the four entries of the physical vector register 0 correspond to e0 to e3 of the vector register 1, and the contents thereof are A, B, C, and D, respectively. The four entries of the physical vector register 1 correspond to e4, e1, e2, and e7 of the vector register 1, and their contents are E, B, C, and H, respectively.

  By executing the instruction M1, the values of the four entries of the logical vector register 0 are updated from the contents of A, B, C, and D, and only the entry whose mask register value is “1” is updated. , B, C, H.

  After execution of the instruction M1, the physical vector register 0 holds the register state before register renaming, and the physical vector register 1 holds the register state after register renaming. Therefore, register renaming by two physical vector registers is correctly performed for one logical vector register number.

  Here, FIG. 8C ′ shows a state after register renaming is executed when the instruction M1 is executed according to the conventional technique. The four entries of the physical vector register 1 correspond to e4 to e7 of the vector register 1, and their contents are E,-,-, and H, respectively. That is, since the physical vector register number “1” and each of the WP are combined, the above association is made. As a result, the values of the four entries in the logical vector register 1 are updated only for the entries whose mask register value is “1” based on the contents of A, B, C, and D before register renaming. Thus, the expected values of E, B, C, and H are not met. Therefore, the result is garbled data.

  Next, a case where the instruction M2 is executed will be described.

  As for the logical vector register 0 of the instruction M2, the physical vector register 0 is designated by the register renaming in the register management unit 7. The value of the mask register of the instruction M2 is 1100 (binary number) corresponding to each entry of the logical vector register 0 or the physical vector register 1.

  FIG. 8D shows a state immediately before writing vector data.

  The entry 0 of the logical vector register 0 corresponding to the entry 0 (fe0) of the physical vector register 0 is determined as follows.

  1-0) From the physical 0 extended bit register 82 and the physical 1 extended bit register 83, the corresponding 1 bit of WP (binary number “00”) corresponding to the entry 0 (fe0) of the physical vector register 0 Values (here, “0” and “1”, respectively) are read by the extension bit register control unit 86. The read values are transmitted to the update unit 84 via the path 820 and the path 830, respectively.

  2-0) The mask identification circuit 841 receives the contents of the mask register and the mask information corresponding to the WP from the mask unit 6 via the path 60. Since the instruction M2 is a masked instruction, the mask identification circuit 841 outputs the 1-bit value “1” of the corresponding mask register to the arithmetic circuit 842 based on the mask information.

  3-0) The write selector 840 receives the write physical vector register number “0” via the path 70. Therefore, the write selector 840 selects the path 830 and transmits “1” that is the value of the physical 1 extension bit register 83 to the arithmetic circuit 842.

  4-0) The arithmetic circuit 842 performs an XOR operation on “1” that is the output value of the mask identification circuit 841 and “1” that is the value received from the write selector 840. The result is “0”, and the arithmetic circuit 842 transmits the arithmetic result to the pointer synthesis unit 9 and the update determination circuit 843 via the path 80. The calculation result is transmitted to the pointer synthesis unit 9 as WEX.

  5-0) The update determination circuit 843 receives the write physical vector register number “0” via the path 70. In addition, the update determination circuit 843 receives the calculation result of the calculation circuit 842 through the path 80. Since the write physical vector register number is “0”, the update determination circuit 843 transmits the calculation result and the update instruction to the path 844.

  6-0) The physical 0 extension bit register 82 writes the operation result received from the update determination circuit 843 via the path 844 in its own entry corresponding to WP.

  7-0) The pointer synthesis unit 9 generates a write extension pointer from the WEX received via the path 80 and the WP received via the path 40 by the WP synthesis circuit 92. Since WEX is “0” and WP is “00”, the write extension pointer is binary “000”. The write extension pointer “000” indicates e0 of the vector register 1 according to the correspondence table of FIG. Therefore, entry 0 of logical vector register 0 is associated with e0 of vector register 1 and fe0 of physical vector register 0.

  The entry 1 of the logical vector register 0 corresponding to the entry 1 of the physical vector register 0 is determined as follows.

  1-1) From the physical 0 extended bit register 82 and the physical 1 extended bit register 83, the corresponding 1 bit of WP corresponding to the entry 1 (fe1) of the physical vector register 1 is output from the physical 0 extended bit register 82 and the physical 1 extended bit register 83. Values (here, “0” and “0”, respectively) are read by the extension bit register control unit 86. The read values are transmitted to the update unit 84 via the path 820 and the path 830, respectively.

  2-1) The mask identification circuit 841 receives the contents and mask information of the mask register corresponding to the WP from the mask unit 6 via the path 60. Since the instruction M2 is a masked instruction, the mask identification circuit 841 outputs the 1-bit value “1” of the corresponding mask register to the arithmetic circuit 842 based on the mask information.

  3-1) The write selector 840 receives the write physical vector register number “0” via the path 70. Therefore, the write selector 840 selects the path 830 and transmits “0” that is the value of the physical 1 extension bit register 83 to the arithmetic circuit 842.

  4-1) The arithmetic circuit 842 performs an XOR operation between “1” that is the output value of the mask identification circuit 841 and “0” that is the value received from the write selector 840. The result is “1”, and the arithmetic circuit 842 transmits the arithmetic result to the pointer synthesis unit 9 and the update determination circuit 843 via the path 80. The calculation result is transmitted to the pointer synthesis unit 9 as WEX.

  5-1) The update determination circuit 843 receives the write physical vector register number “0” via the path 70. In addition, the update determination circuit 843 receives the calculation result of the calculation circuit 842 through the path 80. Since the write physical vector register number is “0”, the update determination circuit 843 transmits the calculation result and the update instruction to the path 844.

  6-1) The physical 0 extension bit register 82 writes the operation result received from the update determination circuit 843 via the path 844 in its own entry corresponding to WP.

  7-1) The pointer synthesis unit 9 generates a write extension pointer from the WEX received via the path 80 and the WP received via the path 40 by the WP synthesis circuit 92. Since WEX is “1” and WP is “01”, the write extension pointer is binary “101”. The write extension pointer “101” points to e5 of the vector register 1 according to the correspondence table of FIG. Therefore, entry 1 of logical vector register 0 is associated with e5 of vector register 1 and fe1 of physical vector register 0.

  The entry 2 of the logical vector register 0 corresponding to the entry 2 of the physical vector register 0 is determined as follows.

  1-2) From the physical 0 extended bit register 82 and the physical 1 extended bit register 83, the corresponding 1 bit of the physical vector register 0 corresponding to entry 2 (fe2) of the physical vector register 0 is obtained. Values (here, “0” and “0”, respectively) are read by the extension bit register control unit 86. The read values are transmitted to the update unit 84 via the path 820 and the path 830, respectively.

  2-2) The mask identification circuit 841 receives the contents of the mask register and the mask information corresponding to the WP from the mask unit 6 via the path 60. Since the instruction M2 is an instruction with a mask, the mask identification circuit 841 outputs the 1-bit value “0” of the corresponding mask register to the arithmetic circuit 842 based on the mask information.

  3-2) The write selector 840 receives the write physical vector register number “0” via the path 70. Therefore, the write selector 840 selects the path 830 and transmits “0” that is the value of the physical 1 extension bit register 83 to the arithmetic circuit 842.

  4-2) The arithmetic circuit 842 performs an XOR operation between “0” that is the output value of the mask identification circuit 841 and “0” that is the value received from the write selector 840. The result is “0”, and the arithmetic circuit 842 transmits the arithmetic result to the pointer synthesis unit 9 and the update determination circuit 843 via the path 80. The calculation result is transmitted to the pointer synthesis unit 9 as WEX.

  5-2) The update determination circuit 843 receives the write physical vector register number “0” via the path 70. In addition, the update determination circuit 843 receives the calculation result of the calculation circuit 842 through the path 80. Since the write physical vector register number is “0”, the update determination circuit 843 transmits the calculation result and the update instruction to the path 844.

  6-2) The physical 0 extension bit register 82 writes the operation result received from the update determination circuit 843 via the path 844 in its own entry corresponding to WP.

  7-2) The pointer synthesis unit 9 generates a write extension pointer from the WEX received via the path 80 and the WP received via the path 40 by the WP synthesis circuit 92. Since WEX is “0” and WP is “10”, the write extension pointer is binary “010”. The write extension pointer “010” points to e2 of the vector register 1 according to the correspondence table of FIG. Therefore, entry 2 of logical vector register 0 is associated with e2 of vector register 1 and fe2 of physical vector register 0. However, since the mask bit is “0”, writing to the entry e2 of the vector register 1 (that is, the entry 2 of the logical vector register 0) is not executed.

  The entry 3 of the logical vector register 0 corresponding to the entry 3 of the physical vector register 0 is determined as follows.

  1-3) From the physical 0 extended bit register 82 and the physical 1 extended bit register 83, the corresponding 1 bit of WP corresponding to the entry 3 (fe3) of the physical vector register 0 is output from the physical 0 extended bit register 82 and the physical 1 extended bit register 83. Values (here, “0” and “1”, respectively) are read by the extension bit register control unit 86. The read values are transmitted to the update unit 84 via the path 820 and the path 830, respectively.

  2-3) The mask identification circuit 841 receives the contents and mask information of the mask register corresponding to WP from the mask unit 6 via the path 60. Since the instruction M2 is an instruction with a mask, the mask identification circuit 841 outputs the 1-bit value “0” of the corresponding mask register to the arithmetic circuit 842 based on the mask information.

  3-3) The write selector 840 receives the write physical vector register number “0” via the path 70. Therefore, the write selector 840 selects the path 830 and transmits “1” that is the value of the physical 1 extension bit register 83 to the arithmetic circuit 842.

  4-3) The arithmetic circuit 842 performs an XOR operation on “0” that is the output value of the mask identification circuit 841 and “1” that is the value received from the write selector 840. The result is “1”, and the arithmetic circuit 842 transmits the arithmetic result to the pointer synthesis unit 9 and the update determination circuit 843 via the path 80. The calculation result is transmitted to the pointer synthesis unit 9 as WEX.

  5-3) The update determination circuit 843 receives the write physical vector register number “0” via the path 70. In addition, the update determination circuit 843 receives the calculation result of the calculation circuit 842 through the path 80. Since the write physical vector register number is “0”, the update determination circuit 843 transmits the calculation result and the update instruction to the path 844.

  6-3) The physical 0 extension bit register 82 writes the operation result received from the update determination circuit 843 via the path 844 in its own entry corresponding to WP.

  7-3) The pointer synthesis unit 9 generates a write extension pointer from the WEX received via the path 80 and the WP received via the path 40 by the WP synthesis circuit 92. Since WEX is “1” and WP is “11”, the write extension pointer is binary “111”. The write extension pointer “111” points to e7 of the vector register 1 according to the correspondence table of FIG. Thus, entry 3 of logical vector register 0 is associated with e7 of vector register 1 and fe3 of physical vector register 0.

  As described above, the entry of the vector register 1 written as the physical vector register No. 0 (that is, the entry of the logical vector register No. 0) is e0, e5, no write (e2), and no write (e7), respectively.

  FIG. 8E shows a state after execution of the instruction M2.

  The values of the physical 0 extension bit register 82 are 0, 1, 0, 1, respectively, and the values of the physical 1 extension bit register 83 are 1, 0, 0, 1, respectively. E0 to e7 of the vector register 1 store I, B, C, D, E, J,-, H (hyphen (-) is an initial value), respectively. At this time, the four entries of the physical vector register No. 0 correspond to e0, e5, e2, and e7 of the vector register 1, and their contents are I, J, C, and H, respectively. The four entries of the physical vector register 1 correspond to e4, e1, e2, and e7 of the vector register 1, and their contents are E, B, C, and H, respectively.

  By executing the instruction M2, the values of the four entries of the logical vector register 0 are updated from the contents of E, B, C, and H, only the entry whose mask register value is “1”. , J, C, H.

  After execution of the instruction M2, the physical vector register No. 0 holds the register state after register renaming, and the physical vector register No. 1 holds the register state before register renaming. Therefore, register renaming by two physical vector registers is correctly performed for one logical vector register number.

  Here, FIG. 8 (e ′) shows a state after register renaming in the case where the instruction M2 is executed from the state shown in FIG. 8 (c ′) by the conventional technique. The four entries of physical vector register 0 correspond to e0 to e3 of vector register 1 (that is, e0 to e3 of logical vector register 0), and their contents are I, J, C, and D, respectively. Yes. That is, since the physical vector register number “0” and the WP are combined, the above association is made. As a result, the values of the four entries of the logical vector register 1 shown in FIG. 8 (e ′) do not match the expected values of I, J, C, and H shown in FIG. 8 (e). Therefore, the result is garbled data.

  As described above, since association can be performed by register renaming for each entry between the logical vector register and the physical vector register, it is possible to avoid data corruption due to register renaming even if a masked operation is performed. A special effect is obtained.

  Next, the operation of the first embodiment of the present invention will be described with reference to the flowchart of FIG.

  The register management unit 7 executes register renaming between the logical vector register and the physical vector register (S1).

  The extension bit unit 8 receives WP from the WP register 4 (S2). At this time, among the entries of the physical vector register designated by the register management unit 7 at the time of register renaming, the WP corresponding to the entry to which data is to be written is received one by one.

  The update unit 84 receives the extension bits corresponding to the WP from the physical 0 extension bit register 82 and the physical 1 extension bit register 83 (S3).

  The write selector 840 selects an extension bit based on the write physical vector register number (S4). Here, the write selector 840 selects the extension bit read from the physical 1 extension bit register 83 when the write physical vector register number is “0”. When the write physical vector register number is “1”, the extension bit read from the physical 0 extension bit register 82 is selected.

  The mask identification circuit 841 receives a mask bit corresponding to an entry to which data is to be written among the entries of the physical vector register designated by the register management unit 7 during register renaming from the mask unit 6 (S4).

  The arithmetic circuit 842 executes arithmetic processing using the mask bit value and the extension bit value selected by the write selector 840 (S6). The arithmetic circuit 842 performs an XOR operation and transmits the operation result to the pointer synthesis unit 9 as WEX.

  The pointer synthesizer 9 synthesizes the calculation result of the calculation circuit 842 and the WP received from the WP register 4 to generate a write extension pointer (S7).

  The entry of the vector register 1 corresponding to the write extension pointer is associated with the entry of the physical vector register corresponding to WP (S8). Thereby, the entry of the logical vector register is associated with the entry of the vector register 1 and the entry of the physical vector register.

  Vector data elements are written in the entry designated by the write extension pointer (S9).

  When there is a vector data read request (Yes in S10), the read selector 85 receives the extension bit corresponding to RP from the extension bit register corresponding to the physical vector register designated by the register renaming (S11). ). The read selector 85 transmits the received extension bit to the pointer synthesis unit 9.

  The pointer synthesis unit 9 synthesizes the received extension bit and RP to generate a read extension pointer (S12).

  Among the entries in the vector register 1, the element of the vector data is read from the entry specified by the read extension pointer (S13).

(Second Embodiment)
Next, a second embodiment of the present invention will be described.

  In the first embodiment, the case where the number of entries in the vector register 1 is 8 and the number of physical vector registers in which the number of entries is 4 is two has been mainly described. However, the present invention is not limited to this. Under the predetermined conditions shown in FIG. 10, the number of vector register entries, the number of physical vector register entries, and the number of physical vector registers may be any number.

  The predetermined condition will be described with reference to FIG. Let the number of entries in the physical vector register be a number represented by 2 to the power of x. In this case, the number of bits of WP or RP is an x-bit value. This is because WP or RP has a one-to-one correspondence with each entry in the physical vector register. If the number of entries in the vector register 1 is a number expressed by 2 to the power of m, the write extension pointer or the read extension pointer has an m-bit value. The write extension pointer or read extension pointer is a value obtained by combining WP or RP and WEX or REX. Therefore, WEX or REX has a value of (mx) bits.

  Under this condition, the number of entries in the Kuttle register, the number of entries in the physical vector register, and the number of physical vector registers can be determined arbitrarily.

  Next, the structure of the 2nd Embodiment of this invention is demonstrated using FIG.11, FIG.12, FIG.13 and FIG. In FIG. 11, FIG. 12, FIG. 13, and FIG. 14, the components having the same numbers as those described in the first embodiment are the same as those in the first embodiment.

  Referring to FIG. 11, the information processing apparatus 130 according to the second exemplary embodiment of the present invention includes a register management unit 700 and an extension bit unit 800. Other parts are the same as those in the first embodiment.

  In addition to the functions of the register management unit 7 according to the first embodiment of the present invention, the register management unit 700 manages the correspondence between logical vector registers and physical vector registers in register renaming during instruction execution in more detail. To do. The correspondence relationship is a correspondence relationship between the logical vector register and the physical vector register for each entry. For example, when the number of physical vector registers is n, the register management unit 700 is configured to manage the correspondence between the logical vector registers and the physical vector registers after the instruction execution for the past n times at the maximum according to the instruction execution order. do it. Note that it is not always necessary to manage the correspondence relationship for the past n times, and an optimal design may be made in consideration of hardware resources and the like. The register management unit 700 manages the correspondence relationship based on the physical vector register number of the physical vector register associated with the logical vector register. The register management unit 700 transmits the rename information and the latest state information to the extension bit unit 800 via the path 701. The register management unit 700 transmits the latest state information and rename information every time an instruction is executed. The latest state information and rename information are information generated based on the past correspondence relationship between the logical vector register and the physical vector register managed by the register management unit 700. The latest state information and rename information are represented by physical vector register numbers. Rename information is the number of a physical vector register associated with a logical vector register by register renaming in an instruction being executed. The register management unit 700 selects a physical vector register as a register renaming target from the physical vector registers, and transmits the physical vector register number to the extension bit unit 800 as rename information. The latest state information is the number of a physical vector register that holds data of the latest state of the logical vector register when executing a certain instruction. The contents of the logical vector register are sequentially rewritten by executing the instruction, but the state in which the contents are rewritten last becomes the latest state. If the register management unit 700 refers to the correspondence between the logical vector register and the physical vector register managed in accordance with the execution order of the instructions, the register management unit 700 selects the physical vector register corresponding to the logical vector register holding the latest state. Can be identified. The register management unit 700 selects a physical vector register that holds the latest data of the logical vector register from the physical vector registers, and transmits the physical vector register number to the extension bit unit 800 as the latest state information. . Note that the register management unit 700 stores the latest state of the logical vector register based on the correspondence relationship between the past logical vector register and the physical vector register managed by the register management unit 700 based on the update history of the logical vector register. A vector register may be selected.

  Next, the extension bit unit 800 will be described with reference to FIG.

  The extension bit unit 800 includes an extension bit storage unit 8000, a physical 0 extension bit register 82-0 to a physical n extension bit register 82-n (n is the number of physical vector registers), and an update unit 8400. Other parts are the same as those in the first embodiment.

  The extension bit storage unit 8000 includes as many extension bit registers as the number of physical vector registers. When the number of physical vector registers is n (n is an arbitrary number), the extension bit storage unit 8000 includes physical 0 extension bit registers 82-0 to physical n extension bit registers 82-n. Each of the physical 0 extension bit register 82-0 to physical n extension bit register 82-n has the same number of entries as the number of entries in the physical vector register, and stores an extension bit in each entry. The physical 0 extension bit register 82-0 to physical n extension bit register 82-n are connected to the update unit 8400 via the path 820-0 to path 820-n, respectively. The physical 0 extension bit register 82-0 to physical n extension bit register 82-n are connected to the read selector 85 via the path 821-0 to path 821-n, respectively.

  Next, the update unit 8400 will be described with reference to FIG.

  The update unit 8400 includes a write selector 8401 and an arithmetic circuit 8420. Other parts are the same as those in the first embodiment.

  The write selector 8401 selects one of the paths 820-0 to 820-n, and selects one of the physical 0 extension bit register 82-0 to physical n extension bit register 82-n via the selected path. Receive extension bits. The write selector 8401 receives the latest state information from the register management unit 700 via the path 701. The write selector 8401 selects a path corresponding to the physical vector register number indicated by the latest state information, and receives the extension bit. The write selector 8401 transmits the received extension bit to the arithmetic circuit 8420 via the path 84010. For example, when the latest state information is “2”, the write selector 8401 selects the path 820-2 corresponding to the physical vector register 2 and receives the extension bit. If the latest state information is an initial value (for example, NULL), the path corresponding to the write physical vector register number received via the path 70 is selected. For example, when the write physical vector register number is “0”, the write selector 8401 selects the path 820-0.

  The arithmetic circuit 8420 performs a predetermined calculation based on the mask bit received from the mask identification circuit 841 and the extension bit received from the write selector 8401. Details will be described later.

  The update determination circuit 843 selects a path corresponding to the write physical vector register number received via the path 70 from 844-0 to 844-n. For example, when the write physical vector register number is “1”, the path 844-1 is selected. Other functions are the same as those in the first embodiment.

  Next, the arithmetic circuit 8420 will be described with reference to FIG.

  The arithmetic circuit 8420 includes a mask bit storage unit 8421, an extended bit storage unit 8422, and an arithmetic execution unit 8423.

  The mask bit storage unit 8421 stores the mask bits received from the mask identification circuit 841.

  The extension bit storage unit 8422 stores the extension bits received from the write selector 8401.

  The operation execution unit 8423 executes a predetermined operation based on the value stored in the mask bit storage unit 8421 and the value stored in the extension bit storage unit 8422. When the value stored in the mask bit storage unit 8421 is “1”, the operation execution unit 8423 increments the value stored in the extension bit storage unit 8422. For example, when the value stored in the extension bit storage unit 8422 is “010”, the calculation execution unit 8423 may be configured to increment the value by “1” to “011”. Note that the arithmetic processing by the arithmetic execution unit 8422 is not limited to this, and the increment amount may be other than 1, for example. Further, instead of incrementing the value, the value stored in the extension bit storage unit 8422 may be decremented by a predetermined amount. When the value stored in the mask bit storage unit 8421 is “0”, the calculation execution unit 8423 does not execute the calculation process and transmits the value stored in the extension bit storage unit 8422 to the path 80 as it is. . The calculation execution unit 8423 transmits the calculation result as WEX to the pointer synthesis unit 9 via the path 80. The value of the extension bit is a value of (mx) bits as described above. Therefore, there is an upper limit value and a lower limit value. For example, when the extension bit is a 3-bit value, the upper limit value is “111” and the lower limit value is “000”. The calculation execution unit 8423 sets the calculation result to the lower limit value when the result of the calculation process exceeds the upper limit value. In addition, when the result of the arithmetic processing is below the lower limit value, the arithmetic execution unit 8423 sets the calculation result to the upper limit value.

  When the value stored in the extension bit storage unit 8422 is an initial value (for example, NULL), the calculation execution unit 8423 does not execute the calculation process, and sets the value of the extension bit as either the upper limit value or the lower limit value. Process to set to. However, in this case, any value other than the upper limit value or the lower limit value may be set.

  Next, arithmetic processing by the arithmetic circuit 8420 will be described with reference to the flowchart of FIG.

  The arithmetic circuit 8420 receives the mask bit from the mask identification circuit 841 and stores it in the mask bit storage unit 8421 (S21).

  The arithmetic circuit 8420 stores the extension bit selected by the write selector 8401 in the extension bit storage unit 8422 (S22).

  The operation execution unit 8423 determines whether or not the value of the extension bit in the extension bit storage unit is an initial value (for example, NULL or the like) (S23).

  When the value of the extension bit is an initial value (Yes in S23), the operation execution unit 8423 sets the value of the extension bit (S24). The operation execution unit 8423 sets the value of the extension bit to the upper limit value or the lower limit value. Moreover, you may set to arbitrary values other than an upper limit or a lower limit.

  The operation execution unit 8423 determines whether or not the mask bit permits writing to the entry (S25). For example, when the mask bit is “1”, it is determined that writing is permitted.

  When it is determined that writing is permitted (Yes in S25), the operation execution unit 8423 performs operation processing on the value stored in the extension bit storage unit 8422 (S26). For example, an arithmetic process of incrementing or decrementing the value is performed. Here, when the result of the arithmetic processing exceeds the upper limit value of the extension bit value, the arithmetic execution unit 8423 sets the lower limit value of the extension bit as the result of the arithmetic processing. Also, when the result of the arithmetic processing falls below the lower limit value of the extension bit value, the arithmetic execution unit 8423 sets the upper limit value of the extension bit as the result of the arithmetic processing.

  Next, a case where an instruction is executed in the second embodiment will be described with reference to FIGS. In the description, a case where m is 4 and x is 2, that is, a case where the number of entries in the vector register 1 is 16 and the number of entries in the physical vector register is 4 will be described. The description will be made assuming that the number of physical vector registers is four. One logical vector register number (0) is given to the vector register 1, and the number of elements of the logical vector register 0 is 4. That is, the vector register 1 is accessed from the program as one logical vector register having four elements (four entries).

  FIG. 16 shows a correspondence table between logical vector register entries and physical vector register entries when register renaming is executed. Based on the correspondence table, the logical vector register and the physical vector register are associated with each other. The correspondence table is an example, and the association is not limited to this.

  Referring to FIGS. 17A to 17B and FIGS. 18C to 18D, one normal instruction for writing vector data to logical vector register No. 0 (hereinafter, instruction 0), masked instruction A case where two instructions are executed (hereinafter, instruction M1 and instruction M2 respectively) will be described. In FIG. 17 and FIG. 18, the entry of the vector register 1 is e0 to e15, and the entry of each physical vector register is fe0 to fe3. Note that any four of the entries e0 to e15 of the vector register 1 are associated with any of the four entries of the logical vector register 0. That is, the logical vector register 0 entry associated with the physical vector register entry is any four of the vector register 1 entries.

  FIG. 17A shows an initial state. In the initial state, it is assumed that all values of the physical 0 extension bit register 82-0 to the physical 3 extension bit register 82-3 are initial values (represented by hyphens (-) here). It is assumed that all entries in the vector register 1 and all entries in the physical vector register 0 to the physical vector register 3 have initial values (represented by hyphens (-) here). It is assumed that both the rename information and the latest state information are initial values (represented by a hyphen (-) here).

  A case where instruction 0 is executed will be described.

  Note that control information is transferred to the mask unit 6, the register management unit 700, and the register control unit 12 by issuing an instruction. Hereinafter, the same applies to the description of instruction execution.

  As for the logical vector register No. 0 of the instruction 0, the physical vector register No. 2 is designated by register renaming in the register management unit 700. Since the instruction 0 is a normal instruction, the output of the mask identification circuit 841 is “1”. The output of the mask identification circuit 841 is stored in the mask bit storage unit 8421.

  Since the instruction 0 is a normal instruction, the outputs of the mask identification circuit 841 corresponding to each entry are all “1”. Since the latest state information transmitted from the register management unit 700 is an initial value, the value of the physical 2 extension bit register 82-2 corresponding to the write physical vector register number “2” is selected by the write selector 8401. The value selected by the write selector 8401 is stored in the extension bit storage unit 8422. The arithmetic circuit 8420 performs arithmetic processing using the value stored in the mask bit storage unit 8421 and the value stored in the extension bit storage unit 8422. Here, since the value stored in the physical 2 extension bit register 82-2 is an initial value, the arithmetic circuit 8420 outputs “00”, which is the lower limit value of the extension bit, as an operation result. The calculation result is written by the update determination circuit 843 to the corresponding entry of the physical 2 extension bit register 82-2 via the path 844-2.

  The association between each entry of the physical vector register 2 and each entry of the logical vector register 0 is performed as follows.

  1) 1 bit corresponding from physical 0 extended bit register 82-0 to physical n extended bit register 82-n by WP (binary number "00") corresponding to entry 0 (fe0) of physical vector register 2 Is read by the extension bit register control unit 86. The read values are transmitted to the update unit 8400 via the path 820-0 to path 820-n, respectively.

  2) The mask identification circuit 841 receives the contents and mask information of the mask register corresponding to the WP from the mask unit 6 via the path 60. Since the instruction 0 is a normal instruction, the mask identification circuit 841 outputs a 1-bit value “1” to the arithmetic circuit 8420 based on the mask information.

  3) The write selector 8401 receives the write physical vector register number “2” via the path 70. Further, the write selector 8401 receives the latest state information via the path 701. Since the latest state information is an initial value, the write selector 8401 selects the path 820-2 corresponding to the write physical vector register number “2”, and sends the initial value, which is the value of the physical 2 extension bit register, to the arithmetic circuit 842. Send. Here, for example, NULL data or the like is transmitted as an initial value.

  4) Since the initial value received from the write selector 8401 is stored in the extension bit storage unit 8422, the arithmetic circuit 8420 outputs “00”, which is the lower limit value of the extension bit, as the operation result. The arithmetic circuit 8420 transmits the calculation result to the pointer synthesis unit 9 and the update determination circuit 843 via the path 80. The calculation result is transmitted to the pointer synthesis unit 9 as WEX.

  5) The update determination circuit 843 receives the write physical vector register number “2” via the path 70. In addition, the update determination circuit 843 receives the calculation result of the calculation circuit 842 through the path 80. Since the write physical vector register number is “2”, the update determination circuit 843 transmits the calculation result and the update instruction to the path 844-2.

  6) The physical 2 extension bit register 82-2 writes the calculation result received from the update determination circuit 843 via the path 844-2 into the entry corresponding to WP.

  7) The pointer combining unit 9 generates a write extension pointer from the WEX received via the path 80 and the WP received via the path 40 by the WP combining circuit 92. Since WEX is “00” and WP is “00”, the write extension pointer is binary “0000”. The write extension pointer “0000” points to e0 of the vector register 1 according to the correspondence table of FIG.

  As described above, the logical vector register 0 entry 0 is associated with e0 of the vector register 1 and fe0 of the physical vector register 2. By the instruction 0, an element of vector data is written in the entry e0 of the vector register 1 specified by the write extension pointer “0000”. That is, the element of the vector data written in e0 of the vector register 1 is written into the entry 0 of the logical vector register 0 by the program. Physically, an element of vector data is written in entry fe0 of physical vector register 2 corresponding to e0 of vector register 1.

  From entry 1 onward of physical vector register 2, WP is incremented by 1 (increment), and the number of entries of physical vector register 1 is repeated from 1) above. When the WP changes from “00” to “11”, the entries of the vector register 1 associated with the physical vector register 2 are e0, e1, e2, and e3, respectively. In FIG. 17B, they are expressed as fe0 (e0), fe1 (e1), fe2 (e2), and fe3 (e3). The four entries of the logical vector register 0 are associated with e0, e1, e2, and e3 of the vector register 1, respectively.

  FIG. 17B shows the state after the instruction 0 is executed.

  In the physical 2 extension bit register 82-2, the values of all bits are “00”. A, B, C, and D are stored in e0 to e3 of the vector register 1 (that is, entries 0 to 3 of the logical vector register 0), respectively. At this time, the four entries fe0 to fe3 of the physical vector register 2 correspond to the e0 to e3 of the vector register 1 (that is, the entries 0 to 3 of the logical vector register 0), and their contents are A, B, C, D.

  After the instruction 0 is executed, the register state after the register renaming is held in the physical vector register No. 2, and the register state before the register renaming is held in the other physical vector registers. Therefore, register renaming is correctly performed.

  Next, execution of the instruction M1, which is an instruction with a mask, will be described.

  The logical vector register 0 of the instruction M1 is assumed to be designated as the physical vector register 0 by register renaming in the register management unit 700. The output of the mask identification circuit 841 is stored in the mask bit storage unit 8421.

  The instruction M1 is an instruction with a mask, and the output of the mask identification circuit 841 corresponding to each entry is 1, 1, 0, 0, respectively. Since the latest state information transmitted from the register management unit 700 is “2” indicating the physical vector register No. 2, the value of the physical 2 extension bit register 82-2 is selected by the write selector 8401. The value selected by the write selector 8401 is stored in the extension bit storage unit 8422. The arithmetic circuit 8420 performs arithmetic processing using the value stored in the mask bit storage unit 8421 and the value stored in the extension bit storage unit 8422. The arithmetic circuit 8420 transmits the calculation result to the pointer synthesis unit 9 and the update determination circuit 843. The calculation result is written by the update determination circuit 843 into the corresponding entry of the physical 0 extension bit register 82-0 via the path 844-0. This is because the write physical vector register number is “0”.

  The association between each entry in the physical vector register 0 and each entry in the logical vector register 0 is performed as follows.

  1-0) Corresponding from the physical 0 extension bit register 82-0 to the physical n extension bit register 82-n by the WP (binary number "00") corresponding to the entry 0 (fe0) of the physical vector register 2 The 1-bit value is read by the extension bit register control unit 86. The read values are transmitted to the update unit 8400 via the path 820-0 to path 820-n, respectively.

  2-0) The mask identification circuit 841 receives the contents of the mask register and the mask information corresponding to the WP from the mask unit 6 via the path 60. The instruction M1 is an instruction with a mask, and the value corresponding to the entry 0 is “1”. The mask identification circuit 841 outputs the result to the mask bit storage unit 8421.

  3-0) The write selector 8401 receives the write physical vector register number “0” via the path 70. Further, the write selector 8401 receives the latest state information via the path 701. Since the latest state information is “2” (actually expressed in binary, but expressed in decimal for convenience. The same shall apply hereinafter), the write selector 8401 selects the path 820-2 and expands physical 2 The bit register value “00” is transmitted to the extension bit storage unit 8422 of the arithmetic circuit 8420.

  4-0) The arithmetic circuit 8420 executes arithmetic processing based on the value stored in the mask bit storage unit 8421 and the value stored in the extension bit storage unit 8422. Since the value stored in the mask bit storage unit 8421 is “1”, the arithmetic circuit 8420 executes arithmetic processing. Here, the arithmetic circuit 8420 generates “01” obtained by incrementing the value “00” stored in the extension bit storage unit 8422 by 1, as the operation result. The arithmetic circuit 8420 transmits the calculation result to the pointer synthesis unit 9 and the update determination circuit 843 via the path 80. The calculation result is transmitted to the pointer synthesis unit 9 as WEX.

  5-0) The update determination circuit 843 receives the write physical vector register number “0” via the path 70. In addition, the update determination circuit 843 receives the calculation result of the calculation circuit 8420 through the path 80. Since the write physical vector register number is “0”, the update determination circuit 843 transmits the calculation result and the update instruction to the path 844-0.

  6-0) The physical 0 extension bit register 82-0 writes the operation result received via the path 844-0 in the entry corresponding to WP.

  7-0) The pointer synthesis unit 9 generates a write extension pointer from the WEX received via the path 80 and the WP received via the path 40 by the WP synthesis circuit 92. Since WEX is “01” and WP is “00”, the write extension pointer is binary “0100”. The write extension pointer “0100” points to e4 of the vector register 1 according to the correspondence table of FIG.

  The association is also performed in the same manner as described above for the entry 1 and later of the physical vector register 0.

  The entries in the vector register 1 associated with the physical vector register 0 are e4, e5, e2, and e3, respectively. In FIG. 18C, they are expressed as fe0 (e4), fe1 (e5), fe2 (e2), and fe3 (e3). The four entries of the logical vector register 0 are associated with e4, e5, e2, and e3 of the vector register 1, respectively.

  FIG. 18C shows a state after execution of the instruction M1.

  The values of the physical 0 extension bit register 82-0 are “01”, “01”, “00”, and “00”, respectively. E and F are stored in e4 and e5 of the vector register 1, respectively. At this time, the four entries fe0 to fe3 of the physical vector register 0 correspond to the e4, e5, e2, and e3 of the vector register 1 (that is, the entries 0 to 3 of the logical vector register 0), and their contents Are E, F, C, and D.

  After execution of the instruction M1, the physical vector register No. 0 holds the register state after register renaming, and the other physical vector registers hold the register state before register renaming. Therefore, register renaming is correctly performed.

  The instruction M2 is also executed by the same process as described above.

  FIG. 18D shows a state after execution of the instruction M2. The register renaming is correctly executed as in the case after the execution of the instruction M1.

  As described above, according to the second embodiment of the present invention, even when the number of vector register entries, the number of physical vector register entries, and the number of physical vector registers are arbitrarily set, at the time of executing the mask operation, Register renaming is possible for vector registers. This makes it possible to improve instruction execution performance in processing using vector data. In an information processing device that processes vector data, the number of vector registers that store vector data becomes very large, so the number of vector register entries, the number of physical vector register entries, and the number of physical vector registers can be set arbitrarily. Even in this case, register renaming is possible, and the effect of improving the instruction execution performance is exceptional.

It is a block diagram for demonstrating the information processing apparatus in the 1st Embodiment of this invention. It is a table | surface for demonstrating the 1st Embodiment of this invention. It is a figure for demonstrating the 1st Embodiment of this invention. It is a block diagram for demonstrating the extension bit part in the 1st Embodiment of this invention. It is a block diagram for demonstrating the update part in the 1st Embodiment of this invention. It is a block diagram for demonstrating the pointer synthetic | combination part in the 1st Embodiment of this invention. It is a figure for demonstrating the 1st Embodiment of this invention. It is a figure for demonstrating the 1st Embodiment of this invention. It is a flowchart for demonstrating the 1st Embodiment of this invention. It is a table | surface for demonstrating the 2nd Embodiment of this invention. It is a block diagram for demonstrating the information processing apparatus in the 2nd Embodiment of this invention. It is a block diagram for demonstrating the extension bit part in the 2nd Embodiment of this invention. It is a block diagram for demonstrating the update part in the 2nd Embodiment of this invention. It is a block diagram for demonstrating the arithmetic circuit in the 2nd Embodiment of this invention. It is a flowchart for demonstrating the operation | movement of the 2nd Embodiment of this invention. It is a table | surface for demonstrating the 2nd Embodiment of this invention. It is a figure for demonstrating the 2nd Embodiment of this invention. It is a figure for demonstrating the 2nd Embodiment of this invention.

Explanation of symbols

1 Vector register 2 WD register 3 RD register 4 WP register 5 RP register 6 Mask unit 7 Register management unit 700 Register management unit 8 Extension bit unit 800 Extension bit unit 82 Physical 0 extension bit register 82-0 to 82-n Physical n extension Bit register 83 Physical 1 extension bit register 84 Update unit 8400 Update unit 840 Write selector 8401 Write selector 841 Mask identification circuit 842 Calculation circuit 8420 Calculation circuit 8421 Mask bit storage unit 8422 Extension bit storage unit 8423 Calculation execution unit 843 Update determination circuit 8000 Extension Bit storage unit 85 Read selector 86 Extension bit register control unit 9 Pointer synthesis unit 92 WP synthesis circuit 93 RP synthesis circuit 10 WE register 11 WE control unit 12 Register control unit 13 Information processing device

Claims (2)

An information processing apparatus for processing a logical vector register having n elements (0th element to n-1th element),
The information processing apparatus includes a vector register having 2n entries (0th entry to 2n-1th entry), an n-bit first extension bit register, an n-bit second extension bit register, and n bits With a mask register,
The information processing apparatus performs a rename process for associating each element of the logical register with an entry of the vector register,
The renaming process is a process of associating the i-th element (0 ≦ i ≦ n−1) of the logical register with either the i-th entry or i + n-th entry of the vector register. for the n-1 element,
As a result of the rename process, “0” is stored in the first extension bit register when “0” is associated with the i-th entry for each element, and “1” is stored in the first extension bit register. Represented in bits,
Performing an arithmetic process to update a corresponding entry (physical vector register) of the vector register based on the result of the rename process;
Next, when the logical register is renamed, the result of the rename process similar to the rename process is stored in the second extension bit register and expressed by a total of n bits,
Performing an arithmetic process to update a corresponding entry (physical vector register) of the vector register based on the result of the rename process;
Thereafter, the rename process and the arithmetic process are alternately performed using the first extension bit register or the second extension bit register.
The mask register sets “1” to all bits when the operation with mask is not performed, and sets “1” to the bit position corresponding to the element to be updated and “1” as the element not to be updated when the operation with mask is performed. Keep “0” in the corresponding bit position,
In the renaming process, the result of performing an exclusive OR (XOR) operation between the extension bit register and the mask register that does not store the result of the renaming process (the one that stored the result of the previous renaming process) By storing the result of the renaming process in the extension bit register that stores the result, the component corresponding to the bit position that is “0” of the mask register is associated with the entry of the vector register before the update, and the mask register An information processing apparatus characterized in that a component corresponding to a bit position of “1” is associated with an entry of a vector register to be updated . An information processing method in an information processing apparatus for processing a logical vector register having n elements (0th element to n-1th element),
The information processing apparatus includes a vector register having 2n entries (0th entry to 2n-1th entry), an extension bit including an n-bit first extension bit register and an n-bit second extension bit register And an n-bit mask register,
The information processing apparatus performs a rename process for associating each element of the logical register with an entry of the vector register,
The renaming process is a process of associating the i-th element (0 ≦ i ≦ n−1) of the logical register with either the i-th entry or i + n-th entry of the vector register. for the n-1 element,
The extension bit unit sets the result of the rename process to “0” when the element is associated with the i-th entry for each element, and “1” when the element is associated with the i + n-th entry. Stored in a total of n bits,
The extension bit unit performs an arithmetic process to update a corresponding entry (physical vector register) of the vector register based on the result of the rename process,
Next, when the logical register is renamed, the result of the rename process similar to the rename process is stored in the second extension bit register and expressed by a total of n bits,
The extension bit unit performs an arithmetic process to update a corresponding entry (physical vector register) of the vector register based on the result of the rename process,
Thereafter, the rename process and the arithmetic process are alternately performed using the first extension bit register or the second extension bit register.
The mask register sets “1” to all bits when the operation with mask is not performed, and sets “1” to the bit position corresponding to the element to be updated and “1” as the element not to be updated when the operation with mask is performed. Keep “0” in the corresponding bit position,
The extension bit unit performs an exclusive OR (XOR) operation between the extension bit register that does not store the result of the rename process (the one that stores the result of the previous rename process) and the mask register in the rename process. The result corresponding to the bit position that is “0” of the mask register is stored in the entry of the vector register before the update. An information processing method , wherein a component corresponding to a bit position that is “1” of the mask register is associated with an entry of a vector register to be updated .

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