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JP5002468B2 - Semiconductor pressure sensor - Google Patents
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JP5002468B2 - Semiconductor pressure sensor - Google Patents

Semiconductor pressure sensor Download PDF

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JP5002468B2
JP5002468B2 JP2008016233A JP2008016233A JP5002468B2 JP 5002468 B2 JP5002468 B2 JP 5002468B2 JP 2008016233 A JP2008016233 A JP 2008016233A JP 2008016233 A JP2008016233 A JP 2008016233A JP 5002468 B2 JP5002468 B2 JP 5002468B2
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pressure sensor
diffusion
semiconductor pressure
piezoresistive
insulating film
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JP2009175078A (en
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岳司 吉田
卓也 砂田
史仁 加藤
雄一 新村
沙知子 麦生田
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Description

本発明は、複数のピエゾ抵抗素子により構成されるブリッジ回路を利用してダイヤフラム部に加えられた圧力を検出する半導体圧力センサに関する。   The present invention relates to a semiconductor pressure sensor that detects a pressure applied to a diaphragm portion using a bridge circuit composed of a plurality of piezoresistive elements.

従来より、ダイヤフラム部表面の離間した複数位置にピエゾ抵抗素子を配置し、このピエゾ抵抗素子によりブリッジ回路を構成することにより、圧力を受けた際にダイヤフラム部に生じる撓みをピエゾ抵抗素子の抵抗値の変化に伴う印加バイアスに対するブリッジ回路の出力電圧の変化として検出する半導体圧力センサが知られている。このような半導体圧力センサでは、ブリッジ回路に電源を投入した際にオフセット電圧(センサに圧力が印加されていない時のブリッジ回路の出力電圧値)が変動する現象が起きる。この現象が起きる原因として、センサ表面上に存在する可動イオンが電源投入後にピエゾ抵抗素子表面を移動することによりピエゾ抵抗素子の抵抗値が変化することが考えられる。このような背景から、絶縁膜を介してピエゾ抵抗素子表面上に導電体膜を形成し、この導電体膜をブリッジ回路の最低電位部に接続することにより、いわゆる電気シールドを設けてこの可動イオンによるピエゾ抵抗素子の抵抗値の変化を抑制する方法が提案されている(特許文献1参照)。
特開2001−281085号公報
Conventionally, by arranging piezoresistive elements at a plurality of spaced positions on the surface of the diaphragm part, and forming a bridge circuit with this piezoresistive element, the resistance value of the piezoresistive element is caused by the bending that occurs in the diaphragm part under pressure. 2. Description of the Related Art A semiconductor pressure sensor that detects a change in the output voltage of a bridge circuit with respect to an applied bias accompanying a change in voltage is known. In such a semiconductor pressure sensor, a phenomenon occurs in which the offset voltage (the output voltage value of the bridge circuit when no pressure is applied to the sensor) fluctuates when power is supplied to the bridge circuit. A possible cause of this phenomenon is that the resistance value of the piezoresistive element changes due to the movement of mobile ions present on the sensor surface on the surface of the piezoresistive element after the power is turned on. From such a background, a conductive film is formed on the surface of the piezoresistive element through an insulating film, and this conductive film is connected to the lowest potential portion of the bridge circuit, so that a so-called electric shield is provided to provide the movable ion. There has been proposed a method for suppressing a change in the resistance value of the piezoresistive element due to (see Patent Document 1).
JP 2001-281085 A

しかしながら、従来の半導体圧力センサによれば、絶縁膜の膜厚がミクロンオーダーと大きい場合は電源投入後のオフセット電圧の変動を抑制することができるが、絶縁膜の膜厚が数千Åと比較的小さくなった場合には、オフセット電圧の変動を抑制することができなくなる。このため従来の半導体圧力センサによれば、電源投入後のオフセット電圧の変動を抑制しつつ絶縁膜の膜厚を小さくしてセンサの小型化を実現することが困難であった。   However, according to the conventional semiconductor pressure sensor, when the film thickness of the insulating film is as large as micron, the fluctuation of the offset voltage after power-on can be suppressed, but the film thickness of the insulating film is compared with several thousand mm. When it becomes smaller, the fluctuation of the offset voltage cannot be suppressed. For this reason, according to the conventional semiconductor pressure sensor, it has been difficult to reduce the thickness of the insulating film while suppressing the fluctuation of the offset voltage after the power is turned on, thereby realizing the downsizing of the sensor.

本発明は上記課題を解決するためになされたものであり、電源投入後のオフセット電圧の変動を抑制しつつ小型化することが可能な半導体圧力センサを提供することにある。   The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a semiconductor pressure sensor that can be miniaturized while suppressing fluctuations in offset voltage after power-on.

本発明に係る半導体圧力センサは、ダイヤフラム部を備える半導体基板と、ダイヤフラム部表面に形成され、ダイヤフラム部に加えられた圧力を抵抗値変化として検出する複数のピエゾ抵抗素子と、半導体基板表面に形成され、複数のピエゾ抵抗素子を接続してブリッジ回路を構成する拡散配線と、ピエゾ抵抗素子及び拡散配線の表面を含む半導体基板表面を被覆する絶縁膜と、絶縁膜の表面に形成された導電体層とを有する半導体圧力センサにおいて、導電体層がブリッジ回路の最高電位部に接続され、前記拡散配線のうち、前記ピエゾ抵抗素子を挟んで離間配置された拡散配線の対の間のピエゾ抵抗素子が介在しない領域に対応する前記絶縁膜表面には、前記導電体層が形成されていないことを特徴とする。
A semiconductor pressure sensor according to the present invention includes a semiconductor substrate having a diaphragm portion, a plurality of piezoresistive elements that are formed on the surface of the diaphragm portion and detect pressure applied to the diaphragm portion as a change in resistance value, and formed on the surface of the semiconductor substrate. A diffusion wiring that connects a plurality of piezoresistive elements to form a bridge circuit, an insulating film that covers the surface of the semiconductor substrate including the surfaces of the piezoresistive elements and the diffusion wiring, and a conductor formed on the surface of the insulating film In the semiconductor pressure sensor having a layer, a conductor layer is connected to the highest potential portion of the bridge circuit, and among the diffusion wirings, a piezoresistance element between a pair of diffusion wirings spaced apart with the piezoresistance element interposed therebetween The conductor layer is not formed on the surface of the insulating film corresponding to a region where no intervening layer is present.

本発明に係る半導体圧力センサによれば、電源投入後のオフセット電圧の変動を抑制しつつ小型化することができる。   According to the semiconductor pressure sensor of the present invention, it is possible to reduce the size while suppressing the fluctuation of the offset voltage after the power is turned on.

以下、図面を参照して、本発明の実施形態となる半導体圧力センサについて説明する。   Hereinafter, a semiconductor pressure sensor according to an embodiment of the present invention will be described with reference to the drawings.

本発明の実施形態となる半導体圧力センサ1は、図1(a),(b)に示すように、矩形形状のダイヤフラム部2が形成されたSOI半導体基板3と、ダイヤフラム部2の各辺中央内側付近のSOI半導体基板3表面領域に形成されたピエゾ抵抗素子R1〜R8とを備える。近接するピエゾ抵抗素子R1,R2は拡散配線L1を介して接続されている。ピエゾ抵抗素子R1は拡散配線L2と薄膜金属配線4aを介して最低電位部となる接地端子GNDに接続され、ピエゾ抵抗素子R2は拡散配線L3と薄膜金属配線4bを介して電圧出力端子Vout+に接続されている。近接するピエゾ抵抗素子R3,R4は拡散配線L4を介して接続されている。ピエゾ抵抗素子R3は拡散配線L5と薄膜金属配線4cを介して電圧出力端子Vout+に接続され、ピエゾ抵抗素子R4は拡散配線L6と薄膜金属配線4dを介して最高電位部となるバイアス電圧印加用端子Vddに接続されている。   As shown in FIGS. 1A and 1B, a semiconductor pressure sensor 1 according to an embodiment of the present invention includes an SOI semiconductor substrate 3 on which a rectangular diaphragm portion 2 is formed, and the center of each side of the diaphragm portion 2. Piezoresistive elements R1 to R8 formed in the surface region of the SOI semiconductor substrate 3 near the inside. Adjacent piezoresistive elements R1, R2 are connected via a diffusion line L1. The piezoresistive element R1 is connected to the ground terminal GND serving as the lowest potential portion via the diffusion line L2 and the thin film metal line 4a, and the piezoresistive element R2 is connected to the voltage output terminal Vout + via the diffusion line L3 and the thin film metal line 4b. Has been. Adjacent piezoresistive elements R3 and R4 are connected via a diffusion line L4. The piezoresistive element R3 is connected to the voltage output terminal Vout + via the diffusion line L5 and the thin film metal line 4c, and the piezoresistive element R4 is a bias voltage application terminal that becomes the highest potential portion via the diffusion line L6 and the thin film metal line 4d. Connected to Vdd.

近接するピエゾ抵抗素子R5,R6は拡散配線L7を介して接続されている。ピエゾ抵抗素子R5は拡散配線L8と薄膜金属配線4eを介してバイアス電圧印加用端子Vddに接続され、ピエゾ抵抗素子R6は拡散配線L9と薄膜金属配線4fを介して電圧出力端子Vout−に接続されている。近接するピエゾ抵抗素子R7,R8は拡散配線L10を介して接続されている。ピエゾ抵抗素子R7は拡散配線L11と薄膜金属配線4gを介して電圧出力端子Vout−に接続され、ピエゾ抵抗素子R8は拡散配線L12と薄膜金属配線4hを介して接地端子GNDに接続されている。拡散配線L1〜L12はSOI半導体基板3表面に不純物イオンを注入,拡散することにより形成される。薄膜金属配線4a〜4hは後述する絶縁膜5表面上に形成され、絶縁膜5に形成されたスルーホールを介して拡散配線L1〜L12と接続されている。   Adjacent piezoresistive elements R5 and R6 are connected via a diffusion line L7. The piezoresistive element R5 is connected to the bias voltage application terminal Vdd via the diffusion line L8 and the thin film metal line 4e, and the piezoresistive element R6 is connected to the voltage output terminal Vout− via the diffusion line L9 and the thin film metal line 4f. ing. Adjacent piezoresistive elements R7 and R8 are connected via a diffusion line L10. The piezoresistive element R7 is connected to the voltage output terminal Vout− via the diffusion line L11 and the thin film metal line 4g, and the piezoresistive element R8 is connected to the ground terminal GND via the diffusion line L12 and the thin film metal line 4h. The diffusion lines L1 to L12 are formed by implanting and diffusing impurity ions on the surface of the SOI semiconductor substrate 3. The thin film metal wirings 4a to 4h are formed on the surface of an insulating film 5 described later, and are connected to the diffusion wirings L1 to L12 through through holes formed in the insulating film 5.

このような構成を有する半導体圧力センサ1では、ピエゾ抵抗素子R1〜R8は図1(c)に示すようなブリッジ回路を構成している。すなわち、ピエゾ抵抗素子R1,R2及びピエゾ抵抗素子R5,R6とピエゾ抵抗素子R3,R4及びピエゾ抵抗素子R7,R8とがそれぞれ対になってブリッジ回路上で対向配置されている。このような構成を有する半導体圧力センサ1では、ダイヤフラム部2の一方の表面に圧力が加わると、ダイヤフラム部2の上面と下面との間に差圧が生じることによってダイヤフラム部2に撓みが生じ、この撓みによってピエゾ抵抗素子R1〜R8を形成する結晶が歪んで抵抗値が変化する。そしてピエゾ抵抗素子R1〜R8の抵抗値の変化をブリッジ回路を利用してバイアス電圧印加用端子Vddに印加されたバイアス電圧Biasに対する電圧変化として出力端子Vout+,Vout−から検出する。   In the semiconductor pressure sensor 1 having such a configuration, the piezoresistive elements R1 to R8 form a bridge circuit as shown in FIG. That is, the piezoresistive elements R1 and R2, the piezoresistive elements R5 and R6, the piezoresistive elements R3 and R4, and the piezoresistive elements R7 and R8 are paired and arranged on the bridge circuit. In the semiconductor pressure sensor 1 having such a configuration, when pressure is applied to one surface of the diaphragm portion 2, a differential pressure is generated between the upper surface and the lower surface of the diaphragm portion 2, so that the diaphragm portion 2 is bent, Due to this bending, the crystals forming the piezoresistive elements R1 to R8 are distorted and the resistance value changes. Then, changes in the resistance values of the piezoresistive elements R1 to R8 are detected from the output terminals Vout + and Vout− as voltage changes with respect to the bias voltage Bias applied to the bias voltage application terminal Vdd using a bridge circuit.

この半導体圧力センサ1では、ピエゾ抵抗素子R1〜R8と拡散リード線L1〜L12の表面を含むSOI半導体基板3表面には絶縁膜5が形成され、さらにダイヤフラム部2表面及び拡散配線L1〜L12表面に対応する絶縁膜5表面上には導電体膜6が形成されている。また導電体膜6は領域Xにおいて最高電位部となるバイアス電圧印加用端子Vddに接続されている。ここで絶縁膜5の膜厚が数千Åオーダーである時に導電体膜6を最高電位部となるバイパス電圧印加用端子Vddに接続した場合と最低電位部となる接地端子GNDに接続した場合における電源投入後のオフセット電圧の変動をシミュレーションした結果、導電体膜6を最低電位部に接続した場合、オフセット電圧の変動量は1.7%であったのに対し、導電体膜6を最高電位部に接続した場合には、オフセット電圧の変動量は0.2%であった。   In this semiconductor pressure sensor 1, an insulating film 5 is formed on the surface of the SOI semiconductor substrate 3 including the surfaces of the piezoresistive elements R1 to R8 and the diffusion lead wires L1 to L12, and further the surface of the diaphragm portion 2 and the surfaces of the diffusion wirings L1 to L12. A conductor film 6 is formed on the surface of the insulating film 5 corresponding to. The conductor film 6 is connected to a bias voltage application terminal Vdd that is the highest potential portion in the region X. Here, when the film thickness of the insulating film 5 is on the order of several thousand Å, the conductor film 6 is connected to the bypass voltage application terminal Vdd that is the highest potential part and the ground film GND that is the lowest potential part. As a result of simulating the fluctuation of the offset voltage after power-on, when the conductor film 6 is connected to the lowest potential portion, the fluctuation amount of the offset voltage was 1.7%, whereas the conductor film 6 was the highest potential. In the case of being connected to the part, the variation amount of the offset voltage was 0.2%.

従って本発明の実施形態となる半導体圧力センサ1によれば、電源投入後のオフセット電圧の変動を抑制しつつセンサの小型化を実現できる。また本実施形態では、導電体膜6は、ダイヤフラム部2の全面に形成され、またダイヤフラム部2の中心軸に対して線対称形状であるので、導電体膜6を非局所的、非対称形状で形成した場合と比較して、ダイヤフラム部2表面の応力バランスを良好にし、応力バランスが崩れることによってオフセット電圧が発生することを抑制できる。   Therefore, according to the semiconductor pressure sensor 1 according to the embodiment of the present invention, it is possible to reduce the size of the sensor while suppressing the fluctuation of the offset voltage after the power is turned on. In the present embodiment, the conductor film 6 is formed on the entire surface of the diaphragm portion 2 and has a line-symmetric shape with respect to the central axis of the diaphragm portion 2, so that the conductor film 6 has a non-local and asymmetric shape. Compared with the case where it forms, it can make the stress balance of the diaphragm part 2 surface favorable, and can suppress that an offset voltage generate | occur | produces by breaking a stress balance.

本実施形態では、ダイヤフラム部2の全面に導電体膜6を形成したが、図2(a),(b)に示すように、拡散配線L1〜L12のうち、ピエゾ抵抗素子を挟んで離間配置された拡散配線の対(具体的には拡散配線L1,L2、拡散配線L1,L3、拡散配線L4,L5、拡散配線L4,L6、拡散配線L7,L8、拡散配線L7,L9、拡散配線L10,L11、拡散配線L10,L12)の間(例えば図2(a)に示す領域Y)のピエゾ抵抗素子が介在しない領域に対応する絶縁膜5表面(例えば図2(b)に示す領域S2。領域S1はピエゾ抵抗素子が介在する領域に対応する絶縁膜5表面を示す)には、例えば導電体層6の形状をリング形状にする等して導電体層6が形成されていないことが望ましい。   In this embodiment, the conductor film 6 is formed on the entire surface of the diaphragm portion 2. However, as shown in FIGS. 2A and 2B, the diffusion wirings L1 to L12 are spaced apart from each other with the piezoresistive element interposed therebetween. Diffusion line pairs (specifically, diffusion lines L1 and L2, diffusion lines L1 and L3, diffusion lines L4 and L5, diffusion lines L4 and L6, diffusion lines L7 and L8, diffusion lines L7 and L9, diffusion line L10) , L11, diffusion wirings L10, L12) (for example, region S2 shown in FIG. 2B) corresponding to the region where no piezoresistive element is interposed (for example, region Y shown in FIG. 2A). In the region S 1, the surface of the insulating film 5 corresponding to the region where the piezoresistive element is interposed) is preferably not formed by, for example, making the shape of the conductor layer 6 into a ring shape. .

このような構成によれば、ピエゾ抵抗素子を介さずに拡散配線間に漏れ電流が流れることを抑制し、オフセット電圧が変動することをさらに抑制できる。また導電体層6の形状をリング形状にした場合には、ダイヤフラム部2表面の応力バランスを良好にし、オフセット電圧が発生することを抑制できる。また導電体層6の面積を小さくし、SOI半導体基板3,絶縁膜5,及び導電体膜6の3層構造では困難であったダイヤフラム部2面内の応力バランス設計が不要となり、応力設計が容易になる。   According to such a configuration, it is possible to suppress the leakage current from flowing between the diffusion wirings without using the piezoresistive element, and to further suppress the fluctuation of the offset voltage. Moreover, when the shape of the conductor layer 6 is a ring shape, the stress balance on the surface of the diaphragm portion 2 can be improved, and the occurrence of an offset voltage can be suppressed. In addition, the area of the conductor layer 6 is reduced, and the stress balance design in the surface of the diaphragm portion 2 which is difficult in the three-layer structure of the SOI semiconductor substrate 3, the insulating film 5, and the conductor film 6 becomes unnecessary, and the stress design is reduced. It becomes easy.

本実施形態では、ダイヤフラム部2の全面に導電体膜6を形成したが、図3に示すように、近接するピエゾ抵抗素子(具体的にはピエゾ抵抗素子R1,R2、ピエゾ抵抗素子R3,R4、ピエゾ抵抗素子R5,R6、ピエゾ抵抗素子R7,R8)の間(例えば図2(a)に示す領域Z)に対応する絶縁膜5表面には導電体層6が形成されていないことが望ましい。このような構成によれば、近接するピエゾ抵抗素子間に漏れ電流が流れることを抑制し、オフセット電圧が変動することをさらに抑制できる。   In the present embodiment, the conductor film 6 is formed on the entire surface of the diaphragm portion 2, but as shown in FIG. 3, adjacent piezoresistive elements (specifically, piezoresistive elements R1, R2, piezoresistive elements R3, R4). It is desirable that the conductor layer 6 is not formed on the surface of the insulating film 5 corresponding to the space between the piezoresistive elements R5 and R6 and the piezoresistive elements R7 and R8 (for example, the region Z shown in FIG. 2A). . According to such a configuration, it is possible to suppress the leakage current from flowing between adjacent piezoresistive elements and further suppress the fluctuation of the offset voltage.

以上、本発明者らによってなされた発明を適用した実施の形態について説明したが、この実施の形態による本発明の開示の一部をなす記述及び図面により本発明は限定されることはない。すなわち、上記実施の形態に基づいて当業者等によりなされる他の実施の形態、実施例及び運用技術等は全て本発明の範疇に含まれることは勿論である。   As mentioned above, although embodiment which applied the invention made by the present inventors was described, this invention is not limited by description and drawing which make a part of indication of this invention by this embodiment. That is, it is needless to say that other embodiments, examples, operation techniques, and the like made by those skilled in the art based on the above-described embodiments are all included in the scope of the present invention.

本発明の実施形態となる半導体圧力センサの構成を示す(a)上面図及び(b)断面図と、(c)ピエゾ抵抗素子により構成されるブリッジ回路の構成を示す回路図である。It is a circuit diagram which shows the structure of the bridge circuit comprised by (a) top view and (b) sectional drawing which show the structure of the semiconductor pressure sensor used as embodiment of this invention, and (b) piezoresistive element. 図1に示す半導体圧力センサの変形例の構成を示す断面図である。It is sectional drawing which shows the structure of the modification of the semiconductor pressure sensor shown in FIG. 図1に示す半導体圧力センサの変形例の構成を示す断面図である。It is sectional drawing which shows the structure of the modification of the semiconductor pressure sensor shown in FIG.

符号の説明Explanation of symbols

1:半導体圧力センサ
2:ダイヤフラム部
3:SOI半導体基板
4a〜4h:薄膜金属配線
5:絶縁膜
6:導電体膜
GND:接地端子
L1〜L12:拡散配線
R1〜R8:ピエゾ抵抗素子
Vdd:バイアス電圧印加用端子
Vout+,Vout−:出力端子
1: Semiconductor pressure sensor 2: Diaphragm part 3: SOI semiconductor substrates 4a-4h: Thin film metal wiring 5: Insulating film 6: Conductor film GND: Ground terminals L1-L12: Diffusion wirings R1-R8: Piezoresistive element Vdd: Bias Voltage application terminals Vout +, Vout-: Output terminals

Claims (3)

ダイヤフラム部を備える半導体基板と、前記ダイヤフラム部表面に形成され、ダイヤフラム部に加えられた圧力を抵抗値変化として検出する複数のピエゾ抵抗素子と、前記半導体基板表面に形成され、前記複数のピエゾ抵抗素子を接続してブリッジ回路を構成する拡散配線と、前記ピエゾ抵抗素子及び前記拡散配線の表面を含む前記半導体基板表面を被覆する絶縁膜と、前記絶縁膜の表面に形成された導電体層とを有する半導体圧力センサにおいて、前記導電体層が前記ブリッジ回路の最高電位部に接続され、前記拡散配線のうち、前記ピエゾ抵抗素子を挟んで離間配置された拡散配線の対の間のピエゾ抵抗素子が介在しない領域に対応する前記絶縁膜表面には、前記導電体層が形成されていないことを特徴とする半導体圧力センサ。 A semiconductor substrate having a diaphragm portion; a plurality of piezoresistive elements formed on the surface of the diaphragm portion for detecting pressure applied to the diaphragm portion as a change in resistance; and a plurality of piezoresistors formed on the surface of the semiconductor substrate. Diffusion wiring that connects elements to form a bridge circuit, an insulating film that covers the surface of the semiconductor substrate including the surface of the piezoresistive element and the diffusion wiring, and a conductor layer formed on the surface of the insulating film; In the semiconductor pressure sensor, the conductor layer is connected to the highest potential portion of the bridge circuit, and the piezoresistive element between the pair of diffusion wirings that are spaced apart from each other with the piezoresistive element being sandwiched among the diffusion wirings A semiconductor pressure sensor characterized in that the conductor layer is not formed on the surface of the insulating film corresponding to a region where no intervening material is present . 請求項に記載の半導体圧力センサにおいて、前記複数のピエゾ抵抗素子のうち、近接するピエゾ抵抗素子間に対応する前記絶縁膜表面には、前記導電体層が形成されていないことを特徴とする半導体圧力センサ。 2. The semiconductor pressure sensor according to claim 1 , wherein the conductor layer is not formed on the surface of the insulating film corresponding to adjacent piezoresistive elements among the plurality of piezoresistive elements. Semiconductor pressure sensor. 請求項に記載の半導体圧力センサにおいて、前記導電体層がリング形状を有することを特徴とする半導体圧力センサ。 2. The semiconductor pressure sensor according to claim 1 , wherein the conductor layer has a ring shape.
JP2008016233A 2008-01-28 2008-01-28 Semiconductor pressure sensor Expired - Fee Related JP5002468B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014070962A (en) * 2012-09-28 2014-04-21 Fujikura Ltd Pressure sensor element
JP2018169177A (en) * 2017-03-29 2018-11-01 パナソニックIpマネジメント株式会社 Pressure sensor element and pressure sensor using the same

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JP3319173B2 (en) * 1994-09-19 2002-08-26 株式会社日立製作所 Sensor
JPH10142089A (en) * 1996-11-08 1998-05-29 Copal Electron Co Ltd Piezo resistance pressure device
JP3330831B2 (en) * 1996-12-02 2002-09-30 株式会社日立製作所 Strain detection sensor
JP2003194647A (en) * 2001-12-28 2003-07-09 Hitachi Unisia Automotive Ltd External force sensor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014070962A (en) * 2012-09-28 2014-04-21 Fujikura Ltd Pressure sensor element
JP2018169177A (en) * 2017-03-29 2018-11-01 パナソニックIpマネジメント株式会社 Pressure sensor element and pressure sensor using the same

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