Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JP5006746B2 - Three-dimensional circuit component structure - Google Patents
[go: Go Back, main page]

JP5006746B2 - Three-dimensional circuit component structure - Google Patents

Three-dimensional circuit component structure Download PDF

Info

Publication number
JP5006746B2
JP5006746B2 JP2007261484A JP2007261484A JP5006746B2 JP 5006746 B2 JP5006746 B2 JP 5006746B2 JP 2007261484 A JP2007261484 A JP 2007261484A JP 2007261484 A JP2007261484 A JP 2007261484A JP 5006746 B2 JP5006746 B2 JP 5006746B2
Authority
JP
Japan
Prior art keywords
insulating
electronic circuit
insulating partition
circuit board
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007261484A
Other languages
Japanese (ja)
Other versions
JP2009094174A (en
Inventor
浩聡 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sankyo Kasei Co Ltd
Original Assignee
Sankyo Kasei Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sankyo Kasei Co Ltd filed Critical Sankyo Kasei Co Ltd
Priority to JP2007261484A priority Critical patent/JP5006746B2/en
Publication of JP2009094174A publication Critical patent/JP2009094174A/en
Application granted granted Critical
Publication of JP5006746B2 publication Critical patent/JP5006746B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Combinations Of Printed Boards (AREA)

Description

本発明は、電子回路等を形成した回路基板同士を、相互に隣接する導電部を形成した接続部材を挟んで、電気的に接続した立体的な回路部品構造に関し、特に接続部材に形成した導電部相互の境界に絶縁隔壁を突設し、この絶縁隔壁によって、この導電部とこの電子回路等とを接続するろう付け層を、相互に隔離するように構成した立体的な回路部品構造に関する。   The present invention relates to a three-dimensional circuit component structure in which circuit boards on which electronic circuits or the like are formed are electrically connected to each other with a connection member formed with a conductive part adjacent to each other. The present invention relates to a three-dimensional circuit component structure in which an insulating partition wall is protruded at a boundary between parts, and a brazing layer connecting the conductive portion and the electronic circuit or the like is isolated from each other by the insulating partition wall.

従来より、絶縁基体の表面に電子回路等を形成した回路基板同士を、この回路基板の対向面に導電部を形成した接続部材を介して、相互にはんだ付け等によって、電気的に接続した立体的な回路部品が提案されている(例えば特許文献1〜3参照。)。しかるに、はんだ付け等によって接続する接続部材の導電部は、いずれもこの接続部材の表面から突出していた。   Conventionally, circuit boards in which an electronic circuit or the like is formed on the surface of an insulating substrate are electrically connected to each other by soldering or the like via a connecting member in which a conductive portion is formed on the opposite surface of the circuit board. A typical circuit component has been proposed (see, for example, Patent Documents 1 to 3). However, all of the conductive portions of the connecting member connected by soldering or the like protrude from the surface of the connecting member.

すなわち図4に示すように、接続部材201を構成する絶縁樹脂からなる絶縁基体211の表面には、凸状の突起部分211cが形成してあり、この凸状の突起部分の外表面に、無電解銅めっき等による第1導電部212が形成してある。また図5に示すように、電子回路基板202を構成する絶縁樹脂からなる絶縁基体221の表面は、平坦に形成してあり、この平坦な表面上に、無電解銅めっき等による電子回路等の第2導電部222が形成してある。   That is, as shown in FIG. 4, a convex protrusion 211c is formed on the surface of an insulating base 211 made of an insulating resin constituting the connecting member 201, and there is no protrusion on the outer surface of the convex protrusion. A first conductive portion 212 is formed by electrolytic copper plating or the like. Further, as shown in FIG. 5, the surface of the insulating base 221 made of an insulating resin constituting the electronic circuit board 202 is formed flat, and an electronic circuit or the like by electroless copper plating or the like is formed on the flat surface. A second conductive portion 222 is formed.

そして図5に示すように、電子回路基板202と接続部材201とを、電気的に接続する場合には、この接続部材に形成した第1導電部212と、電子回路基板に形成した第2導電部222とを、相互に対向するように配置し、これらの導電部の一方の表面にはんだを盛って加熱し、双方の導電部の間をはんだ付け層203により、電気的に接続していた。
特開2005−251889号公報(図1等) 特開2006−286660号公報(図1等) 特開2005−209596号公報(図6等)
As shown in FIG. 5, when the electronic circuit board 202 and the connection member 201 are electrically connected, the first conductive portion 212 formed on the connection member and the second conductivity formed on the electronic circuit board. The parts 222 are arranged so as to face each other, solder is deposited on one surface of these conductive parts and heated, and the conductive parts are electrically connected between the conductive parts by the soldering layer 203. .
JP 2005-251889 A (FIG. 1 etc.) JP 2006-286660 A (FIG. 1 etc.) Japanese Patent Laying-Open No. 2005-209596 (FIG. 6 etc.)

しかるに上述した従来の立体的な回路部品構造には、次の改善すべき問題があった。すなわち図5に示すように、上記特許文献1〜3に記載の回路部品構造では、接続部材201に形成した第1導電部212と、電子回路基板202に形成した第2導電部222とは、いずれもこの接続部材、及び電子回路基板の表面から突出している。したがって、はんだ付けのために、この導電部同士を相互に対向するように配置した場合には、それぞれ隣接する導電部の間には、空間204が生じてしまう。このため図6に示すように、はんだ付けの際に、はんだが飛び散って(「爆(は)ぜ」と呼ばれる。)、空間204にはんだの架橋205を形成し、隣接する導電部を短絡させてしまうという問題があった。   However, the conventional three-dimensional circuit component structure described above has the following problems to be improved. That is, as shown in FIG. 5, in the circuit component structures described in Patent Documents 1 to 3, the first conductive portion 212 formed on the connection member 201 and the second conductive portion 222 formed on the electronic circuit board 202 are: Both project from the connection member and the surface of the electronic circuit board. Accordingly, when the conductive parts are arranged so as to face each other for soldering, a space 204 is generated between the adjacent conductive parts. For this reason, as shown in FIG. 6, when soldering, the solder scatters (called “explosion”) to form a solder bridge 205 in the space 204 and short-circuit adjacent conductive parts. There was a problem that.

なお上述した「爆ぜ」は、はんだ等が、有機物からなるフラックスにはんだ等の成分を混合したものであるため、加熱した際に、気化した有機物の気泡が破裂し、はんだ等の成分が細い糸状になって、外部に飛散することによって生ずるものである。   In the above-mentioned “explosion”, since solder or the like is a mixture of solder and other components such as solder made of organic matter, the vaporized organic bubbles burst when heated, and the components such as solder are thin thread-like. This is caused by scattering outside.

特に最近は、例えば携帯電話のように、通話機能ばかりでなく、デジタルカメラ機能、インターネット機能、GPS機能、あるいはテレビ機能など、多くの機能を持つ電子機器が多い。したがって最近の電子機器は、極度に小型化され、さらに高機能、多機能になっているため、電子回路の幅、及びこの電子回路間のピッチがミクロンオーダにまで狭くなっている。したがって、上述した「爆ぜ」によって、隣接する電子回路が短絡する不具合が、より発生しやすくなっている。   In particular, recently, there are many electronic devices having many functions such as a digital camera function, an Internet function, a GPS function, or a television function as well as a telephone function, such as a mobile phone. Therefore, recent electronic devices are extremely miniaturized, and have higher functions and more functions. Therefore, the width of the electronic circuit and the pitch between the electronic circuits are reduced to the micron order. Therefore, the above-mentioned “explosion” is more likely to cause a problem that an adjacent electronic circuit is short-circuited.

そこで本願発明の目的は、はんだ付け等の際に生じる「爆ぜ」によって、隣接する電子回路が短絡する不具合を防止できる立体的な回路部品構造を提供することにある。   Accordingly, an object of the present invention is to provide a three-dimensional circuit component structure capable of preventing a short circuit between adjacent electronic circuits due to “explosion” generated during soldering or the like.

本願発明による立体的な回路部品構造の特徴は、接続部材の表面に設けた相互に隣接する第1導電部の境界部分に絶縁隔壁を突設し、この絶縁隔壁によって、相互に隣接するろう付け層を隔離させることにある。すなわち本願発明による立体的な回路部品構造は、電子回路基板と接続部材とを備え、この接続部材の、この電子回路基板と対向する表面には、絶縁隔壁が突設してあると共に、この絶縁隔壁を境界として相互に隣接する第1導電部が形成してある。上記電子回路基板の表面には、絶縁域を境界として相互に隣接する第2導電部が形成してある。上記第1導電部と第2導電部とは、ろう付け層を介して電気的に接続されている。そして上記絶縁隔壁の頂部は、上記絶縁域と隙間なく当接して、相互に隣接する上記ろう付け層を隔離している。   The three-dimensional circuit component structure according to the present invention is characterized in that an insulating partition wall protrudes from the boundary portion of the first conductive portions adjacent to each other provided on the surface of the connecting member, and is brazed adjacent to each other by the insulating partition wall. In isolating layers. That is, the three-dimensional circuit component structure according to the present invention includes an electronic circuit board and a connecting member, and an insulating partition wall protrudes from the surface of the connecting member facing the electronic circuit board. First conductive portions adjacent to each other with the partition wall as a boundary are formed. On the surface of the electronic circuit board, second conductive portions adjacent to each other with the insulating region as a boundary are formed. The first conductive part and the second conductive part are electrically connected via a brazing layer. And the top part of the said insulation partition is contact | abutted with the said insulation area without gap, and isolate | separates the said brazing layer adjacent to each other.

上記絶縁域は、上記電子回路基板の表面に突設した第2の絶縁隔壁からなり、上記絶縁隔壁の頂部は、この第2の絶縁隔壁の頂部と隙間なく当接して、相互に隣接する上記ろう付け層を隔離すように構成する。 The insulating region is composed of a second insulating partition protruding from the surface of the electronic circuit board, and the top of the insulating partition is in contact with the top of the second insulating partition without any gap and adjacent to each other. Configure to isolate the braze layer .

また上記第1導電部と絶縁隔壁との境界面に直交する方向において、この第1導電部の幅は、この絶縁隔壁の幅より広くしてもよい。   Further, the width of the first conductive portion may be wider than the width of the insulating partition in a direction perpendicular to the boundary surface between the first conductive portion and the insulating partition.

ここで「電子回路基板」とは、絶縁基体の表面に電子回路や接続端子等の導電部が形成され、抵抗、コンデンサ、あるいは半導体素子等の電子部品等が実装されているものを意味する。また「接続部材」とは、上述した「電子回路基板」同士を、電気的に接続するための部材を意味し、絶縁基体の表面であって、この「電子回路基板」に設けた導電部と対向する位置に、ろう付け層を介して電気的に接続する導電部が形成されているものを意味する。なお「接続部材」には、この「接続部材」の両側面に重ねる「電子回路基板」同士を電気的に接続するだけのものに限らず、この「接続部材」自体に、電子部品等が実装されているものも含む。   Here, the “electronic circuit board” means that a conductive part such as an electronic circuit or a connection terminal is formed on the surface of an insulating base, and an electronic component such as a resistor, a capacitor, or a semiconductor element is mounted. The “connecting member” means a member for electrically connecting the above-mentioned “electronic circuit boards” to each other, and is a surface of an insulating base, and a conductive portion provided on the “electronic circuit board”. It means that a conductive portion that is electrically connected via a brazing layer is formed at an opposing position. Note that the “connection member” is not limited to the one that electrically connects the “electronic circuit boards” stacked on both sides of the “connection member”, and electronic components and the like are mounted on the “connection member” itself. Including those that have been.

また「上記接続部材の上記電子回路基板と対向する」とは、「電子回路基板」を「接続部材」の両側面にそれぞれ重ねる場合に限らず、一方の側面にのみ重ねる場合も含む。「絶縁域」とは、電子回路基板の表面が平坦であって、この平坦な表面の一部、すなわち相互に隣接する第2導電部を隔てる境界面に限らず、相互に隣接する第2導電部の境界に絶縁隔壁を突設する場合も含む。「第1導電部」及び「第2導電部」は、それぞれ導電性部材からなる電子回路や接続端子等を意味し、絶縁基体の表面に形成した無電解めっきの層、電解めっきの層、あるいは金属箔等が該当する。「ろう付け層」とは、接合する母材より融点の低い金属または合金を溶融させて、母材間の隙間に満たして接合するろう材の層を意味し、融点が450℃以下のはんだ付け層の他、融点が450℃以上の硬ろう付け層も含む。   Further, “facing the connection member to the electronic circuit board” includes not only the case where the “electronic circuit board” is overlapped on both side surfaces of the “connection member” but also the case where the connection member is overlapped only on one side surface. The “insulation zone” is not limited to a part of the flat surface of the electronic circuit board, that is, a boundary surface that separates the second conductive parts adjacent to each other. This includes the case where an insulating partition wall is projected at the boundary of the part. “First conductive portion” and “second conductive portion” mean an electronic circuit or a connection terminal made of a conductive member, respectively, and an electroless plating layer, an electrolytic plating layer formed on the surface of an insulating substrate, or For example, metal foil. “Brazing layer” means a layer of brazing material that melts a metal or alloy having a melting point lower than that of the base material to be joined and fills the gap between the base materials, and is soldered with a melting point of 450 ° C. or less. In addition to the layer, a hard brazing layer having a melting point of 450 ° C. or higher is also included.

「相互に隣接する第1導電部」及び「相互に隣接する第2導電部」とは、絶縁域や絶縁隔壁等の絶縁部分を境界として、導電部が相互に並んでいることを意味し、導電部が電子回路のような通路状の場合には、間に絶縁部を挟んで、両通路が相互に電気的に分離されていることを意味する。また導電部が接続端子のようなスポット状の場合には、このスポット状の接続端子の周囲が、それぞれ絶縁部で囲まれて、相互に電気的に分離されていることを意味する。   “A first conductive portion adjacent to each other” and “a second conductive portion adjacent to each other” mean that the conductive portions are arranged side by side with an insulating portion such as an insulating region or an insulating partition, In the case where the conductive portion is in the form of a passage such as an electronic circuit, it means that both passages are electrically separated from each other with an insulating portion interposed therebetween. Further, when the conductive portion is spot-like like a connection terminal, it means that the periphery of the spot-like connection terminal is surrounded by an insulating portion and electrically isolated from each other.

「絶縁隔壁の頂部」とは、絶縁隔壁が突設された回路基板の表面から見て、絶縁隔壁の頂部を形成する稜線または稜面を意味する。「隙間なく当接」とは、当接部分に、絶縁隔壁の両側を貫通する通路が形成されていないことを意味する。   The “top part of the insulating partition wall” means a ridge line or a ridge surface that forms the top part of the insulating partition wall as viewed from the surface of the circuit board on which the insulating partition wall protrudes. “Abutting without a gap” means that a passage penetrating both sides of the insulating partition is not formed in the abutting portion.

接続部材の表面に設けた相互に隣接する第1導電部の境界部分に絶縁隔壁を突設し、この絶縁隔壁の頂部を、電子回路基板の表面の絶縁域、または電子回路基板に突設した第2の絶縁隔壁の頂部に隙間なく当接させて、相互に隣接するろう付け部分を隔離させることにより、ろう付けの際に「爆ぜ」が生じても、この絶縁隔壁に妨げられて、相互に対向するろう付け部分が短絡することが防止できる。   An insulating partition wall is projected at the boundary portion of the first conductive portions adjacent to each other provided on the surface of the connecting member, and the top of the insulating partition wall is projected on the insulating area of the surface of the electronic circuit board or the electronic circuit board. By abutting the top of the second insulating partition wall without any gap and isolating the brazing parts adjacent to each other, even if an “explosion” occurs during brazing, the insulating partition wall prevents the mutual insulation from occurring. It can prevent that the brazing part which opposes is short-circuited.

絶縁隔壁によって、「爆ぜ」による短絡が確実に防止できるので、隣接する導電部の相互間隔の幅を、導電部自体の幅より狭くすることができる。このため、電子回路等の集積密度を向上することができる。   Since the insulating partition can reliably prevent a short circuit due to “explosion”, the width of the interval between adjacent conductive portions can be made narrower than the width of the conductive portions themselves. For this reason, the integration density of an electronic circuit etc. can be improved.

図1〜図3を参照しつつ、本願発明による立体的な回路部品構造の構成を説明する。なお本願請求項1及び2に係る発明を実施するための最良の形態は、図3を参照しつつ段落「0030」〜「0031」において後述する。図1は、電子回路基板を相互に接続するための接続部材1を示しており、この接続部材には、絶縁基体11の取手状部分の全周にわたって、帯状の絶縁隔壁11aが、複数列突設してある。互いに隣接する帯状の絶縁隔壁11aの間には、全周にわたって、それぞれ導電部12が形成してある。図2に示すように、接続部材1の帯状の絶縁隔壁11aの上面は、凸状の円弧断面形状に形成してあり、相互に隣接するこの絶縁隔壁に挟まれた部分に、第1導電部12形成してある。なお帯状の絶縁隔壁11aは、矩形断面形状に形成してもよい。 The configuration of the three-dimensional circuit component structure according to the present invention will be described with reference to FIGS. The best mode for carrying out the invention according to claims 1 and 2 of the present application will be described later in paragraphs “0030” to “0031” with reference to FIG. FIG. 1 shows a connecting member 1 for connecting electronic circuit boards to each other. In this connecting member, strip-shaped insulating partition walls 11a are formed in a plurality of rows over the entire circumference of the handle-like portion of the insulating base 11. It is set up. Conductive portions 12 are respectively formed over the entire circumference between adjacent strip-shaped insulating partition walls 11a. As shown in FIG. 2, the upper surface of the strip-shaped insulating partition wall 11a of the connecting member 1 is formed in a convex arc cross-sectional shape, and the first conductive portion is formed between the adjacent insulating partition walls. 12 are formed. The strip-shaped insulating partition 11a may be formed in a rectangular cross section.

図2に示すように、接続部材1の上下両面には、それぞれ電子回路基板2、2が、接続されている。電子回路基板2は、絶縁基体21の平坦な表面に、第2導電部22が、複数列、相互に隣接して設けてあり、この第2導電部が、それぞれ対向する接続部材1に形成された第1導電部12と、はんだ付け層3によって電気的に接続されて、立体的な回路部品構造を形成している。   As shown in FIG. 2, electronic circuit boards 2 and 2 are connected to the upper and lower surfaces of the connection member 1, respectively. In the electronic circuit board 2, the second conductive portions 22 are provided adjacent to each other in a plurality of rows on the flat surface of the insulating base 21, and the second conductive portions are formed on the connecting members 1 that face each other. The first conductive part 12 and the soldering layer 3 are electrically connected to form a three-dimensional circuit component structure.

接続部材1の帯状の絶縁隔壁11aの、凸状の円弧断面形状に形成した頂部は、電子回路基板2を構成する絶縁基体21の平坦な表面であって、相互に隣接する第2導電部22相互の境界をなす絶縁域21aと、隙間なく当接している。   The top portion of the strip-shaped insulating partition 11a of the connecting member 1 formed in a convex arc cross-sectional shape is a flat surface of the insulating base 21 constituting the electronic circuit board 2 and is adjacent to the second conductive portion 22. It is in contact with the insulating region 21a forming the boundary without any gap.

次に接続部材1及び電子回路基板2の製造方法を説明する。接続部材1の絶縁基体11は、液晶ポリマー、耐熱性ポリアミド、あるいはポリフェニレンサルファイドなどの電気絶縁性の熱可塑性樹脂を、射出成形することにより成形する。例えば芳香族系ポリエステル液晶ポリマーとして、ポリプラスチック株式会社の商品名「ベクトラ」を使用する。次に、絶縁基体11の全表面を粗化(エッチング)処理する。このエッチング処理としては、苛性ソーダ、または苛性カリを所定濃度、例えば45重量%に溶解したアルカリ性水溶液を、所定温度、例えば50〜90℃に加熱し、絶縁基体11を所定時間、例えば30分浸漬する。このエッチング処理によって絶縁基体11の全表面が粗面化される。   Next, a method for manufacturing the connection member 1 and the electronic circuit board 2 will be described. The insulating base 11 of the connecting member 1 is formed by injection molding an electrically insulating thermoplastic resin such as liquid crystal polymer, heat resistant polyamide, or polyphenylene sulfide. For example, the trade name “Vectra” of Polyplastics Co., Ltd. is used as the aromatic polyester liquid crystal polymer. Next, the entire surface of the insulating substrate 11 is roughened (etched). As this etching process, caustic soda or an alkaline aqueous solution in which caustic potash is dissolved at a predetermined concentration, for example, 45% by weight is heated to a predetermined temperature, for example, 50 to 90 ° C., and the insulating substrate 11 is immersed for a predetermined time, for example, 30 minutes. By this etching process, the entire surface of the insulating substrate 11 is roughened.

次に、帯状の絶縁隔壁11aの凸状の円弧断面形状の表面と、この絶縁隔壁の両側壁面とを覆うように被覆材を射出成形する。この被覆材としては、例えばオキシアルキレン基含有ポリビニルアルコール系樹脂が該当する。なおオキシアルキレン基含有ポリビニルアルコール系樹脂としては、日本合成化学工業株式会社の商品名「エコマティAX」を使用することができる。   Next, a covering material is injection-molded so as to cover the convex arc-shaped cross-sectional surface of the strip-shaped insulating partition 11a and both side walls of the insulating partition. As this coating material, for example, an oxyalkylene group-containing polyvinyl alcohol resin is applicable. In addition, as an oxyalkylene group containing polyvinyl alcohol-type resin, the brand name "Ekomati AX" of Nippon Synthetic Chemical Industry Co., Ltd. can be used.

次に、絶縁基体11の露出している表面、すなわち帯状の絶縁隔壁11aの両側壁面に挟まれた表面に、パラジウム、金等の触媒を附与する。この触媒附与は、公知の手段を使用する。例えば、錫、パラジウム系の混合触媒液に、絶縁基体11を浸漬した後、塩酸、硫酸などの酸で活性化し、表面にパラジウムを析出させる。あるいは、塩化第一錫等の比較的還元作用が強い還元剤を、絶縁基体11の表面に吸着させて、金等の貴金属イオンを含む触媒溶液に浸漬し、表面に金を析出させる。なお液の温度は15〜23℃で5分間浸漬させればよい。   Next, a catalyst such as palladium or gold is applied to the exposed surface of the insulating substrate 11, that is, the surface sandwiched between both side walls of the strip-shaped insulating partition wall 11a. This catalyst application uses a known means. For example, the insulating substrate 11 is immersed in a mixed catalyst solution of tin and palladium, and then activated with an acid such as hydrochloric acid or sulfuric acid to deposit palladium on the surface. Alternatively, a reducing agent having a relatively strong reducing action such as stannous chloride is adsorbed on the surface of the insulating substrate 11 and immersed in a catalyst solution containing a noble metal ion such as gold to deposit gold on the surface. In addition, what is necessary is just to immerse the temperature of a liquid at 15-23 degreeC for 5 minutes.

さらに、触媒附与後の絶縁基体11を、60℃の湯中に10分間浸漬して、被覆材のエコマティAXを湯中に溶出させて除去する。次に、絶縁基体11の被覆材で覆われなかった露出表面、すなわち触媒が附与された帯状の絶縁隔壁11aの両側壁面に挟まれた部分に、無電解銅めっき層、または無電解ニッケルめっき層からなる第1導電部12を形成する。なおこのめっき層が形成される絶縁基体11の表面は、上述したように粗面化されているため、第1導電部12は、アンカー効果によって強固に接着する。最後に、熱処理を施して内部の水分を除去する。   Further, the insulating substrate 11 after the catalyst application is immersed in hot water at 60 ° C. for 10 minutes, and the ecomatic AX of the coating material is eluted and removed in the hot water. Next, an electroless copper plating layer or an electroless nickel plating is formed on the exposed surface of the insulating substrate 11 that is not covered with the covering material, that is, the portion sandwiched between both side walls of the strip-like insulating partition wall 11a provided with the catalyst. A first conductive portion 12 made of a layer is formed. Since the surface of the insulating base 11 on which the plating layer is formed is roughened as described above, the first conductive portion 12 is firmly bonded by the anchor effect. Finally, heat treatment is performed to remove moisture inside.

電子回路基板2も、上述した接続部材1と、ほぼ同様にして形成する。すなわち液晶ポリマー等の電気絶縁性の熱可塑性樹脂を用いて、電子回路基板2の絶縁基体21を射出成形して成形する。次に、絶縁基体21の全表面を粗化(エッチング)処理する。そして第2の導電部22を形成すべき表面部分を残して、絶縁基体21の全表面を、オキシアルキレン基含有ポリビニルアルコール系樹脂等の被覆剤を射出成形して覆う。   The electronic circuit board 2 is also formed in substantially the same manner as the connection member 1 described above. That is, the insulating base 21 of the electronic circuit board 2 is injection-molded using an electrically insulating thermoplastic resin such as a liquid crystal polymer. Next, the entire surface of the insulating base 21 is roughened (etched). Then, the entire surface of the insulating base 21 is covered by injection molding with a coating agent such as an oxyalkylene group-containing polyvinyl alcohol resin, leaving the surface portion where the second conductive portion 22 is to be formed.

次に、被覆剤で覆われていない絶縁基体21の露出している表面に、パラジウム、金等の触媒を附与し、その後被覆材を湯中に溶出させて除去する。そして触媒が附与された絶縁基体21の表面に、無電解銅めっき層、または無電解ニッケルめっき層からなる第2導電部22を形成する。最後に、熱処理を施して内部の水分を除去する。   Next, a catalyst such as palladium or gold is applied to the exposed surface of the insulating substrate 21 that is not covered with the coating agent, and then the coating material is eluted in hot water and removed. And the 2nd electroconductive part 22 which consists of an electroless copper plating layer or an electroless nickel plating layer is formed in the surface of the insulation base | substrate 21 to which the catalyst was provided. Finally, heat treatment is performed to remove moisture inside.

なお上述した無電解銅めっき、または無電解ニッケルめっきは、いずれも公知の無電解めっき手段を使用することができる。また第1導電部12、及び第2導電部22は、めっき層を形成する場合に限らず、導電性薄膜を付着したり、金属端子を嵌合さたりしてもよい。さらに無電解めっき層に重ねて、更に電解めっき層を形成してもよい。   In addition, the electroless copper plating or the electroless nickel plating mentioned above can use any known electroless plating means. Moreover, the 1st electroconductive part 12 and the 2nd electroconductive part 22 may adhere not only when forming a plating layer but a conductive thin film, or a metal terminal may be fitted. Further, an electrolytic plating layer may be formed on the electroless plating layer.

そこで次に図2を参照しつつ、このようにして形成した接続部材1と、電子回路基板2とを、相互に電気的に接続する方法を説明する。まず接続部材1の第1導電部12の表面上であって、はんだ付けする部分に、はんだを、所定の量だけ盛り付ける。なお盛り付けるはんだ量は、第1導電部12の表面積等を考慮して、適切な量とする。次に接続部材1の上下面に、電子回路基板2、2を、それぞれ第1導電部12と第2導電部22とのはんだ付け部分が対向するように重ね合わせ、所定のはんだ付け温度に加熱する。はんだは、溶融して、第1導電部12と第2導電部22との間にはんだ付け層3を形成して、両者を電気的に接続する。   A method for electrically connecting the connection member 1 thus formed and the electronic circuit board 2 to each other will now be described with reference to FIG. First, on the surface of the first conductive portion 12 of the connection member 1, a predetermined amount of solder is placed on the portion to be soldered. The amount of solder to be deposited is set to an appropriate amount in consideration of the surface area of the first conductive portion 12 and the like. Next, the electronic circuit boards 2 and 2 are superimposed on the upper and lower surfaces of the connection member 1 so that the soldering portions of the first conductive portion 12 and the second conductive portion 22 face each other, and heated to a predetermined soldering temperature. To do. The solder is melted to form a soldering layer 3 between the first conductive portion 12 and the second conductive portion 22, and the two are electrically connected.

上述したように、接続部材1の絶縁隔壁11aの凸状の円弧断面形状に形成した上面、すなわち頂部が、電子回路基板2の表面であって、相互に隣接する第2導電部22の境界をなす絶縁域21aと隙間なく当接しているため、相互に隣接するはんだ付け層3は、この絶縁隔壁によって相互に隔離される。したがって、はんだ付け層3が形成される際に、例え「爆ぜ」が発生しても、相互に隣接するはんだ付け層に、電気的な短絡が生じることはない。   As described above, the upper surface, i.e., the top portion, of the insulating partition wall 11a of the connecting member 1 formed in the convex arc cross-sectional shape is the surface of the electronic circuit board 2, and the boundary between the second conductive portions 22 adjacent to each other. Since it is in contact with the insulating region 21a formed without any gap, the soldering layers 3 adjacent to each other are isolated from each other by this insulating partition. Therefore, even if “explosion” occurs when the soldering layer 3 is formed, an electrical short circuit does not occur in the soldering layers adjacent to each other.

図3に他の実施の形態を示す。なおこの他の実施の形態においては、理解を容易にするため、上述した実施の形態と同等の箇所の符号は、一律100を加えた番号にしている。さてこの他の実施の形態では、上述した電子回路基板2に設けた、平坦な絶縁域11aの代わりに、第2の絶縁隔壁121aが突設してある。すなわち電子回路基板102の絶縁基体121の表面には、帯状の第2の絶縁隔壁121aが、複数列突設してある。第2の絶縁隔壁111aの頂部も、凸状の円弧断面形状に形成してあり、相互に隣接するこの絶縁隔壁に挟まれた部分に、第2導電部122が形成してある。なお帯状の絶縁隔壁121aは、矩形断面形状に形成してもよい。一方電子回路基板102同士を接続する接続部材101は、図1、2において上述した接続部材1と同等のものになっている。また電子回路基板102の製造方法も、上述した接続部材1と同等の方法によって製造する。   FIG. 3 shows another embodiment. In other embodiments, in order to facilitate understanding, the same reference numerals as those in the above-described embodiments are given the same number plus 100. In this other embodiment, a second insulating partition wall 121a protrudes in place of the flat insulating region 11a provided on the electronic circuit board 2 described above. That is, on the surface of the insulating base 121 of the electronic circuit board 102, a plurality of rows of strip-shaped second insulating partition walls 121a are projected. The top of the second insulating partition 111a is also formed in a convex arc cross-sectional shape, and a second conductive portion 122 is formed in a portion sandwiched between the insulating partitions adjacent to each other. Note that the strip-shaped insulating partition wall 121a may be formed in a rectangular cross-sectional shape. On the other hand, the connecting member 101 that connects the electronic circuit boards 102 is equivalent to the connecting member 1 described above with reference to FIGS. The electronic circuit board 102 is also manufactured by a method equivalent to that of the connection member 1 described above.

このように接続部材101と電子回路基板102とを形成し、両者を重ねて接続するときに、この接続部材に突設した絶縁隔壁111aの頂部と、この電子回路基板に突設した第2の絶縁隔壁121aの頂部とを、隙間なく当接するように構成することによって、相互に隣接するはんだ付け層103は、この絶縁隔壁と第2の絶縁隔壁とによって相互に隔離される。したがって、はんだ付け層103が形成される際に、例え「爆ぜ」が発生しても、相互に隣接するはんだ付け層に、電気的な短絡が生じることはない。   Thus, when the connection member 101 and the electronic circuit board 102 are formed and the two are overlapped and connected, the top of the insulating partition wall 111a protruding from the connection member and the second protrusion protruding from the electronic circuit board are provided. By configuring the top of the insulating partition wall 121a so as to contact with no gap, the soldering layers 103 adjacent to each other are separated from each other by the insulating partition wall and the second insulating partition wall. Therefore, even if “explosion” occurs when the soldering layer 103 is formed, an electrical short circuit does not occur between the soldering layers adjacent to each other.

本発明による立体的な回路部品構造は、ろう付けする際の短絡を回避して、歩留まりを少なくすると共に、使用中の短絡故障の発生を防止できるため、電子機器等に関する産業に広く利用可能である。   The three-dimensional circuit component structure according to the present invention avoids a short circuit during brazing, reduces the yield, and prevents the occurrence of a short circuit failure during use. Therefore, the three-dimensional circuit component structure can be widely used in industries related to electronic devices and the like. is there.

第1の基体の一部斜視図である。It is a partial perspective view of the 1st base. 立体的な回路部品構造の一部断面図である。It is a partial cross section figure of a three-dimensional circuit component structure. 他の立体的な回路部品構造の一部断面図である。It is a partial cross section figure of another three-dimensional circuit component structure. 従来例による第1の基体の一部斜視図である。It is a partial perspective view of the 1st base | substrate by a prior art example. 従来例による立体的な回路部品構造の一部断面図である。It is a partial sectional view of a three-dimensional circuit component structure according to a conventional example. 従来例による立体的な回路部品構造における短絡を示す説明図である。It is explanatory drawing which shows the short circuit in the three-dimensional circuit component structure by a prior art example.

符号の説明Explanation of symbols

1、101、201 接続部材
11、111、211 絶縁基体
11a、111a 絶縁隔壁
12、112、212 第1導電部
2、102、202 電子回路基板
21、121、212 絶縁基体
21a、121a 絶縁域、第2の絶縁隔壁
22、122、222 第2導電部
3、103、203 はんだ付け層(ろう付け層)
1, 101, 201 Connecting member 11, 111, 211 Insulating substrate 11a, 111a Insulating partition 12, 112, 212 First conductive part 2, 102, 202 Electronic circuit board 21, 121, 212 Insulating substrate 21a, 121a Insulating region, first Insulating partition wall 2, 122, 222 Second conductive part 3, 103, 203 Soldering layer (brazing layer)

Claims (2)

電子回路基板と接続部材とを備え、
上記接続部材の上記電子回路基板と対向する表面には、絶縁隔壁が突設してあると共に、この絶縁隔壁を境界として相互に隣接する第1導電部が形成してあり、
上記電子回路基板の表面には、絶縁域を境界として相互に隣接する第2導電部が形成してあり、
上記第1導電部と第2導電部とは、ろう付け層を介して電気的に接続されており、
上記絶縁域は、上記電子回路基板の表面に突設した第2の絶縁隔壁からなり、
上記絶縁隔壁の頂部は、上記第2の絶縁隔壁の頂部と隙間なく当接して、相互に隣接する上記ろう付け層を隔離している
ことを特徴とする立体的な回路部品構造。
An electronic circuit board and a connection member;
On the surface of the connection member facing the electronic circuit board, an insulating partition wall protrudes, and first conductive portions adjacent to each other with the insulating partition wall as a boundary are formed.
On the surface of the electronic circuit board, second conductive portions adjacent to each other with an insulating region as a boundary are formed,
The first conductive part and the second conductive part are electrically connected via a brazing layer,
The insulating region comprises a second insulating partition wall protruding from the surface of the electronic circuit board,
A three-dimensional circuit component structure characterized in that a top portion of the insulating partition wall is in contact with a top portion of the second insulating partition wall without any gap, thereby isolating the brazing layers adjacent to each other .
請求項1において、上記第1導電部と絶縁隔壁との境界面に直交する方向において、この第1導電部の幅は、この絶縁隔壁の幅より広い
ことを特徴とする立体的な回路部品構造。
2. The three-dimensional circuit component structure according to claim 1, wherein the width of the first conductive portion is wider than the width of the insulating partition in a direction perpendicular to the boundary surface between the first conductive portion and the insulating partition. .
JP2007261484A 2007-10-05 2007-10-05 Three-dimensional circuit component structure Expired - Fee Related JP5006746B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007261484A JP5006746B2 (en) 2007-10-05 2007-10-05 Three-dimensional circuit component structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007261484A JP5006746B2 (en) 2007-10-05 2007-10-05 Three-dimensional circuit component structure

Publications (2)

Publication Number Publication Date
JP2009094174A JP2009094174A (en) 2009-04-30
JP5006746B2 true JP5006746B2 (en) 2012-08-22

Family

ID=40665896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007261484A Expired - Fee Related JP5006746B2 (en) 2007-10-05 2007-10-05 Three-dimensional circuit component structure

Country Status (1)

Country Link
JP (1) JP5006746B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9829915B2 (en) * 2014-06-18 2017-11-28 Intel Corporation Modular printed circuit board

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4619807B2 (en) * 2004-01-30 2011-01-26 パナソニック株式会社 Component built-in module and electronic device equipped with component built-in module
JP2006040870A (en) * 2004-02-20 2006-02-09 Matsushita Electric Ind Co Ltd Connection member, mounting body, and manufacturing method thereof
JP4393400B2 (en) * 2005-02-25 2010-01-06 パナソニック株式会社 Three-dimensional electronic circuit device and its relay substrate

Also Published As

Publication number Publication date
JP2009094174A (en) 2009-04-30

Similar Documents

Publication Publication Date Title
JP5084509B2 (en) Interconnect element for interconnecting terminals exposed on the outer surface of an integrated circuit chip and method for manufacturing the same, multilayer interconnect substrate including a plurality of interconnect elements, method for manufacturing the same, and method for manufacturing multilayer interconnect substrate
CN101315917B (en) Wiring board and its fabricating method
KR100375861B1 (en) Module Substrate and Method of Producing the Same
US9437352B2 (en) Resistor and structure for mounting same
WO2004098249A1 (en) Connection structure of printed wiring board
US7712210B2 (en) Method of providing a printed circuit board with an edge connection portion
US11335508B2 (en) Electronic device
CN101455130B (en) Wiring board
CN101316476A (en) Wiring circuit board
JP5006746B2 (en) Three-dimensional circuit component structure
JP2757748B2 (en) Printed wiring board
KR101951732B1 (en) Conductive contactor for substrate surface mount and preparing method for the same
CN104604341B (en) Circuit board and its manufacture method
JP7136672B2 (en) Wiring board and electronic device
JP2007012483A (en) Male connector
US20250142737A1 (en) Circuit board assembly and manufacturing method thereof
KR100850457B1 (en) The substrate of which upper side terminal and lower side terminal are connected each other, and the method for making it
JP3879394B2 (en) Circuit board connection structure
JPS6126171B2 (en)
KR100507625B1 (en) Surface mountable electric device using cream solder and method of manufacturing the same
JP4564441B2 (en) Circuit board
CN115486208A (en) FPCB and method for manufacturing the FPCB
JP2000299550A (en) Wiring board and method of manufacturing the same
JP2004172360A (en) Compound substrate device
JPH06326475A (en) Multilayer circuit board with protruding contact and its connection method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090709

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110720

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110721

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20111018

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111121

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20111219

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120307

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120405

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120501

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120525

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150601

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees