JP5012191B2 - 多層配線板およびその製造方法並びにプローブ装置 - Google Patents
多層配線板およびその製造方法並びにプローブ装置 Download PDFInfo
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- JP5012191B2 JP5012191B2 JP2007128292A JP2007128292A JP5012191B2 JP 5012191 B2 JP5012191 B2 JP 5012191B2 JP 2007128292 A JP2007128292 A JP 2007128292A JP 2007128292 A JP2007128292 A JP 2007128292A JP 5012191 B2 JP5012191 B2 JP 5012191B2
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors
- H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors incorporating printed resistors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/06766—Input circuits therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07342—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0302—Properties and characteristics in general
- H05K2201/0317—Thin film conductor layer; Thin film passive component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/025—Abrading, e.g. grinding or sand blasting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1453—Applying the circuit pattern before another process, e.g. before filling of vias with conductive paste, before making printed resistors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0023—Etching of the substrate by chemical or physical means by exposure and development of a photosensitive insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/467—Adding a circuit layer by thin film methods
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49082—Resistor making
- Y10T29/49099—Coating resistive material on a base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
12 多層配線板
14 絶縁基板
16 多層配線層
18 多層配線層の絶縁層
20 多層配線層の導電層
32b ダミー層
34 ダミー層の平坦面
36 絶縁層
40 抵抗体層(配線下地領域)
40a 抵抗体(抵抗体領域)
44a 絶縁膜(封止膜)
50a、50b 抵抗体の配線路
52 プローブ
52a プローブの針先
Claims (9)
- 表面に凹凸が形成された多層配線層を有する多層配線板の前記表面の所望領域に平坦面を形成し、該平坦面上に電気抵抗材料を堆積して抵抗体を形成する、多層配線板の製造方法であって、
前記所望領域内の前記凹凸面を埋め込むためのダミー層であって前記所望領域内の前記凹凸面を埋め込むのに充分な厚さ寸法に前記ダミー層のための材料を堆積することにより前記ダミー層を形成し、その後平面研磨によって前記ダミー層の表面を平坦化することにより前記平坦面を形成し、
前記ダミー層は導電材料からなり、フォトレジストによって前記平坦面を作る領域を露出するレジストマスクを形成し、該レジストマスクから露出する領域に電気メッキ法によってダミー層のための前記導電材料が堆積されて前記凹凸を埋め込むための前記ダミー層が形成され、該ダミー層の少なくとも一部が配線路の一部として使用される、多層配線板の製造方法。 - 前記多層配線層上の配線を形成するための導電材料の堆積と同時的に前記ダミー層のための導電材料が堆積される、請求項1に記載の製造方法。
- 前記ダミー層上に電気絶縁材料からなる絶縁層が形成され、該絶縁層上に前記電気抵抗材料が堆積される、請求項2に記載の製造方法。
- 表面に凹凸が形成された多層配線層と、該多層配線層の前記表面の所望領域に、該領域内の前記凹凸を埋め込みかつほぼ平坦な表面を有するダミー層と、該ダミー層上および該ダミー層をはみ出す領域に堆積された電気抵抗材料で形成される抵抗材料層と、前記電気抵抗体材料上に堆積され導電材料からなる配線であって前記ダミー層からはみ出す領域から前記ダミー層の前記平坦面領域の一部に達する配線とを含み、前記抵抗材料層の前記配線が達していない領域で抵抗体が形成されており、
前記ダミー層は前記多層配線板の前記表面上の配線を形成するための導電材料と同層で堆積された導電材料からなり、
前記ダミー層の少なくとも一部が前記多層配線層の配線路の一部を構成している、多層配線板。 - 前記ダミー層は前記多層配線板の前記表面上の配線を形成するための導電材料と同層で堆積された導電材料からなる、請求項4に記載の多層配線板。
- 前記ダミー層上には、該ダミー層を覆う絶縁層が形成され、該絶縁層を介して前記抵抗体が前記ダミー層上に形成されている、請求項5に記載の多層配線板。
- 前記ダミー層は、該ダミー層下の他の導電層に電気的に接続された配線として機能する、請求項6に記載の多層配線板。
- 多層配線層を有する多層配線板からなるプローブ基板と、該プローブ基板の前記多層配線層の表面に設けられ、該多層配線層の導電路に接続される複数のプローブと、前記多層配線層の前記導電路に接続される抵抗体とを含むプローブ装置であって、前記多層配線層の前記表面には、凹凸が形成されており、前記多層配線層の前記表面の所望領域には、該領域内の前記凹凸面を埋め込むように平坦な表面を有するダミー層が形成されており、該ダミー層上に前記抵抗体が形成されており、
前記ダミー層は、前記プローブが固着される前記多層配線板のパッド部と同層で前記多層配線層上に堆積された導電材料層からなり、前記ダミー層上には、該ダミー層を覆う絶縁層が形成され、該絶縁層を介して前記抵抗体が前記ダミー層上に形成されており、
前記ダミー層の少なくとも一部は前記多層配線層の配線路の一部を構成している、プローブ装置。 - 前記ダミー層上および該ダミー層をはみ出す領域には電気抵抗材料層が形成されており、該電気抵抗材料層上には、前記電気抵抗体材料上に堆積された導電材料からなる配線であって前記ダミー層からはみ出す領域から前記ダミー層の前記平坦面領域の一部に達する配線が形成され、前記抵抗材料層の前記配線が達していない領域で抵抗体が形成されていることを特徴とする、請求項8に記載のプローブ装置。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007128292A JP5012191B2 (ja) | 2007-05-14 | 2007-05-14 | 多層配線板およびその製造方法並びにプローブ装置 |
| US12/099,691 US7735221B2 (en) | 2007-05-14 | 2008-04-08 | Method for manufacturing a multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007128292A JP5012191B2 (ja) | 2007-05-14 | 2007-05-14 | 多層配線板およびその製造方法並びにプローブ装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2008283131A JP2008283131A (ja) | 2008-11-20 |
| JP5012191B2 true JP5012191B2 (ja) | 2012-08-29 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007128292A Expired - Fee Related JP5012191B2 (ja) | 2007-05-14 | 2007-05-14 | 多層配線板およびその製造方法並びにプローブ装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7735221B2 (ja) |
| JP (1) | JP5012191B2 (ja) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110089967A1 (en) * | 2008-04-21 | 2011-04-21 | Sanghee Kim | Mems probe card and manufacturing method thereof |
| JP2012502274A (ja) * | 2008-09-05 | 2012-01-26 | トップ・エンジニアリング・カンパニー・リミテッド | Memsプローブ用カード及びその製造方法 |
| US20100257495A1 (en) * | 2009-04-06 | 2010-10-07 | Chan-Liang Wu | 3D-IC Verification Method |
| JP5426494B2 (ja) * | 2010-07-20 | 2014-02-26 | 日本電子材料株式会社 | プローブカードの製造方法 |
| US8815707B2 (en) | 2012-06-21 | 2014-08-26 | Board of Trustess of the Leland Stanford Junior University | Environmentally-assisted technique for transferring devices onto non-conventional substrates |
| JP6092572B2 (ja) * | 2012-10-30 | 2017-03-08 | 株式会社日本マイクロニクス | 多層配線基板及びこれを用いたプローブカード |
| JP6110113B2 (ja) * | 2012-11-20 | 2017-04-05 | 株式会社日本マイクロニクス | 多層配線基板、及びその製造方法 |
| EP3075005A1 (en) * | 2013-11-25 | 2016-10-05 | The Board of Trustees of The Leland Stanford Junior University | Laser liftoff of epitaxial thin film structures |
| JP6652443B2 (ja) | 2016-05-06 | 2020-02-26 | 株式会社日本マイクロニクス | 多層配線基板及びこれを用いたプローブカード |
| TWI663407B (zh) * | 2018-06-06 | 2019-06-21 | 中華精測科技股份有限公司 | 探針卡裝置及其立體式信號轉接結構 |
| KR102729106B1 (ko) * | 2020-11-17 | 2024-11-13 | 재팬 일렉트로닉 메트리얼스 코오포레이숀 | 프로브 카드용 다층 배선 기판 및 프로브 카드 |
| WO2026022920A1 (ja) * | 2024-07-23 | 2026-01-29 | 日本電子材料株式会社 | プローブ |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4870746A (en) * | 1988-11-07 | 1989-10-03 | Litton Systems, Inc. | Method of making a multilayer printed circuit board having screened-on resistors |
| JP3255112B2 (ja) | 1998-06-17 | 2002-02-12 | 日本電気株式会社 | 抵抗内蔵型の配線基板及びその製造方法 |
| JP2000022331A (ja) * | 1998-07-01 | 2000-01-21 | Sumitomo Metal Electronics Devices Inc | ビルドアップ多層基板の配線パターン形成方法 |
| JP2003021668A (ja) * | 1999-11-18 | 2003-01-24 | Ibiden Co Ltd | 検査装置およびプローブカード |
| JP2002124639A (ja) * | 2000-08-09 | 2002-04-26 | Seiko Instruments Inc | 半導体装置及びその製造方法 |
| JP2002374069A (ja) * | 2001-06-13 | 2002-12-26 | Sony Corp | 高周波モジュール装置及びその製造方法 |
| JP2003101222A (ja) * | 2001-09-21 | 2003-04-04 | Sony Corp | 薄膜回路基板装置及びその製造方法 |
| JP2005017121A (ja) | 2003-06-26 | 2005-01-20 | Micronics Japan Co Ltd | プローブカード |
| JP4311157B2 (ja) * | 2003-10-10 | 2009-08-12 | 凸版印刷株式会社 | 半導体装置用基板の製造方法 |
| JP2007158017A (ja) * | 2005-12-05 | 2007-06-21 | Mitsui Mining & Smelting Co Ltd | 配線基板およびその製造方法 |
-
2007
- 2007-05-14 JP JP2007128292A patent/JP5012191B2/ja not_active Expired - Fee Related
-
2008
- 2008-04-08 US US12/099,691 patent/US7735221B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US7735221B2 (en) | 2010-06-15 |
| US20080315901A1 (en) | 2008-12-25 |
| JP2008283131A (ja) | 2008-11-20 |
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