JP5013966B2 - Arithmetic processing unit - Google Patents

Description

  The present invention relates to an arithmetic processing apparatus in which a control process is executed by a controller that drives a device.

  In a hardware arithmetic unit (dedicated arithmetic circuit or processor) that executes control processing on a controller, it is required to operate the circuit at a low clock frequency because of problems of heat generation and noise. For this reason, an arithmetic circuit specialized in processing contents is realized, in which a plurality of arithmetic circuits capable of performing various arithmetic processes in one clock cycle are realized, and the plurality of arithmetic circuits are driven in a plurality of clock cycles to complete an entire desired arithmetic operation. It needs to be realized.

  When an arithmetic circuit specialized for such processing contents is used, if the processing contents assumed when the arithmetic circuit is mounted are corrected, it is difficult to execute the processing contents. For this reason, in the conventional arithmetic processing unit, an arithmetic circuit capable of changing the processing content to be executed is used, and in order to improve the arithmetic performance even at a low operating frequency without increasing the operating frequency, ALU (arithmetic logic unit), BRL (Barrel shifter) and a data path fixedly connected by a multiplexer are configured, and configuration data (opcode data) to ALU, BRL, and multiplexer is set, so that an operation data path specialized for processing contents is configured. (For example, refer to Patent Document 1).

JP 2004-54335 A

However, in the conventional arithmetic processing unit, a multiplexer that switches input / output to an arithmetic circuit such as arithmetic operation, logical operation, and shift by a selection signal is widely used as a precaution for assuming that the processing content is corrected. It becomes the form to do. For this reason, a longer delay time and a longer number of execution cycles are required for execution of operations compared to the case of using a dedicated operation circuit specialized for processing contents that do not assume input / output switching to each operation circuit. In addition, there has been a problem that the operation itself cannot be executed with respect to the operation circuit that is not originally connected in the operation device.
On the other hand, when a dedicated arithmetic circuit that does not assume switching of an input / output path is employed, it is difficult to cope with correction of processing content that occurs after the dedicated arithmetic circuit is mounted.

  The present invention has been made in order to solve the above-described problems, and provides an arithmetic processing device that enables high-speed execution of processing and prevents deterioration in execution time when processing content is corrected. The purpose is to get.

The arithmetic processing device according to the present invention has arithmetic means for performing arithmetic operation, logical operation, shift operation, and general arithmetic processing means for executing each operation by issuing an instruction code defined for each arithmetic means And a special arithmetic processing means for executing a specific arithmetic processing in a predetermined clock cycle, and issuing an instruction code defined for the specific arithmetic processing in the special arithmetic processing means. Special operation control means for controlling execution and suspension, and the number of clock cycles at which the special operation processing means is suspended is set to an arbitrary value using a specific instruction code .

The arithmetic processing apparatus of the present invention includes arithmetic operation means for performing arithmetic operation, logical operation, and shift operation, and general arithmetic processing means for executing each operation by issuing an instruction code defined for each operation means; , Special arithmetic processing means for executing specific arithmetic processing in a predetermined clock cycle, and execution of arithmetic processing in the special arithmetic processing means based on the issuance of an instruction code defined for the specific arithmetic processing And special arithmetic control means for controlling suspension, and the number of clock cycles in which the special arithmetic processing means pauses is set to an arbitrary value using a specific instruction code , enabling high-speed processing execution In addition, it is possible to prevent the execution time from being deteriorated when the processing content is corrected.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing an arithmetic processing apparatus according to Embodiment 1 of the present invention. Prior to this description, a general arithmetic processing apparatus will be described.

  A general microprocessor is configured to perform arithmetic operations by fetching data called instruction codes by the processor, interpreting them, and executing operations defined for the respective instruction codes. The instruction code is placed on the instruction memory, and an address is assigned to each instruction code on the instruction memory, the instruction codes are read in the ascending order of addresses (fetch operation), and the instruction codes are interpreted ( (Decoding operation), the operation indicated by the instruction code is executed (arithmetic operation). In addition, as the instruction code, fetching of data from the data memory (load operation) and writing of data (store operation) are also defined. When these instruction codes are issued, the data memory is accessed, The result is written to a register or data memory.

FIG. 2 is a diagram showing a pipeline stage of a general microprocessor.
A general microprocessor is composed of functional blocks (called “stages”) that operate independently to read, interpret, and execute instruction codes. These are efficiently operated by pipeline operation. It is possible to execute the process. The microprocessor shown in FIG. 2 includes an instruction fetch (IF) 1, an instruction decode (D) 2, an instruction execution (EX) 3, a memory access (MA) 4, a result store (S) 5, an instruction memory 6, and a register block 7. A data memory 8 is provided.

These functional blocks generally have the following functions.
Instruction memory 6: Memory in which instruction codes are stored.
Register block 7: a data storage area temporarily used for execution of operations.
Data memory 8: A memory for storing operation input data and output data.
Instruction fetch 1: a stage for fetching an instruction from the instruction memory 6.
Instruction decode 2: A stage for decoding an instruction. In the case of an operation instruction, the availability of the source and destination registers is checked, and if it is available, it is read. If not available, wait until it becomes available.
Instruction execution 3: Calculation execution.
Memory access 4: In the case of a load / store instruction, data memory access is performed. This stage does nothing for arithmetic instructions.
Result store 5: Store results and post-process instructions.

In the instruction execution 3 (EX stage), an arithmetic circuit necessary for executing an operation is mounted. As such an arithmetic circuit, for example,
Arithmetic operation circuit (arithmetic addition, arithmetic subtraction, arithmetic multiplication, arithmetic division, arithmetic shift operation)
Logical operation circuit (logical sum, logical product, exclusive logical sum, logical shift operation)
Etc. exist.
In general, a plurality of registers exist on the register block 7. For the sake of explanation, it is assumed here that there are 32 registers from r0 to r31. In addition, these registers are generally used in operations and the like, and are generally called “general-purpose registers”.
As these blocks operate in parallel, the microprocessor executes operations. The operation execution operation will be described based on the instruction code.

FIG. 3 is an explanatory diagram of instruction codes set in the instruction memory 6.
FIG. 4 is an explanatory diagram of such an instruction code.
These instruction codes are general instruction codes adopted in a processor called a MIPS (Microprocessor without Interlocked Pipeline Stages) processor. Each instruction code is stored in the instruction memory 6 at a position indicated by an instruction address. In FIG. 4, GPR is a general purpose register.

As the processing flow of the processor that operates by interpreting the instruction code shown in FIG. 3, the instruction code [LW r8, 0 (r1)] at the instruction address 0000 is first read and executed. In this instruction code, an address value on the data memory 8 in which the offset value 0 is added to the address on the data memory 8 held on the general-purpose register r1 is generated and held at the address on the data memory 8. The stored 4-byte data is stored in the general-purpose register r8.
Next, the instruction code [LW r9, 4 (r1)] at address 0004 is executed. By executing this instruction code, 4-byte data in the data memory 8 having the address value (r1 + 4) is stored in the general-purpose register r9.

Next, the instruction code [MUL r10, r8, r9] at the instruction address 0008 is executed, and the result of arithmetic multiplication of the values stored in the general-purpose register r8 and the general-purpose register r9 is stored in the general-purpose register r10.
Next, the instruction code [LW r11,8 (r1)] of the instruction address 000c is executed, and the data on the data memory 8 having the address value (r1 + 8) is stored in the general-purpose register r11.
Next, [ADD r12, r10, r11] at the instruction address 0010 is executed, and the result of arithmetic addition of the values stored in the general-purpose register r10 and the general-purpose register r11 is stored in the general-purpose register r12.

Next, [LW r13, 12 (r1)] of the instruction address 0014 is executed, and the data in the data memory having the address value (r1 + 12) is stored in the general-purpose register r13.
Next, [SUB r14, r13, r12] at the instruction address 0018 is executed, arithmetic subtraction (r13-r12) is calculated from the values stored in the general-purpose register r13 and the general-purpose register r12, and the calculation result is the general-purpose value. It is stored on the register r14.
Next, [SW r14, 16 (r1)] of the instruction address 001c is executed.
By executing this instruction code, the value of the general-purpose register r14 is stored in the area on the data memory 8 indicated by the address value (r1 + 16).
In this way, the general processor is configured so that the processing is executed on the processor based on the instruction code on the instruction memory 6 and the result is stored in the data memory 8 continuously. Has been.

In addition, the arithmetic circuit mounted in the instruction execution 3 (EX stage) in the processor for executing each operation is generally executed in one cycle of the operation clock that is a reference of the processor operation. Although the delay time of each arithmetic circuit is set, if the delay time is one cycle or more, the arithmetic circuit is such that the arithmetic is executed in a plurality of cycles.
For example, in a certain processor, in an arithmetic circuit that performs 64-bit floating point arithmetic in the IEEE 754 standard, a multiplication circuit (64-bit floating point multiplication) outputs a result in five cycles, and an addition circuit (64-bit floating point multiplication) outputs a result in 4 cycles.

For example, after performing 64-bit floating point multiplication, performing 64-bit floating point addition,
D = A × B + C
When the above calculation is performed, if the above multiplication and addition are used, the calculation result can be acquired in a total of 9 cycles of 5 cycles + 4 cycles. Such an operation that adds to the result of multiplication is common and is often referred to as “product-sum operation” and is often used. Many processors are equipped with arithmetic circuits specialized for product-sum operations for this operation. For example, in a processor that refers to the number of cycles as described above, the product-sum operation circuit can acquire an operation result in five cycles. It is like that.
As described above, when it is desired to execute a specific process at high speed, it is possible to complete the operation in a shorter number of cycles by developing an operation circuit dedicated to the operation and mounting it in the processor. For this reason, in a processor that mainly executes specific processing, a processing content-specific arithmetic circuit may be mounted so that arithmetic processing specialized for the processing content can be executed as fast as possible (with a short number of execution cycles). Many.

As an example of such an operation, for example, a complete list 1:
d = (a × b) + ch = ((d> e)? e: ((d <f)? f: d)) >> g
k = (h + i) >> j
In the case where it is desired to execute the arithmetic processing as a specific processing at high speed, an arithmetic circuit that directly realizes the entire arithmetic data flow is considered. By dividing the delay time of the arithmetic circuit by the clock cycle time, the arithmetic circuit is realized as an arithmetic circuit operating in a plurality of cycles and mounted on the processor.
In the above process,
X is arithmetic multiplication + is arithmetic addition (A> B) is a comparison operation (true if A is greater than B, false otherwise)
(C <D) is a comparison operation (true if C is less than D, false otherwise)
((X)? Y: Z) is a selection operation (if X is true, Y is returned; if false, Z is returned)
>> indicates arithmetic right shift.

FIG. 5 is an explanatory diagram showing a calculation data flow expressing this calculation.
In the figure, blocks indicated by a to j indicate input data necessary for executing an operation, and a block indicated by k indicates output data of an operation result. Also, the portions surrounded by circles in the figure indicate circuits that perform operations described therein. Further, the block described as SEL indicates a so-called selector for selecting data, and if the value is compared with the true / false value acquired in the portion described as “B” which is an input to the SEL block, If true (1), the value of the input described as “T” is output as a result, and if false (0), the value of the input described as “F” is output as a result. It corresponds to the selection operation being processed.

  When the operation data flow shown in the list 1 is executed with an instruction code for performing a general operation, all necessary instruction codes are as shown in FIG. The description of each instruction code in FIG. 6 is as described in FIG. In the description of FIG. 6, for example, [b], [a], etc. in the LW instruction and the SW instruction indicate addresses on the data memory in which the data b and a are stored, respectively. The general-purpose register r0 is assumed to have a value of 0. In this way, when processing is executed with a general instruction code, 19 steps are required, and a lot of calculation time (number of execution cycles) is required. Therefore, in the present invention, a circuit that performs a plurality of steps simultaneously is provided, and arithmetic processing is executed using this circuit.

FIG. 7 is an explanatory diagram showing a division example of the calculation data flow shown in FIG.
That is, FIG. 7 shows that the special arithmetic circuit is configured in a plurality of cycles by dividing the delay time of the arithmetic circuit by the clock time (reciprocal of the clock frequency) from the arithmetic data flow of FIG. In FIG. 7, the sub data flow 71, the sub data flow 72, and the sub data flow 73 result from dividing the delay time of the original arithmetic data flow by the clock time, resulting in three arithmetic circuits. The circuit part is shown.

If such a special processing circuit is installed in the processor, the processing can be completed in a very short time compared to the case where the same processing content is executed by a general instruction code.
However, there is a problem that processing cannot be executed by the same arithmetic circuit when the processing contents are corrected after the arithmetic circuit specialized for the processing contents is mounted inside the processor. If the implemented circuit becomes completely unusable, it will be necessary to perform an operation using the above-mentioned general instruction code in order to execute the processing contents, so the processing time will be lengthened. .
As an example of a measure to prevent the problem, it is conceivable to mount the circuit in anticipation of future correction contents of the processing contents, but it is difficult to predict what correction contents will occur, so it is difficult to predict the circuit to be realized. There is a problem that the assumption is difficult, and there is a problem that if the circuit has general versatility, the delay time becomes long and the calculation time of the circuit is adversely affected. Furthermore, since the circuit scale is increased, there is a problem that the implementation cost of the processor is increased.

  Therefore, in the present invention, in order to avoid these problems, the special arithmetic processing means that is executed in a plurality of cycles, which is specialized for the application, is implemented, and an arbitrary specified as the special arithmetic control means for controlling the special arithmetic processing means. In addition to having a function to stop the computation in the execution cycle, and by issuing a general processor instruction code, the intermediate results of the special-purpose processing means specialized for the application are corrected and the special arithmetic processing control is performed again. The function for resuming the execution of the special processing means for application specific is defined for the means. The whole image is shown in FIG. 1 and will be described below with reference to FIG.

In FIG. 1, a special arithmetic circuit 9 is an arithmetic circuit for executing a specific arithmetic process, and includes special arithmetic control means 9a and special arithmetic processing means 9b. The special arithmetic control means 9a is a means for controlling execution and stop of the special arithmetic processing means 9b, and the special arithmetic processing means 9b is a means for executing specific arithmetic processing, and details thereof will be described later. Also, a dedicated communication path 10 between the register block 7 and the special arithmetic circuit 9, between the data memory 8 and the special arithmetic circuit 9, and between the instruction decode (D) 2 and the special arithmetic circuit 9, respectively. 11 and 12 are provided.
The instruction fetch (IF) 1 to result store (S) 5 are the same as the functional blocks of the general microprocessor shown in FIG. 2, and these functional blocks constitute general arithmetic means.

FIG. 8 is a block diagram showing details of the connection state to the special arithmetic circuit 9.
In the figure, a communication path 101a indicates a communication path for sending a request signal to the register block 7 and an index signal for designating a register, and the communication path 101b is read from a register designated corresponding to the communication path 101a. A communication path for sending a value to the special arithmetic circuit 9 is shown. Further, the communication path 102a and the communication path 102b, the communication path 103a and the communication path 103b show the same correspondence as the communication path 101a and the communication path 101b, respectively, and the special arithmetic circuit 9 receives three register values from the register block 7. It is configured to capture at the same time. In the illustrated example, three sets of communication paths for reading data from the register block 7 are prepared, but the number is not limited to three sets.

  A communication path 104a indicates a communication path for sending a register value write request signal to the register block 7 and an index signal for designating the register. The communication path 104b is a register designated corresponding to the communication path 104a. A communication path for communicating a value to be written to the register block 7 from the special arithmetic circuit 9 is shown. In the illustrated example, one set of communication paths for writing data to the register block 7 is prepared, but the present invention is not limited to one set.

  A communication path 105a indicates a communication path for sending a request signal for reading a data value to the data memory 8 and an address signal for designating an address on the data memory 8, and the communication path 105b corresponds to the communication path 105a. The communication path for communicating the value read from the designated address to the special arithmetic circuit 9 is shown. The communication path 106a and the communication path 106b, the communication path 107a and the communication path 107b show the same correspondence as the communication path 101a and the communication path 101b, and the special arithmetic circuit 9 simultaneously receives three data values from the data memory 8. I am trying to capture it. In the illustrated example, three sets of communication paths for reading data from the data memory 8 are prepared, but the number is not limited to three sets.

  A communication path 108a indicates a communication path for sending a request signal for writing a data value to the data memory 8 and an address signal designating data. The communication path 108b corresponds to the address designated corresponding to the communication path 108a. A communication path for communicating a value to be written from the special arithmetic circuit 9 to the data memory 8 is shown. In the illustrated example, one set of communication paths for writing data to the data memory 8 is prepared. However, the communication path is not limited to one set.

  Further, the communication path 109a is a communication path that sends a start signal sent from the instruction decode 2 to the special arithmetic circuit 9, and the communication path 109b is a communication path that sends the number of pause cycles sent from the instruction decode 2 to the special arithmetic circuit 9. A communication path 109 c indicates a communication path for sending a computation execution signal sent from the special arithmetic circuit 9 to the instruction decode 2.

FIG. 9 is a block diagram showing details of the special arithmetic circuit 9.
The special arithmetic control means 9 a is connected to communication paths 109 a to 109 c with the instruction decode 2, communication paths 101 a to 104 a are connected to the register block 7, and communication paths 105 a to 108 a are connected to the data memory 8. Each is connected. The special arithmetic control means 9 a includes a temporary stop cycle holding unit 901 and an execution cycle holding unit 902. The pause cycle holding unit 901 holds the number of pause cycles designated from the instruction decode 2 via the communication path 109b, and the execution cycle holding unit 902 performs the current operation when the special arithmetic processing means 9b is executed. This is a functional block that holds what cycle is being executed.

  In the special arithmetic circuit 9, the special arithmetic processing means 9b includes special arithmetic sub-circuits 911, 912, and 913. These special operation sub-circuits 911, 912, and 913 are circuits that realize the functions of the sub-data flows 71, 72, and 73 in FIG. 7, respectively, and each circuit communicates with the communication paths 101b to 104b with the register block 7. The communication paths 105b to 108b with the data memory 8 are connected. The special arithmetic subcircuits 911, 912, and 913 and the special arithmetic control means 9a are connected by communication paths 110 to 112, respectively, and an operation execution signal is given through these communication paths 110 to 112. .

Next, the operation of the special arithmetic circuit 9 configured as described above will be described.
The special arithmetic control means 9a is composed of two independent operations. One is an operation of holding the number of pause cycles designated by the instruction decode 2 in the pause cycle holding unit 901 via the communication path 109b. The other is that the special arithmetic subcircuits 911, 912, and 913 are operated via the communication path 109a in response to the start request specified by the instruction decode 2, and various signals necessary for the operation are driven. Is the action. Hereinafter, these operations will be described with reference to the flowchart shown in FIG.

In the present embodiment, the special operation sub-circuits 911, 912, and 913 receive the communication paths 101b to 103b and the communication path 105b, which are input value communication paths from the register block 7 and the data memory 8, at the time of each calculation. ~ 107b from which communication path is taken in, and the communication path 104b and communication path 108b, which are output value communication paths to the register block 7 and the data memory 8, are fixedly realized. Suppose that
Further, in the special arithmetic control means 9a, it is assumed that the order in which the special arithmetic subcircuits 911, 912, and 913 should be executed is fixedly realized in advance, and the special arithmetic subcircuits 911, 912, and 913 are further realized. When executing the above, it is fixed in advance which index value to be fetched from the register block 7 and which address value to be fetched from the data memory 8 is to be fetched. Suppose that

  In the flowchart of FIG. 10, when the processing of the special arithmetic circuit 9 is started, the special arithmetic control means 9a first sets the number of cycles of the execution cycle holding unit 902 to 0 (step ST1). Thereafter, in step ST2, the process waits until the calculation start signal from the communication path 109a is turned on. When the calculation start signal is turned ON, 1 is added to the number of cycles of the execution cycle holding unit 902 (step ST3). Next, it is compared whether or not the value of the execution cycle holding unit 902 and the value of the suspension cycle holding unit 901 are the same (step ST4), and if they are the same, the calculation is paused (step ST5) and paused. Steps ST4 and ST5 are looped until the value of the cycle holding unit 901 is changed.

  On the other hand, if the value of the execution cycle holding unit 902 and the value of the pause cycle holding unit 901 are different from each other in step ST4 (if the value of the pause cycle holding unit 901 is changed), the process proceeds to step ST6. In step ST6, it is determined whether the number of computation completion cycles has been reached. If so, the pause cycle holding unit 901 is set to 0 in step ST7, and the process proceeds to step ST1. On the other hand, if the calculation completion cycle number has not been reached in step ST6, the process proceeds to step ST8, the calculation circuit corresponding to the current execution cycle is executed, and the process returns to step ST3.

Next, details of what processing is executed in each calculation cycle will be described.
FIG. 11 is an explanatory diagram showing state transition of each calculation cycle.
First, in cycle 1, which is the first cycle,
A request and an address signal necessary for acquiring the value of the data “a” on the input communication path 105a from the data memory 8 are:
A request and an address signal necessary for acquiring the value of the data “b” on the input communication path 106a from the data memory 8 are:
A request and an address signal necessary for acquiring the value of the data “c” on the input communication path 107a from the data memory 8 are:
Issue each.
It is assumed that each data value can be acquired from the data memory 8 in the next cycle.

  In cycle 2, since the values of “a”, “b”, and “c” can be used, the special operation sub-circuit 911 executes the operation (the signal of the communication path 110 is turned ON) and the result “d” The value "" is output to the register block 7 via the communication path 104b. At the same time, a request signal and an address for acquiring values of “e”, “f”, and “g” required in the next cycle 3 are issued to the data memory 8 via the communication paths 105a to 107a.

  In cycle 3, since the values of “e”, “f”, “g” and “d” can be used, the special operation sub-circuit 912 executes the operation (the signal of the communication path 111 is turned ON). At the same time, the resulting “h” value is output to the register block 7. At the same time, a request signal and an address for acquiring values of “i” and “j” required in the next cycle 4 are issued to the data memory 8.

In cycle 4, since the values of “i”, “j” and “h” can be used, the special operation sub-circuit 913 executes the calculation (the signal of the communication path 112 is turned ON) and the result is The value of “k” is output to the data memory 8 through the communication path 108b.
As described above, the special arithmetic control unit 9a controls the special arithmetic processing unit 9b. When the special arithmetic processing means 9b is executing a calculation, that is, not waiting for the start of the calculation or not being temporarily stopped, the special arithmetic circuit in-progress signal of the communication path 109c is turned on to indicate that the calculation is in progress.

Next, how to control the operation of the special arithmetic circuit 9 as viewed from the instruction decode 2 will be described including the situation in which the processing content (list 1) has been corrected.
When processing corresponding to the normal list 1 is to be performed using the special arithmetic circuit 9, a corresponding instruction code, for example,
SPMCI
This is done by issuing this command code.
This instruction code is held in the instruction memory 6 in the same way as a normal instruction code. The instruction code is fetched by the instruction fetch 1 and decoded by the instruction decode 2, thereby performing an operation execution process for the special arithmetic circuit 9. It is interpreted that there is, and a start signal for the special arithmetic circuit 9 is issued through the communication path 109a. Thereby, the special arithmetic circuit 9 starts execution.

As described above, when the special arithmetic circuit 9 is executing an operation, the special arithmetic circuit in-progress signal from the communication path 109c is turned on, and the instruction decode 2 remains stopped during that time.
Now, assume that the processing contents shown in the list 1 are corrected as follows and executed.
Listing 2:
d = (a * b) + c
h = ((d> e)? e: ((d <f)? f: d)) << X
k = (h + i) >> j

This is a modification in which the arithmetic shift for obtaining h as compared with the list 1 is changed from the right shift for the value g to the left shift for the value X.
Originally, the special arithmetic circuit 9 is not configured in such a way that the processing contents of the list 2 can be executed, so that the processing contents written in the list 2 cannot be directly executed by the arithmetic circuit.
However, this modified process is
d = (a * b) + c
h = ((d> e)? e: ((d <f)? f: d)) << 0
h = h << X
k = (h + i) >> j
As described above, if the value g is set to 0, the result h is arithmetically shifted to the left by the value X, overwritten with h, and the k-derivative operation is executed again, the modified processing content can be executed. Is possible. This is because the value of “g” on the data memory 8 is set to 0, the special arithmetic circuit 9 is stopped at the third cycle (stopped after execution of the special arithmetic subcircuit 912), and the arithmetic left shift instruction (SLA) in the normal instruction is executed. ) Is issued, the special operation circuit 9 is restarted (the fourth cycle of the special operation circuit is executed. The special operation sub-circuit 913 is executed), so that the modified processing content can be executed. .

In order to execute such processing, an instruction code that can specify the number of pause cycles for the special arithmetic circuit 9 is, for example,
MCSTP n
Define as follows. Here, n represents immediate data, and is an instruction for instructing the special arithmetic circuit 9 to suspend processing in the nth cycle.

  This instruction code is interpreted by the instruction decode 2 and set in the suspension cycle holding unit 901 via the communication path 109b for the special arithmetic circuit 9. If the above-mentioned SPMCI instruction code is issued after this instruction code is issued, a desired operation is realized. This will be described based on the instruction code string of FIG. Here, it is assumed that “h”, which is the result data after the end of the cycle 2 of the special arithmetic circuit 9, is held in the register r5 in the register block 7.

FIG. 12 is an explanatory diagram of an instruction code string in the arithmetic processing unit according to this embodiment.
Execution of special arithmetic processing by a normal SPMCI instruction code is executed by issuing an instruction address 0104. Here, “...” of the instruction addresses 0100, 0108, and 0124 indicates the issuance of an arbitrary normal instruction code.

In order to execute the modified special processing content, an instruction code is described as in the instruction address 010c and thereafter.
First, 3 is designated as the number of pause cycles for the special arithmetic circuit 9 by the instruction code of the instruction address 010c.
Thereafter, the value of “X” is fetched into the register r3 by the instruction code of the instruction address 0110.
Thereafter, 0 is set to “g” by the instruction code of the instruction address 0114. Here, it is assumed that the value of the register r0 is 0.
Thereafter, the special arithmetic circuit 9 starts to operate according to the SPMCI instruction at the instruction address 0118. Since the operation is set to stop at the number of pause cycles 3 after the operation starts, the special arithmetic circuit 9 stops before issuing the process in the third cycle, and the special arithmetic circuit execution signal of the communication path 109c is turned from ON to OFF. It becomes.

The instruction decode 2 can issue the next instruction code if the special arithmetic circuit execution signal is OFF, and therefore the instruction at the instruction address 011c is issued. As described above, since the operation result “h” in the list 2 is held in the register r5, the value is shifted to the left by “X” bits which is the value of the register r3.
Thereafter, the instruction code MCSTP 0 at the instruction address 0120 is issued. Thus, until step ST4 in the flowchart of FIG. 10 is not YES until the special arithmetic circuit 9 completes the processing, the remaining processing of the special arithmetic circuit 9 is executed.
After the execution is completed, the special arithmetic circuit execution signal changes from ON to OFF, so that the instruction code after the instruction address 0124 is executed.

As described above, in the present embodiment, the processing specialized for the processing content can be executed at high speed by the dedicated special arithmetic circuit 9, and even when the processing content is corrected, the processing time is greatly increased. It is possible to execute the modified processing content by using the special arithmetic circuit 9 that is mounted without dropping the function.
In the present embodiment, the processing contents such as the specific list 1 and list 2 have been described. However, the processing contents of the special arithmetic circuit are not limited to the lists 1 and 2.
In the present embodiment, the special arithmetic processing means 9b is constituted by the three special arithmetic subcircuits 911, 912, and 913. However, the number is not limited to this number, and may be one or more values.

Furthermore, in the present embodiment, the processing content executed by the special arithmetic circuit 9 has been described as one specific processing content. However, as the processing content implemented on the special arithmetic circuit 9, a plurality of independent processing details are provided. It may be a single item. In such a case, an operand (argument) is given to the instruction code “SPMCI” instructing the start of execution of the special arithmetic circuit 9 described above.
SPMCI m
It is also possible to select an arbitrary processing content from a plurality of processing contents by changing m of the argument to an ID number for selecting one from a plurality of independent processing contents and changing the value of m. In that case, the special arithmetic control means 9a can be shared.

  As described above, according to the arithmetic processing apparatus of the first embodiment, the arithmetic processing unit has arithmetic means for performing arithmetic operation, logical operation, and shift operation, and each operation is performed by issuing an instruction code defined for each arithmetic means. General arithmetic processing means for executing a specific arithmetic processing means in a predetermined clock cycle, and special arithmetic processing means based on the issuance of an instruction code defined for the specific arithmetic processing Special processing control means that controls the execution and pause of arithmetic processing in the system, so that processing can be executed at high speed, and when corrections occur, it is possible to partially correct the arithmetic results Therefore, it is possible to avoid an increase in the execution time of the processing after the processing content correction.

  Further, according to the arithmetic processing unit of the first embodiment, the number of clock cycles at which the special arithmetic processing means pauses is set to an arbitrary value using a specific instruction code. Regardless of the form of the processing means, it is possible to correct the result after an arbitrary cycle of the special arithmetic processing means with a general instruction, so that the processing contents of the special arithmetic processing means are implemented and the special arithmetic control means In addition to the effect that the implementation of this processing unit can be easily implemented, there is one instruction code for pause for any processing content of any special arithmetic processing means. This is advantageous in that it does not require a load on the instruction decoding process, and it does not increase the instruction code size unnecessarily.

  Further, according to the arithmetic processing apparatus of the first embodiment, the special arithmetic processing means is configured to be able to execute a plurality of independent specific arithmetic processes, and selects a plurality of independent specific arithmetic processes as a specific arithmetic process. Since it is specified by the argument of the instruction code that specifies the start of processing, it is not necessary to increase the instruction code for each of multiple independent processing contents, so there is an effect that it is not necessary to increase the instruction code size unnecessarily. is there.

It is a block diagram which shows the arithmetic processing apparatus by Embodiment 1 of this invention. It is explanatory drawing of the pipeline stage of a general microprocessor. It is explanatory drawing of the instruction code on the instruction memory of the arithmetic processing unit by Embodiment 1 of this invention. It is explanatory drawing of the instruction code of the arithmetic processing unit by Embodiment 1 of this invention. It is explanatory drawing which shows the data flow of the processing content of the arithmetic processing unit by Embodiment 1 of this invention. It is explanatory drawing which expressed the processing content of the arithmetic processing unit by Embodiment 1 of this invention with the normal instruction code. It is explanatory drawing which shows the structure which divided | segmented the data flow of the processing content of the arithmetic processing unit by Embodiment 1 of this invention for every cycle. It is a block diagram which shows the detail of the connection state to the special arithmetic circuit of the arithmetic processing apparatus by Embodiment 1 of this invention. It is a block diagram which shows the detail of the special arithmetic circuit of the arithmetic processing apparatus by Embodiment 1 of this invention. It is a flowchart which shows operation | movement of the special arithmetic circuit of the arithmetic processing apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the state transition of each arithmetic cycle of the special arithmetic circuit of the arithmetic processing apparatus by Embodiment 1 of this invention. It is explanatory drawing of the instruction code sequence of the special arithmetic circuit of the arithmetic processing unit by Embodiment 1 of this invention.

Explanation of symbols

  1 instruction fetch, 2 instruction decode, 3 instruction execution, 4 memory access, 5 result store, 6 instruction memory, 7 register block, 8 data memory, 9 special operation circuit, 9a special operation control means, 9b special operation processing means.

Claims (2)

General arithmetic processing means having arithmetic means for performing arithmetic operation, logical operation, shift operation, and executing each operation by issuing an instruction code defined for each arithmetic means;
Special arithmetic processing means for executing specific arithmetic processing in a predetermined clock cycle;
Special arithmetic control means for controlling execution and suspension of arithmetic processing in the special arithmetic processing means based on the issuance of an instruction code defined for the specific arithmetic processing ,
An arithmetic processing unit characterized in that the number of clock cycles at which the special arithmetic processing means pauses is set to an arbitrary value using a specific instruction code . The special arithmetic processing means is configured to be able to execute a plurality of independent specific arithmetic processes,
Wherein the plurality of independent selection of specific processing, the arithmetic processing apparatus according to claim 1, characterized in that specified in the argument of the instruction code specifying the start of the specific operation processing.

Images