JP5032897B2 - Pattern drawing apparatus control method and pattern drawing apparatus - Google Patents

Description

The present invention is related to the pattern writing apparatus and a control method thereof.

  Conventionally, a pattern is formed by irradiating light to a photosensitive material formed on a glass substrate for a liquid crystal display device, a glass substrate for a plasma display device, or a semiconductor substrate or a printed circuit board (hereinafter referred to as “substrate”). A pattern drawing apparatus that performs the drawing is used.

  For example, in Patent Document 1, light from a mercury lamp is irradiated to a photosensitive material on a substrate through a mask having a plurality of rectangular openings arranged in a predetermined direction in a light irradiation unit, and the substrate is arranged in an array of openings. A pattern drawing apparatus is disclosed in which a pattern on a stripe is drawn on a photosensitive material by moving in a direction perpendicular to the direction.

  Control of the light irradiator and the like in such a pattern drawing apparatus is normally performed using a semiconductor integrated circuit device. In the development stage of the pattern drawing apparatus, the semiconductor integrated circuit device responds to various specification changes. A change in control is required.

Therefore, in recent years, semiconductor integrated circuit devices having programmable logic circuit devices (PLDs (Programmable Logic Devices)) that can easily change logic circuits by reading logic circuit information are used. Although Patent Document 2 is not related to a pattern drawing device, a semiconductor integrated circuit device including an FPGA (Field Programmable Gate Array) which is one of programmable logic circuit devices is disclosed. Patent Document 2 discloses a technique for reducing the power consumption of a semiconductor integrated circuit device by changing the logic circuit based on the power consumption of the FPGA during the operation of the FPGA and setting the logic circuit corresponding to the power consumption in the FPGA. It is disclosed.
JP 2005-221596 A Japanese Patent Laid-Open No. 2004-22724

  By the way, with the recent increase in the speed of semiconductor integrated circuit devices, the amount of heat generated from the FPGA and the like has increased, and if a cooling device such as a heat sink fan provided in the semiconductor integrated circuit device breaks down, If the temperature rises outside the allowable operating range, a malfunction (so-called thermal runaway) may occur or the FPGA may be damaged.

  As a method for preventing such thermal runaway, the temperature of the FPGA is measured by a temperature sensor or the like provided in the semiconductor integrated circuit device, and when the temperature of the FPGA becomes higher than a predetermined stop temperature, the external power supply A method of stopping the power supply from the device to the semiconductor integrated circuit device is conceivable. However, in this method, the entire semiconductor integrated circuit device is stopped, and communication between the semiconductor integrated circuit device and the outside cannot be performed. Therefore, the cause of the stop and the possibility of recovery (for example, the temperature of the FPGA reaches the recoverable temperature). It is impossible for the user to obtain information regarding whether or not the voltage has decreased, and the semiconductor integrated circuit device cannot be easily restored.

  The present invention has been made in view of the above problems, and an object of the present invention is to reliably prevent a malfunction due to heat of a semiconductor integrated circuit device and to easily perform recovery after a temperature drop.

According to a first aspect of the present invention, there is provided a substrate holding portion for holding a substrate having a photosensitive material layer formed on a main surface, a light irradiation portion for irradiating the photosensitive material on the substrate with light, and the substrate holding. A holding unit moving mechanism that moves a portion in a moving direction parallel to the main surface of the substrate, and a semiconductor integrated circuit device that controls the light irradiation unit, and a pattern is formed using light on a photosensitive material on the substrate. A method of controlling a pattern drawing apparatus for drawing , wherein a) a step of setting a predetermined logic circuit in a programmable logic circuit device in which the logic circuit can be changed in the semiconductor integrated circuit device ; b) the programmable logic measuring a device temperature of the circuit device, in parallel with the c) the b) step, when the device temperature is higher than a predetermined stop temperature after stopping irradiation of light by the light irradiating unit The by sending the programmable logic circuit circuit setting start signal to the device, the steps of the standby state by erasing the logic circuit from said programmable logic circuit device, d) as well as parallel to the b) step c) And a step of resetting the logic circuit in the programmable logic circuit device when the device temperature becomes lower than a recovery temperature lower than the stop temperature after the step.

A second aspect of the present invention is the pattern drawing apparatus control method according to the first aspect, wherein the programmable logic circuit device is a field programmable gate array.

A third aspect of the present invention is the pattern drawing apparatus control method according to the first or second aspect, wherein the temperature of the device temperature measured in the step b) is mounted on the programmable logic circuit device. Performed by the measurement unit.

A fourth aspect of the present invention is the pattern drawing apparatus control method according to any one of the first to third aspects, wherein the circuit setting start signal is transmitted in the step c) and the step d). The logic circuit is reset by the central processing unit.

According to a fifth aspect of the present invention, there is provided a pattern drawing apparatus for drawing a pattern on a photosensitive material on a substrate using light, and a substrate holding unit for holding a substrate having a photosensitive material layer formed on a main surface. A light irradiating unit for irradiating light to the photosensitive material on the substrate, a holding unit moving mechanism for moving the substrate holding unit in a moving direction parallel to the main surface of the substrate, and controlling the light irradiating unit and a semiconductor integrated circuit device, said semiconductor integrated circuit device, a logic circuit is capable of changing the programmable logic circuit device, on the basis of a storage unit for storing logic circuit information, logic circuit information acquired from the storage unit with a programming device for setting the logic circuit in the programmable logic circuit device, and a temperature measuring unit that continuously measures the device temperature of the programmable logic circuit devices, prior Symbol device When time is higher than a predetermined stop temperature, after stopping the irradiation of light by the light irradiation unit, wherein the programming device, the circuit to the programmable logic circuit device defined logic circuit is set in advance When the setting start signal is transmitted, the logic circuit is erased from the programmable logic circuit device to be in a standby state, and the device temperature is lower than a recovery temperature lower than the stop temperature in the standby state. In addition, the logic circuit is reset in the programmable logic circuit device by the programming device .

A sixth aspect of the present invention is the pattern drawing apparatus according to the fifth aspect, wherein the programmable logic circuit device is a field programmable gate array.

A seventh aspect of the present invention is the pattern drawing apparatus according to the fifth or sixth aspect, wherein the temperature measuring unit is mounted on the programmable logic circuit device.

The invention according to an eighth aspect is the pattern drawing apparatus according to any one of the fifth to seventh aspects, wherein the programming device is a central processing unit.

A ninth aspect of the present invention is the pattern drawing apparatus according to any one of the fifth to eighth aspects, further comprising a cooling unit that cools the programmable logic circuit device.

According to the present invention, it is possible to reliably prevent malfunction due to heat of the semiconductor integrated circuit device and to easily perform recovery after a temperature drop. Further, it is possible to reliably prevent malfunction of the light irradiation portion of the pattern writing apparatus.

  FIG. 1 is a side view showing a configuration of a pattern drawing apparatus 1 according to an embodiment of the present invention, and FIG. 2 is a plan view of the pattern drawing apparatus 1. The pattern drawing apparatus 1 is an apparatus that draws a pattern using light on a photosensitive material on a glass substrate 9 (hereinafter simply referred to as “substrate 9”) for a liquid crystal display device. In the present embodiment, a circuit pattern of a TFT (Thin Film Transistor) is drawn on the substrate 9 by the pattern drawing apparatus 1.

  As shown in FIGS. 1 and 2, the pattern writing apparatus 1 is a substrate that holds a substrate 9 on which a layer of a photosensitive material is formed on a main surface 91 (hereinafter referred to as “upper surface 91”) on the (+ Z) side. The holding unit 3 is provided on the base 11 and fixed to the base 11 so as to straddle the holding unit moving mechanism 2 that moves the substrate holding unit 3 in the X direction and the Y direction, and the substrate holding unit 3 and the holding unit moving mechanism 2. And a light irradiation unit 4 that is attached to the frame 12 and irradiates modulated light to the photosensitive material on the substrate 9. Further, the pattern drawing apparatus 1 includes a control unit that controls the light irradiation unit 4.

  As shown in FIGS. 1 and 2, the substrate holding unit 3 includes a stage 31 on which the substrate 9 is placed, a support plate 33 that rotatably supports the stage 31, and the upper surface of the substrate 9 on the support plate 33. A stage rotation mechanism 32 that rotates the stage 31 about a rotation axis 321 perpendicular to 91 is provided.

  The holding unit moving mechanism 2 includes a sub-scanning mechanism 23 that moves the substrate holding unit 3 in the X direction in FIGS. 1 and 2 (hereinafter referred to as “sub-scanning direction”), and a support plate 33 via the sub-scanning mechanism 23. And a main scanning mechanism 25 that moves the substrate holder 3 together with the base plate 24 in the Y direction perpendicular to the X direction (hereinafter referred to as “main scanning direction”). In the pattern drawing apparatus 1, the substrate holder 3 is moved in the main scanning direction and the sub-scanning direction parallel to the upper surface 91 of the substrate 9 by the holding unit moving mechanism 2.

  The sub-scanning mechanism 23 has a linear motor 231 extending in the sub-scanning direction parallel to the main surface of the stage 31 and perpendicular to the main scanning direction on the lower side (that is, (−Z) side) of the support plate 33, and A pair of linear guides 232 extending in the sub-scanning direction are provided on the (+ Y) side and (−Y) side of the linear motor 231. The main scanning mechanism 25 has a linear motor 251 extending in a main scanning direction parallel to the main surface of the stage 31 below the base plate 24, and a main scanning direction on the (+ X) side and the (−X) side of the linear motor 251. A pair of air sliders 252 extending in the direction.

  As shown in FIG. 2, the light irradiation unit 4 includes a plurality (eight in the present embodiment) of optical heads 41 arranged at an equal pitch along the sub-scanning direction and attached to the frame 12. As shown in FIG. 1, the light irradiation unit 4 includes a light source optical system 42 connected to each optical head 41, a UV light source 43 that emits ultraviolet light, and a light source driving unit 44. The UV light source 43 is a solid-state laser, and when the light source driving unit 44 is driven, ultraviolet light having a wavelength of 355 nm is emitted from the UV light source 43 and guided to the optical head 41 via the light source optical system 42.

  Each of the optical heads 41 emits light from the UV light source 43 downward, an optical unit 451 that reflects the light from the output unit 45 and guides it to the spatial light modulator 46, and the optical system 451. The spatial light modulator 46 that reflects and modulates the light emitted from the emitting portion 45, and the modulated light from the spatial light modulator 46 onto the photosensitive material provided on the upper surface 91 of the substrate 9. A guiding optical system 47 is provided.

  FIG. 3 is an enlarged view of the spatial light modulator 46. As shown in FIG. 3, the spatial light modulator 46 includes a diffraction grating type light modulation element 461 that guides light from the UV light source 43 irradiated through the emitting unit 45 to the upper surface 91 of the substrate 9. The light modulation element 461 is manufactured using a semiconductor device manufacturing technique, and is a diffraction grating capable of changing the depth of the grating. A plurality of flexible ribbons 461a and fixed ribbons 461b are alternately arranged in parallel on the light modulation element 461, and the plurality of flexible ribbons 461a can be individually moved up and down with respect to the reference plane on the back, and a plurality of fixed ribbons are arranged. The ribbon 461b is fixed with respect to the reference plane. As a diffraction grating type light modulation element, for example, GLV (Grating Light Valve) (registered trademark of Silicon Light Machines (Sunnyvale, Calif.)) Is known.

  FIG. A and FIG. B is a view showing a cross section of the light modulation element 461 in a plane perpendicular to the flexible ribbon 461a and the fixed ribbon 461b. FIG. As shown in A, when the flexible ribbon 461a and the fixed ribbon 461b are located at the same height with respect to the reference surface 461c (that is, the flexible ribbon 461a does not flex), the surface of the light modulation element 461 is a surface. The reflected light of the incident light L1 is derived as the 0th-order light L2. On the other hand, FIG. When the flexible ribbon 461a bends to the reference surface 461c side of the fixed ribbon 461b as shown in B, the flexible ribbon 461a becomes the bottom surface of the groove of the diffraction grating, and the first-order diffracted light L3 (and higher-order diffracted light). ) Is derived from the light modulation element 461, and the zero-order light L2 disappears. As described above, the light modulation element 461 performs light modulation using a diffraction grating.

  In the light irradiation unit 4 shown in FIG. 1, the light from the UV light source 43 is converted into linear light (light having a light beam cross-section linear) by the light source optical system 42, and the line of the spatial light modulator 46 is passed through the emission unit 45. Irradiation is performed on a plurality of flexible ribbons 461a and fixed ribbons 461b. In the light modulation element 461, when each adjacent one flexible ribbon 461a and fixed ribbon 461b is one ribbon pair, three or more ribbon pairs correspond to one pixel of a pattern to be drawn. In the light modulation element 461, the flexible ribbon 461a of the ribbon pair corresponding to each pixel of the pattern is controlled based on the signal from the light modulator control unit 48 connected to each spatial light modulator 46, and each pixel is controlled. Between a state in which the corresponding ribbon pair emits 0th-order light (regular reflection light) and a state in which non-zeroth-order diffracted light (mainly 1st-order diffracted light ((+1) th-order diffracted light and (−1) th-order diffracted light)) is emitted It is possible to transition with. The 0th-order light emitted from the light modulation element 461 is guided to the optical system 47, and the first-order diffracted light is guided in a direction different from that of the optical system 47. In order to prevent stray light from being generated, the first-order diffracted light is shielded by a light shielding unit (not shown).

  The zero-order light from the light modulation element 461 is guided to the upper surface 91 of the substrate 9 through the optical system 47, and thereby the X direction (that is, the sub-scanning perpendicular to the main scanning direction) on the upper surface 91 of the substrate 9. The modulated light is irradiated to each of a plurality of irradiation positions arranged in the direction). That is, the ribbon pair corresponding to each pixel of the light modulation element 461 is in the ON state when the 0th order light is emitted, and is in the OFF state when the 1st order diffracted light is emitted.

  In the light modulation element 461, FIG. As shown in A, by making the heights of the flexible ribbon 461a and the fixed ribbon 461b from the reference surface 461c equal, zero-order light can be obtained as signal light. The amount of signal light can be reduced by making it slightly lower than the height of 461b, and the amount of light from the light modulation element 461 can be adjusted using this property.

  FIG. 5 is a diagram illustrating a configuration of the control unit 6 that controls the light irradiation unit 4. The control unit 6 includes eight semiconductor integrated circuit devices 61 provided in the eight optical heads 41. In each optical head 41, the semiconductor integrated circuit device 61 is connected to the spatial light modulator 46 and the spatial light modulator 46 is connected. Control. A rectangle drawn with a broken line in FIG. 5 indicates each optical head 41. The control unit 6 includes a light source control unit 62 that controls the light source drive unit 44.

  FIG. 6 is a diagram showing the structure of the semiconductor integrated circuit device 61. As shown in FIG. 6, the semiconductor integrated circuit device 61 includes an FPGA (Field Programmable Gate Array) 611 which is a programmable logic circuit device (PLD (Programmable Logic Device)) whose logic circuit can be changed. A storage unit 612 that stores a plurality of pieces of logic circuit information each indicating a different logic circuit configuration, and a CPU (Central Processing Unit: CPU) that is a programming device that sets a logic circuit in the FPGA 611 based on the logic circuit information acquired from the storage unit 612. Central processing unit) 613, temperature measurement unit 614 that continuously measures the temperature of FPGA 611 (hereinafter referred to as “device temperature”), cooling unit 615 that cools FPGA 611, and circuit board 616 on which these components are arranged Is provided. The output from the temperature measurement unit 614 is transmitted to the CPU 613 via the temperature IC 6141.

  An operable temperature range in which normal operation is guaranteed is set in advance in the FPGA 611. In the semiconductor integrated circuit device 61, an upper limit temperature at which the operation of the FPGA 611 determined based on the operable temperature range of the FPGA 611 is to be stopped. (Hereinafter referred to as “stop temperature”) is stored in the storage unit 612 in advance. In addition, a temperature at which the FPGA 611 whose operation has been stopped exceeding the stop temperature has been lowered and can be operated again (which is lower than the stop temperature, hereinafter referred to as “recovery temperature”) is also stored in advance. Stored in the unit 612. In the present embodiment, the stop temperature is 70 ° C., and the recovery temperature is 40 ° C.

  In the pattern drawing apparatus 1 according to the present embodiment, a type in which the temperature measuring unit 614 is mounted is used as the FPGA 611. Further, a flash memory that is a nonvolatile memory is used as the storage unit 612, and a heat sink is used as the cooling unit 615. In the semiconductor integrated circuit device 61, the device temperature measurement by the temperature measurement unit 614 may be performed continuously or intermittently at predetermined time intervals.

  FIG. 7 is a diagram illustrating a part of the FPGA 611. The FPGA 611 includes a plurality of logic circuit blocks 6111, a grid-like wiring 6112 provided between the plurality of logic circuit blocks 6111, and a plurality of logic circuit blocks including the wiring 6112. A plurality of switch elements 6113 for changing the connection state of 6111 are provided.

  In the semiconductor integrated circuit device 61 illustrated in FIG. 6, the CPU 613 switches the switch element 6113 of the FPGA 611 illustrated in FIG. 7 based on the logic circuit information acquired from the storage unit 612, thereby causing a plurality of logic circuit blocks 6111 of the FPGA 611. Among them, a required logic circuit block 6111 is connected through a wiring 6112 to set a desired logic circuit. The semiconductor integrated circuit device 61 is also based on other logic circuit information acquired from the storage unit 612 by the CPU 613 shown in FIG. 6 when drawing data is changed or upgraded, or logic circuits are debugged. Thus, the switch element 6113 of the FPGA 611 shown in FIG. 7 is switched to change the logic circuit.

  FIG. 8 is a diagram illustrating signals transmitted and received between the FPGA 611 and the CPU 613 when the logic circuit is set (configured) for the FPGA 611 illustrated in FIG. 6. When a logic circuit is set in the FPGA 611, a circuit setting start signal 81 is transmitted from the CPU 613 to the FPGA 611 as shown in FIG. As a result, all the switch elements 6113 (see FIG. 7) of the FPGA 611 are set to a default state, and all the logic circuit blocks 6111 (see FIG. 7) are disconnected from each other. State. At this time, if any logic circuit is already set in the FPGA 611, the logic circuit is erased.

  When the FPGA 611 is set in a standby state, a setting start permission signal 82 is transmitted from the FPGA 611 to the CPU 613. Subsequently, the CPU 613 transmits the setting clock signal 83 and circuit data 84 indicating the logic circuit information to the FPGA 611, the switch element 6113 is switched based on the logic circuit information, and the logic circuit block 6111 is connected to the wiring 6112 (FIG. 7), a logic circuit is set in the FPGA 611. When the logic circuit setting is completed, a circuit setting completion signal 85 is transmitted from the FPGA 611 to the CPU 613.

  Next, pattern drawing by the pattern drawing apparatus 1 will be described. FIG. A and FIG. B is a diagram showing a flow of pattern drawing by the pattern drawing apparatus 1. FIG. When a pattern is drawn, first, power supply from the external power supply to the pattern drawing apparatus 1 is started. Subsequently, in each of the eight semiconductor integrated circuit devices 61 of the control unit 6 shown in FIG. 5, logic circuit information indicating a logic circuit predetermined as a pattern drawing logic circuit is stored in the storage unit 612 by the CPU 613 shown in FIG. The logic circuit is set in the FPGA 611 based on the logic circuit information (step S11).

  Next, in each semiconductor integrated circuit device 61, measurement of the device temperature of the FPGA 611 by the temperature measurement unit 614 is started (step S12). Then, in the state where the device temperature is continuously measured, the movement of the substrate 9 from the drawing start position shown in FIG. 1 in the (+ Y) direction is started and the light irradiation unit 4 transmits light to the substrate 9. Irradiation is started (step S13). In each optical head 41 of the light irradiation unit 4, the light modulation element 461 (see FIG. 3) of the spatial light modulator 46 is based on the data of the pattern to be drawn, and the semiconductor integrated circuit device 61 (FIG. 6) of the control unit 6. The pattern is drawn on the photosensitive material on the upper surface 91 of the substrate 9 by being controlled by the control (that is, ON / OFF of the ribbon pair corresponding to each pixel is switched).

  In the pattern drawing apparatus 1, in parallel with drawing the pattern on the substrate 9 and measuring the device temperature in the semiconductor integrated circuit device 61, the device temperature and storage unit 612 of the FPGA 611 shown in FIG. The CPU 613 continuously performs comparison with the stop temperature (70 ° C.) stored in advance in step S14.

  Normally, when the device temperature is kept lower than the stop temperature and the substrate 9 moves to the drawing stop position (step S15), the light irradiation to the substrate 9 and the movement of the substrate 9 are stopped. The device temperature measurement is also stopped, and the pattern drawing ends (steps S16 and S17). When the pattern drawing apparatus 1 performs continuous pattern drawing on a plurality of substrates 9, the device temperature measurement stop shown in step S <b> 17 is not performed at the end of pattern drawing on one substrate 9. Steps S <b> 13 to S <b> 16 are repeated until step S <b> 17 is performed until pattern drawing on the substrate 9 is completed.

  On the other hand, if an abnormality occurs in the cooling unit 615 of any one of the semiconductor integrated circuit devices 61 during pattern drawing and the cooling efficiency decreases, the device temperature of the FPGA 611 of the semiconductor integrated circuit device 61 rises above a predetermined operating temperature. In step S14, the CPU 613 determines that the device temperature has become higher than the stop temperature. And the irradiation stop signal is transmitted with respect to the light source drive part 44 shown in FIG. 1 from the light source control part 62 (refer FIG. 5) of the control part 6, Thereby, the emission of the light from the UV light source 43 is stopped. In the pattern drawing apparatus 1, when it is detected that the device temperature has become higher than the stop temperature in one semiconductor integrated circuit device 61, the light emission from the UV light source 43 is performed in all the optical heads 41 of the light irradiation unit 4. Is stopped, and light irradiation to the substrate 9 by the light irradiation unit 4 is stopped (step S141). Further, the movement of the substrate 9 is also stopped in parallel with the stop of the light irradiation (step S142).

  Subsequently, in the semiconductor integrated circuit device 61 in which the device temperature becomes higher than the stop temperature, as shown in FIG. 10, a circuit setting start signal 81 is transmitted to the FPGA 611 by the CPU 613, thereby all the switches of the FPGA 611. After the element 6113 (see FIG. 7) is set to the default state, the setting start permission signal 82 is transmitted from the FPGA 611 to the CPU 613. As a result, the logic circuit set in the FPGA 611 in step S11 is erased from the FPGA 611 and the FPGA 611 is set in a standby state, thereby reducing the amount of heat generated by the FPGA 611 (step S143).

  In the semiconductor integrated circuit device 61, the device temperature of the FPGA 611 is continuously measured by the temperature measuring unit 614 even after the FPGA 611 is in the standby state, and the device temperature and the recovery temperature (40 stored in the storage unit 612 in advance) The CPU 613 continuously performs a comparison with the measurement of the device temperature (step S144). When the temperature of the FPGA 611 in the standby state decreases and becomes lower than the recovery temperature, the logic circuit is reset in the FPGA 611 based on the logic circuit information acquired from the storage unit 612 by the CPU 613 as in step S11. Thus, the FPGA 611 is restored (step S145).

  When the FPGA 611 is restored, the process returns to step S13 to start the movement of the substrate 9 and the light irradiation again, and in parallel with the measurement of the device temperature in each semiconductor integrated circuit device 61 and the comparison between the device temperature and the stop temperature. When the drawing of the pattern performed in this step is resumed and the substrate 9 moves to the drawing stop position, the irradiation of light to the substrate 9, the movement of the substrate 9, and the measurement of the device temperature are stopped, and the drawing of the pattern is finished (step S13 to S17). In the pattern drawing apparatus 1, after the restoration of the FPGA 611, a pattern may be drawn on a new substrate 9 without drawing on the substrate 9 being drawn.

  As described above, in the control unit 6 of the pattern drawing apparatus 1, the device temperature of the FPGA 611 is continuously measured in each semiconductor integrated circuit device 61, and when the device temperature becomes higher than the stop temperature, When the circuit setting start signal is transmitted from the CPU 613 to the FPGA 611, the logic circuit is erased from the FPGA 611 and the FPGA 611 is set in a standby state. After that, when the device temperature becomes lower than the recovery temperature, the CPU 613 causes the FPGA 611 to operate. The FPGA 611 is restored by resetting the logic circuit.

  In the pattern drawing apparatus 1, the semiconductor integrated circuit device 61 is controlled by such a control method, so that the FPGA 611 has a malfunction (so-called thermal runaway) of the semiconductor integrated circuit device 61 due to heat from the FPGA 611. It can be easily and reliably prevented by using the function. Further, by continuously measuring the temperature of the FPGA 611 while the CPU 613 is operable even when the operation of the FPGA 611 is stopped, information on whether or not the temperature of the FPGA 611 has decreased to the recovery temperature is easily obtained, and the temperature of the FPGA 611 decreases. Later recovery can be done easily and quickly.

  In the pattern writing apparatus 1, when the device temperature of the FPGA 611 is higher than the stop temperature in the semiconductor integrated circuit device 61, the light irradiation is performed before the CPU 613 transmits a circuit setting start signal to the FPGA 611. The light irradiation by the unit 4 is stopped. Thereby, irradiation of light from the light irradiation unit 4 in a state where the control by the semiconductor integrated circuit device 61 is not performed can be prevented, and malfunction of the light irradiation unit 4 can be prevented.

  In the semiconductor integrated circuit device 61, the device temperature of the FPGA 611 is measured by the temperature measuring unit 614 mounted on the FPGA 611, so that there is no need to provide the FPGA 611 and a separate temperature measuring unit. The structure is simplified. In addition, by using the CPU as a programming device, it is possible to quickly set a logic circuit for the FPGA 611. By using the FPGA as a programmable logic circuit device, various functions are provided in the semiconductor integrated circuit device 61. Can be easily set. Furthermore, by providing the semiconductor integrated circuit device 61 with the cooling unit 615 that cools the FPGA 611, the semiconductor integrated circuit device 61 can be quickly restored after the device temperature becomes higher than the stop temperature.

  As mentioned above, although embodiment of this invention has been described, this invention is not limited to the said embodiment, A various change is possible.

  In pattern drawing by the pattern drawing apparatus 1, the setting of the logic circuit in step S11 and the start of device temperature measurement in step S12 may be performed in parallel, and step S12 is performed prior to step S11. May be.

  In the semiconductor integrated circuit device 61, a temperature measurement unit 614 independent of the FPGA 611 may be provided on the circuit board 616. In addition, another programmable logic circuit device such as CPLD (Complex Programmable Logic Device) may be used instead of the FPGA 611, and another programming device such as CPLD may be used instead of the CPU 613. Furthermore, various devices other than the heat sink may be used as the cooling unit 615.

  In the above embodiment, the 0th-order light from the light modulation element 461 is used as signal light for drawing, but the first-order diffracted light may be used as signal light. Further, the relative positional relationship between the flexible ribbon 461a and the fixed ribbon 461b that is not bent differs from the above embodiment, and the light modulation element that emits zero-order light when the flexible ribbon 461a is bent. 461 may be used. The flexible ribbon 461a and the fixed ribbon 461b do not need to be in a ribbon shape in a strict sense as long as they can be regarded as a belt-like reflecting surface. For example, the block-shaped upper surface may serve as a reflecting surface of the fixed ribbon.

  In the light irradiation unit 4, the light modulation element 461 of the spatial light modulator 46 is not limited to the diffraction grating type, and a multi-channel liquid crystal shutter or the like may be used as the light modulation element. Further, the light modulation element is not limited to one that reflects light, and for example, a laser array may serve as the light modulation element. Furthermore, a two-dimensional spatial light modulator may be employed. In the pattern drawing apparatus, light may be irradiated only from the light irradiation unit 4 to one irradiation position on the substrate 9.

  The pattern drawing device according to the above embodiment may be used for drawing a pattern on a color filter substrate for a liquid crystal display device, and for a flat display device such as a plasma display device or an organic EL (Electro Luminescence) display device. It can also be used for drawing a pattern on a glass substrate, a semiconductor substrate, a printed wiring board, a glass substrate for a photomask, or the like.

It is a side view of the pattern drawing apparatus which concerns on one embodiment. It is a top view of a pattern drawing apparatus. It is a figure which expands and shows a spatial light modulator. It is a figure which shows the cross section of a light modulation element. It is a figure which shows the cross section of a light modulation element. It is a figure which shows the structure of a control part. It is a figure which shows the structure of a semiconductor integrated circuit device. It is a figure which shows a part of FPGA. It is a figure which shows the signal transmitted / received at the time of the setting of the logic circuit with respect to FPGA. It is a figure which shows the flow of the pattern drawing by a pattern drawing apparatus. It is a figure which shows the flow of the pattern drawing by a pattern drawing apparatus. It is a figure which shows the signal transmitted / received when device temperature becomes higher than stop temperature.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pattern drawing apparatus 2 Holding part moving mechanism 3 Substrate holding part 4 Light irradiation part 9 Substrate 61 Semiconductor integrated circuit device 81 Circuit setting start signal 91 Upper surface 611 FPGA
612 storage unit 613 CPU
614 Temperature measurement part 615 Cooling part S11-S17, S141-S145 Step

Claims (9)

A substrate holding portion for holding a substrate having a photosensitive material layer formed on the main surface, a light irradiation portion for irradiating the photosensitive material on the substrate with light, and the substrate holding portion on the main surface of the substrate. A method for controlling a pattern drawing apparatus , which includes a holding unit moving mechanism that moves in a parallel moving direction and a semiconductor integrated circuit device that controls the light irradiation unit, and draws a pattern on a photosensitive material on a substrate using light. There,
a) setting a predetermined logic circuit in a programmable logic circuit device in which the logic circuit can be changed in the semiconductor integrated circuit device ;
b) measuring a device temperature of the programmable logic circuit device;
c) In parallel with the step b), when the device temperature becomes higher than a predetermined stop temperature, after the light irradiation by the light irradiation unit is stopped, a circuit setting start signal is sent to the programmable logic circuit device. , By erasing the logic circuit from the programmable logic circuit device and placing it in a standby state,
d) Reconfiguring the logic circuit in the programmable logic circuit device when the device temperature is lower than the recovery temperature lower than the stop temperature in parallel with the step b) and after the step c) And a process of
A method for controlling a pattern drawing apparatus comprising : It is a control method of the pattern drawing apparatus of Claim 1, Comprising:
The method of controlling a pattern drawing apparatus , wherein the programmable logic circuit device is a field programmable gate array. It is a control method of the pattern drawing apparatus of Claim 1 or 2, Comprising:
The method of controlling a pattern drawing apparatus , wherein the device temperature in the step b) is measured by a temperature measuring unit mounted on the programmable logic circuit device. A method for controlling a pattern drawing apparatus according to any one of claims 1 to 3,
A control method of a pattern drawing apparatus , wherein the transmission of the circuit setting start signal in the step c) and the resetting of the logic circuit in the step d) are performed by a central processing unit. A pattern drawing apparatus for drawing a pattern on a photosensitive material on a substrate using light,
A substrate holding unit for holding a substrate having a photosensitive material layer formed on a main surface;
A light irradiation unit for irradiating the photosensitive material on the substrate with light;
A holding unit moving mechanism for moving the substrate holding unit in a moving direction parallel to the main surface of the substrate;
A semiconductor integrated circuit device for controlling the light irradiation unit;
With
The semiconductor integrated circuit device,
A programmable logic circuit device capable of changing the logic circuit; and
A storage unit for storing logic circuit information;
A programming device for setting a logic circuit in the programmable logic circuit device based on the logic circuit information acquired from the storage unit;
A temperature measurement unit that continuously measures the device temperature of the programmable logic circuit device; and
Equipped with a,
When prior Symbol device temperature is higher than a predetermined stop temperature, after stopping the irradiation of light by the light irradiation unit, wherein the programming device, the programmable logic circuit defined logic circuit is set in advance When the circuit setting start signal is transmitted to the device, the logic circuit is erased from the programmable logic circuit device to be in a standby state, and in the standby state, the device temperature is lower than a recovery temperature lower than the stop temperature. In this case, the logic circuit is reset in the programmable logic circuit device by the programming device. It is a pattern drawing apparatus of Claim 5, Comprising:
The pattern drawing apparatus , wherein the programmable logic circuit device is a field programmable gate array. The pattern drawing apparatus according to claim 5, wherein:
The pattern drawing apparatus , wherein the temperature measuring unit is mounted on the programmable logic circuit device. The pattern drawing apparatus according to any one of claims 5 to 7,
The pattern drawing apparatus , wherein the programming device is a central processing unit . A pattern drawing apparatus according to any one of claims 5 to 8,
A pattern writing apparatus , further comprising a cooling unit that cools the programmable logic circuit device.

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