JP5033682B2 - SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a structure in which wiring for connecting upper and lower layers is not provided in a semiconductor construction, in a semiconductor device in which a plurality of semiconductor constructions are laminated. <P>SOLUTION: Since a solder ball 13b of a second semiconductor construction 1b is joined to a connection pad part of a lower layer wiring 22a of a first semiconductor construction 1a, the second semiconductor construction 1b is arranged under the first semiconductor construction 1a. In the side surface of the first and second semiconductor constructions 1a and 1b, side surface wirings 28a and 28b for connecting upper layer wirings 8a and 8b to lower layer wirings 22a and 22b are provided. In this case, since the side surface wirings 28a and 28b are provided only in the side surface of the first and second semiconductor constructions 1a and 1b, they prevent disconnection, even if the first and second semiconductor constructions 1a and 1b are twisted to some extent. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor element, a manufacturing method thereof, a semiconductor device, and a manufacturing method thereof.

  Some conventional semiconductor devices have a plurality of stacked semiconductor chips in order to reduce the mounting area (see, for example, Patent Document 1). In this case, wiring is formed from the upper surface of the semiconductor chip to the upper part of the side surface of the semiconductor chip. The plurality of semiconductor chips are stacked via an adhesive. In this stacked state, side wirings are formed on the side surfaces of the plurality of stacked semiconductor chips by an ink jet method, and the wirings formed on the upper side surfaces of the respective semiconductor chips are connected by the side wirings.

Japanese Patent Laid-Open No. 2004-303884

  However, in the above-described conventional semiconductor device, the side wiring is formed on the side surfaces of the stacked semiconductor chips so as to straddle the bonding surfaces of the upper and lower semiconductor chips. There is a problem that the wiring may be cut at the portion of the bonding surface of the upper and lower semiconductor chips.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor element and a method for manufacturing the same, a semiconductor device and a method for manufacturing the same, which can make side wiring difficult to cut.

A semiconductor element according to the invention of claim 1 is a semiconductor substrate;
A plurality of upper-layer wirings provided on the semiconductor substrate and exposed such that at least one end facet is flush with a side surface of the semiconductor substrate;
A plurality of lower-layer wirings provided under the semiconductor substrate and exposed such that at least one end facet is flush with a side surface of the semiconductor substrate;
Side wiring provided on the side surface of the semiconductor substrate and connecting the end end face of the exposed upper layer wiring and the end end face of the exposed lower layer wiring;
A side surface insulating film corresponding to the position of the side wiring and provided between the side surface of the semiconductor substrate and the side wiring, and wider than the side wiring,
A plurality of external connection electrodes provided on the connection pad portion of the upper wiring;
A sealing film provided around the external connection electrode on the semiconductor substrate;
A solder ball provided on the external connection electrode;
The upper end of the side wiring is located below the upper surface of the sealing film .
請 semiconductor device according to the invention described in Motomeko 2 is the invention according to claim 1, the side surface of the semiconductor substrate is an inclined surface located progressively inwardly toward from the lower side to the upper side, the inclined The side wiring is provided on the surface.
A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the second aspect of the present invention, further comprising a direction in which the inclined surface on which the side surface wiring is formed covers the side surface wiring and intersects the lower surface of the semiconductor substrate. It has the side surface sealing film extended in this.
According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the external connection electrode is a columnar electrode.
According to a fifth aspect of the present invention, there is provided a semiconductor device according to the first aspect, further comprising a lower overcoat film that covers a portion other than the connection pad portion of the lower wiring.
A semiconductor device according to a sixth aspect of the present invention is a semiconductor device in which first and second semiconductor structures are stacked,
The first semiconductor structure includes a semiconductor substrate;
A plurality of upper layer wirings provided on the semiconductor substrate;
A plurality of lower layer wirings provided under the semiconductor substrate,
And, at least one end portion end surface of the upper layer wiring is exposed to be flush with the side surface of the semiconductor substrate, and at least one end portion end surface of the lower layer wiring is exposed to be flush with the side surface of the semiconductor substrate. Side wiring is provided on the side surface of the semiconductor substrate so as to be connected to the end surface of the exposed upper layer wiring and the end surface of the exposed lower wiring, and is wider than the side wiring. The film corresponds to the position of the side wiring and is provided between the side surface of the semiconductor substrate and the side wiring ,
The second semiconductor structure includes a semiconductor substrate;
A plurality of external connection electrodes provided on the semiconductor substrate;
Comprising a solder ball provided on the external connection electrode,
By the solder balls of the second semiconductor structure body is joined to the connection pad portions of the lower layer wiring of said first semiconductor structure, said first semiconductor structure to said second semiconductor structure body on the It is characterized by being mounted .
The semiconductor device according to the invention described in 請 Motomeko 7 is the invention according to claim 6, the side surface of the first semiconductor structure body is an inclined surface located progressively inwardly toward the lower side to the upper side In addition, the side surface wiring is provided on the inclined surface.
The semiconductor device according to an eighth aspect of the present invention is the semiconductor device according to the seventh aspect, wherein the inclined surface of the first semiconductor structure including the side surface wiring has a side surface that is the lower surface of the first semiconductor structure. It is characterized by being covered with a side surface sealing film extending in a direction intersecting with.
A semiconductor device according to a ninth aspect of the present invention is the semiconductor device according to the sixth aspect , wherein the first semiconductor structure includes a columnar electrode provided on a connection pad portion of an upper wiring layer, and the columnar electrode. And a solder ball provided on the columnar electrode.
A semiconductor device according to a tenth aspect of the present invention is the semiconductor device according to the sixth aspect , wherein the first semiconductor structure has a lower overcoat film that covers other than the connection pad portion of the lower layer wiring. It is what.
The semiconductor device according to an eleventh aspect of the present invention is the semiconductor device according to the sixth aspect , wherein the second semiconductor structure includes an upper wiring as the external connection electrode and a connection pad portion of the upper wiring. And a sealing film provided around the columnar electrode, and the solder ball is provided on the columnar electrode.
A semiconductor device according to a twelfth aspect of the present invention is the semiconductor device according to the eleventh aspect ,
The second semiconductor structure has a plurality of lower layer wirings provided under the semiconductor substrate,
In addition, at least one end edge of the upper layer wiring is exposed to be flush with the side surface of the semiconductor substrate, and at least one end edge of the lower layer wiring is exposed to the side surface of the semiconductor substrate. The side wiring on the side surface of the semiconductor substrate is provided connected to one end end face of the exposed upper layer wiring and one end end face of the exposed lower layer wiring ; and The side surface insulating film having a width wider than that of the side surface wiring corresponds to the position of the side surface wiring and is provided between the side surface of the semiconductor substrate and the side surface wiring .
The semiconductor device according to the invention described in 請 Motomeko 13 is the invention according to claim 12, the side surface of the second semiconductor structure body is an inclined surface located progressively inwardly toward the lower side to the upper side In addition, the side surface wiring is provided on the inclined surface.
A semiconductor device according to a fourteenth aspect of the present invention is the semiconductor device according to the thirteenth aspect of the present invention, wherein the inclined surface of the second semiconductor structure including the side surface wiring has a side surface that is the lower surface of the second semiconductor structure. It is characterized by being covered with a side surface sealing film extending in a direction intersecting with.
According to a fifteenth aspect of the present invention, in the semiconductor device according to the twelfth aspect of the present invention, the second semiconductor structure has a lower overcoat film that covers other than the connection pad portion of the lower layer wiring. It is what.
According to a sixteenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a plurality of upper layer wirings on an upper surface of a semiconductor wafer by extending at least a part thereof into a region corresponding to a dicing street; Forming a plurality of lower-layer wirings in such a manner that at least a part thereof extends into a region corresponding to the dicing street;
Attaching the lower surface side of the lower layer wiring to the upper surface of the dicing tape;
Cutting the semiconductor wafer in a region corresponding to at least the dicing street to form grooves to separate the individual semiconductor components, and forming the upper layer wiring formed in at least the region corresponding to the dicing street; and Cutting and removing the lower layer wiring to expose the cut surface; and
Forming a side wiring on the side surface of the semiconductor structure exposed through the groove by connecting to a cut surface of the upper layer wiring and a cut surface of the lower layer wiring;
Before the step of forming the side wiring, a side insulating film wider than the side wiring is formed on the side surface of the semiconductor structure exposed through the groove so as to correspond to the position of the side wiring. And forming the semiconductor substrate so as to be provided between the side surface of the semiconductor substrate and the side surface wiring,
Peeling the semiconductor structure from the dicing tape;
It is characterized by having.
According to a seventeenth aspect of the present invention, in the semiconductor device manufacturing method according to the sixteenth aspect of the present invention, the groove is formed in a region corresponding to the dicing street.
The method for manufacturing a semiconductor device according to claim 18 is the method according to claim 17 , wherein after forming the groove, the dicing tape is extended by extending the dicing tape in the circumferential direction. It has the process of extending.
The method of manufacturing a semiconductor device according to claim 19 is the method of manufacturing a semiconductor element according to claim 17 , wherein the groove is individually separated into the dicing street and regions corresponding to both sides thereof. The side surface is formed so as to gradually become an inclined surface located on the inner side from the lower side toward the upper side.
According to a twentieth aspect of the present invention, there is provided a semiconductor device manufacturing method according to any one of the sixteenth to nineteenth aspects, wherein the side surface wiring is formed using an ink jet head. .
The method of manufacturing a semiconductor device according to the invention described in 請 Motomeko 21 is the invention according to claim 19,
Before the step of peeling the semiconductor structure from the dicing tape,
Forming a side surface sealing film in the groove and covering the inclined surface of the semiconductor structure including the side surface wiring and the side surface insulating film with the side surface sealing film;
And a step of cutting the side surface sealing film at a central portion in the width direction.
According to a twenty-second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a plurality of upper layer wirings on an upper surface of a semiconductor wafer by extending at least a part of the upper wiring into a region corresponding to a dicing street; Forming a plurality of lower-layer wirings in such a manner that at least a part thereof extends into a region corresponding to the dicing street;
Attaching the lower surface side of the lower layer wiring to the upper surface of the dicing tape;
Cutting the semiconductor wafer in a region corresponding to at least the dicing street to form grooves to separate the individual semiconductor components, and forming the upper layer wiring formed in at least the region corresponding to the dicing street; and Cutting and removing the lower layer wiring to expose the cut surface; and
Forming a side wiring on the side surface of the semiconductor structure exposed through the groove by connecting to a cut surface of the upper layer wiring and a cut surface of the lower layer wiring;
Before the step of forming the side wiring, a side insulating film wider than the side wiring is formed on the side surface of the semiconductor structure exposed through the groove so as to correspond to the position of the side wiring. And forming the semiconductor substrate so as to be provided between the side surface of the semiconductor substrate and the side surface wiring,
Peeling the semiconductor structure from the dicing tape;
Another part having a semiconductor substrate, a plurality of external connection electrodes provided on the semiconductor substrate, and solder balls provided on the external connection electrodes under the semiconductor structure peeled from the dicing tape Bonding the solder ball to the connection pad portion of the lower layer wiring of the semiconductor structure, and placing the semiconductor structure;
It is characterized by having.
According to a twenty- third aspect of the present invention, in the semiconductor device manufacturing method according to the twenty-second aspect of the present invention, the groove is formed in a region corresponding to the dicing street.
According to a twenty-fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the twenty- third aspect, wherein after forming the groove, the dicing tape is stretched and expanded in the peripheral direction to obtain a width of the groove. It has the process of extending.
A semiconductor device manufacturing method according to a twenty-fifth aspect of the present invention is the semiconductor device manufacturing method according to the twenty-second aspect of the present invention, wherein the grooves are individually separated into the dicing street and regions corresponding to both sides thereof. The side surface is formed so as to gradually become an inclined surface located on the inner side from the lower side toward the upper side.
According to a twenty-sixth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to any of the twenty-second to twenty- fifth aspects, wherein the side surface wiring is formed using an ink jet head. .
The method of manufacturing a semiconductor device according to the invention described in 請 Motomeko 27 is the invention according to claim 22 to 26, the formation of the side insulating film is characterized in that performed using an inkjet head.
According to a twenty-eighth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the twenty-fifth aspect of the present invention.
Before the step of peeling the semiconductor structure from the dicing tape,
Forming a side surface sealing film in the groove and covering the inclined surface of the semiconductor structure including the side surface wiring and the side surface insulating film with the side surface sealing film;
And a step of cutting the side surface sealing film at a central portion in the width direction.

  According to this invention, the solder ball of the second semiconductor structure is bonded to the connection pad portion of the lower layer wiring of the first semiconductor structure, and the first semiconductor structure is mounted on the second semiconductor structure. By doing so, it is possible to stack the first and second semiconductor structures, and in addition, it is possible to make it difficult to cut the side wiring provided only on the side surface of the first semiconductor structure.

(First embodiment)
FIG. 1 is a front view of a semiconductor device as a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II in FIG. This semiconductor device includes a first semiconductor structure (semiconductor element) 1a and a second semiconductor structure 1b disposed therebelow. In this case, the first and second semiconductor structures 1a and 1b have the same planar size and basic structure, and are generally called CSP (chip size package).

  The first and second semiconductor structures 1a and 1b include planar silicon substrates (semiconductor substrates) 2a and 2b. The planar sizes of the silicon substrates 2a and 2b are the same. An integrated circuit (not shown) having a predetermined function is provided on the upper surfaces of the silicon substrates 2a and 2b, and a plurality of connection pads 3a and 3b made of aluminum metal or the like are provided on the periphery of the upper surface so as to be connected to the integrated circuit. It has been.

  Upper layer insulating films 4a and 4b made of silicon oxide or the like are provided on the upper surfaces of the silicon substrates 2a and 2b except for the center portions of the connection pads 3a and 3b. The center portions of the connection pads 3a and 3b are formed on the upper layer insulating films 4a and 4b. It is exposed through the provided openings 5a and 5b. Protective films 6a and 6b made of polyimide resin or the like are provided on the upper surface of the upper insulating films 4a and 4b. Openings 7a and 7b are provided in the protective films 6a and 6b at portions corresponding to the openings 5a and 5b of the upper insulating films 4a and 4b.

  Upper wirings 8a and 8b are provided on the upper surfaces of the protective films 6a and 6b. The upper layer wirings 8a and 8b are composed of base metal layers 9a and 9b made of copper or the like provided on the upper surfaces of the protective films 6a and 6b, and upper metal layers 10a made of copper provided on the upper surfaces of the base metal layers 9a and 9b, It has a two-layer structure consisting of 10b. The upper wirings 8a and 8b are connected to the connection pads 3a and 3b through the openings 5a and 5b of the upper insulating films 4a and 4b and the openings 7a and 7b of the protective films 6a and 6b.

  Columnar electrodes 11a and 11b made of copper are provided on the upper surface of the connection pad portion made of one end of the upper layer wirings 8a and 8b. Sealing films 12a and 12b made of epoxy resin or the like are provided on the upper surfaces of the upper wirings 8a and 8b and the protective films 6a and 6b so that the upper surfaces thereof are flush with the upper surfaces of the columnar electrodes 11a and 11b. Solder balls 13a and 13b are provided on the upper surfaces of the columnar electrodes 11a and 11b.

  Lower insulating films 21a and 21b made of polyimide resin or the like are provided on the lower surfaces of the silicon substrates 2a and 2b. Lower layer wirings 22a and 22b are provided on the lower surfaces of the lower layer insulating films 21a and 21b. The lower wirings 22a and 22b are composed of base metal layers 23a and 23b made of copper or the like provided on the lower surfaces of the lower insulating films 21a and 21b, and an upper metal layer 24a made of copper provided on the lower surfaces of the base metal layers 23a and 23b. , 24b.

  Lower overcoat films 25a and 25b made of solder resist or the like are provided on the lower surfaces of the lower wirings 22a and 22b and the lower insulating films 21a and 21b. Openings 26a and 26b are provided in the lower overcoat films 25a and 25b in portions corresponding to the connection pad portions formed by one end portions of the lower layer wirings 22a and 22b. In this case, in particular, the opening 26a of the first semiconductor structure 1a is disposed at a position corresponding to the solder ball 13b of the second semiconductor structure 1b.

  Here, at least one end portion of the upper layer wirings 8a and 8b serves as a connection pad portion, but the other end surface has silicon substrates 2a and 2b, upper layer insulating films 4a and 4b, protective films 6a and 6b, and a sealing layer. It is flush with the side surfaces of the film 12a, 12b and is exposed to the outside. In addition, at least one end portion of the lower layer wirings 22a and 22b is a connection pad portion, but the other end surface is formed of the silicon substrates 2a and 2b, the lower layer insulating films 21a and 21b, and the lower layer overcoat films 25a and 25b. It is flush with the sides and exposed to the outside.

  In this case, the other end face of the upper layer wiring 8a, 8b exposed to the outside and the other end face of the lower layer wiring 22a, 22b exposed to the outside correspond to each other in the silicon substrates 2a, 2b, etc. It is arranged above and below the side. Protective films 6a and 6b, upper insulating films 4a and 4b, silicon substrates 2a and 2b, between the other end surface of the upper layer wirings 8a and 8b and the other end surface of the lower layer wirings 22a and 22b, Side insulating films 27a and 27b made of polyimide resin or the like are provided on the side surfaces of the lower insulating films 21a and 21b.

  Side surfaces of the sealing films 12a and 12b above the other end portions of the upper-layer wirings 8a and 8b exposed to the outside, end surfaces of the other end portions of the upper-layer wirings 8a and 8b exposed to the outside, and lower sides thereof The side surfaces of the side insulating films 27a and 27b, the other end surfaces of the lower wirings 22a and 22b exposed to the outside of the side insulating films 27a and 27b, and the side surfaces of the lower overcoat films 25a and 25b below are made of the materials described later. Side wirings 28a and 28b are provided. In this case, as shown in FIG. 1, the width of the side insulating films 27a and 27b is larger than the width of the side wirings 28a and 28b. This is to prevent a short circuit between the side wirings 28a and 28b and the silicon substrates 2a and 2b.

  The second semiconductor structure 1b has its solder ball 13b bonded to the connection pad portion of the lower layer wiring 22a through the opening 26a of the lower overcoat film 25a of the first semiconductor structure 1a. Are disposed under the first semiconductor structure 1a. That is, the first semiconductor structure 1a is stacked on the second semiconductor structure 1b.

  Thus, in this semiconductor device, the electrical connection between the first semiconductor structure 1a and the second semiconductor structure 1b disposed thereunder is via the solder balls 13b of the second semiconductor structure 1b. Therefore, even if the stacked first and second semiconductor structures 1a and 1b are twisted to some extent, the solder balls 13b of the second semiconductor structure 1b are not damaged, and the stacked first and second stacked structures are not damaged. The electrical connection between the two semiconductor structures 1a and 1b can be maintained satisfactorily. In this case, the side wirings 28a and 28b provided only on the side surfaces of the first and second semiconductor structures 1a and 1b can be made difficult to cut.

  Next, an example of a manufacturing method of the semiconductor device will be described. First, an example of a manufacturing method of the first semiconductor structure 1a will be described as a representative. First, as shown in FIG. 3, a connection pad 3a made of an aluminum-based metal or the like and an upper insulating film 4a made of silicon oxide or the like are formed on a silicon substrate (hereinafter referred to as a semiconductor wafer 31) in a wafer state. Is prepared in such a manner that the central portion is exposed through the opening 5a formed in the upper insulating film 4a.

  In this case, an integrated circuit (not shown) having a predetermined function is formed in a region where each first semiconductor structure is formed on the upper surface of the semiconductor wafer 31, and the connection pads 3a are formed in the corresponding regions. It is electrically connected to the integrated circuit. In FIG. 3, an area indicated by reference numeral 32 is an area corresponding to dicing street.

  Next, as shown in FIG. 4, a protective film 6a made of polyimide resin or the like is formed on the upper surface of the upper insulating film 4a by screen printing, spin coating, or the like. In this case, the opening 7a is formed in the protective film 6a at the portion corresponding to the opening 5a of the upper insulating film 4a by laser processing or photolithography with laser beam irradiation. Also, a lower insulating film 21a made of polyimide resin or the like is formed on the lower surface of the semiconductor wafer 31 by screen printing or spin coating.

  Next, as shown in FIG. 5, a base metal layer 9a is formed on the entire upper surface of the protective film 6a including the upper surface of the connection pad 3a exposed through the openings 5a and 7a of the upper insulating film 4a and the protective film 6a. To do. Further, the base metal layer 23a is formed on the entire lower surface of the lower insulating film 21a. In this case, the base metal layers 9a and 23a may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and further may be titanium or the like formed by sputtering. A copper layer may be formed on the thin film layer by sputtering.

Next, plating resist films 33 and 34 are pattern-formed on the upper surface of the base metal layer 9a and the lower surface of the base metal layer 23a. In this case, openings 35 and 36 are formed in the plating resist films 33 and 34 in portions corresponding to the formation regions of the upper metal layers 10a and 24a. Next, the upper metal layer 10a is formed on the upper surface of the base metal layer 9a in the opening 35 of the plating resist film 33 by performing electrolytic plating of copper using the base metal layers 9a and 23a as a plating current path, and Then, the upper metal layer 24a is formed on the lower surface of the base metal layer 23a in the opening 36 of the plating resist film 34. In this state, at least some of the upper metal layers 10 a and 23 a are formed so as to extend into a region corresponding to the dicing street 32 . Next, the plating resist films 33 and 34 are peeled off.

  Next, as shown in FIG. 6, a plating resist film 37 is patterned on the upper surface of the base metal layer 9a including the upper metal layer 10a. In this case, an opening 38 is formed in the plating resist film 37 in the connection pad portion of the upper metal layer 10a, that is, the portion corresponding to the columnar electrode 11a formation region. Next, by performing copper electroplating using the base metal layer 9a as a plating current path, the columnar electrode 11a is formed on the upper surface of the connection pad portion of the upper metal layer 10a in the opening 38 of the plating resist film 37.

Next, the plating resist film 37 is peeled off, and then unnecessary portions of the base metal layers 9a and 23a are removed by etching using the upper metal layers 10a and 24a as a mask, as shown in FIG. The underlying metal layer 9a remains only below, and the underlying metal layer 23a remains only on the upper metal layer 24a. In this state, an upper layer wiring 8a having a two-layer structure is formed by the upper metal layer 10a and the underlying metal layer 9a remaining therebelow. Further, a lower layer wiring 22a having a two-layer structure is formed by the upper metal layer 24a and the base metal layer 23a remaining thereon. Further, at least a part of the upper layer wiring 8 a and the lower layer wiring 22 a are formed so as to extend into a region corresponding to the dicing street 32 .

  Next, as shown in FIG. 8, a sealing film 12a made of an epoxy resin or the like is formed on the upper surface of the protective film 6a including the upper wiring 8a and the columnar electrode 11a by screen printing or spin coating. Is formed to be thicker than the height of the columnar electrode 11a. Therefore, in this state, the upper surface of the columnar electrode 11a is covered with the sealing film 12a. Next, by appropriately grinding and removing the upper surface side of the sealing film 12a, as shown in FIG. 9, the upper surface of the columnar electrode 11a is exposed and the sealing including the exposed upper surface of the columnar electrode 11a is included. The upper surface of the stop film 12a is flattened.

  Next, as shown in FIG. 10, solder balls 13a are formed on the upper surfaces of the columnar electrodes 11a. Next, a lower overcoat film 25a made of a solder resist or the like is formed on the lower surface of the lower insulating film 21a including the lower wiring 22a by screen printing or spin coating. In this case, an opening 26a is formed in the lower overcoat film 25a in the portion corresponding to the connection pad portion of the lower layer wiring 22a by laser processing for irradiating a laser beam or photolithography.

  Next, as shown in FIG. 11, the lower surface of the lower overcoat film 25 a is attached to the upper surface of the dicing tape 39. Next, as shown in FIG. 12, along the dicing street 32, the sealing film 12a, the protective film 6a, the upper insulating film 4a, the semiconductor wafer 31, the lower insulating film 21a, and the lower overcoat film 25a are cut and individually The first semiconductor structure 1a is separated. In this state, the semiconductor wafer 31 is separated into individual silicon substrates 2a.

  In this case, the dicing tape 39 is cut to the middle in the thickness direction. Then, although it isolate | separates into each 1st semiconductor structure 1a, since each 1st semiconductor structure 1a is affixed on the upper surface of the dicing tape 39, each 1st semiconductor structure including the upper surface of the dicing tape 39 is included. A groove 40 is formed in a region corresponding to the dicing street 32 between the semiconductor structural bodies 1a.

  In this state, each first semiconductor structure 1a is separated from the adjacent ones with an interval of the width of the groove 40, that is, the width of the dicing street 32. In addition, in the state shown in FIG. 11 before cutting, at least a part of the upper layer wiring 8a and the lower layer wiring 22a are formed so as to extend into a region corresponding to the dicing street 32, and therefore cut along the dicing street 32. Then, as shown in FIG. 12, the upper layer wiring 8a and the lower layer wiring 22a formed in the region corresponding to the dicing street 32 are cut and removed, and the cut surface (the end surface of the other end portion) is exposed.

  Next, as shown in FIG. 13, when the dicing tape 39 is pulled and expanded in the circumferential direction, the width of the groove 40, that is, the interval between the first semiconductor structural bodies 1a is expanded in accordance with the expansion. This is for facilitating the formation of the side insulating film 27a and the side wiring 28a described below. Next, as shown in FIG. 14, it is between the other end part end surface of the upper layer wiring 8a of the 1st semiconductor structure 1a exposed through the extended groove | channel 40, and the other end part end surface of the lower layer wiring 22a. A side insulating film 27a made of polyimide resin or the like is formed on the side surfaces of the protective film 6a, the upper insulating film 4a, the silicon substrate 2a, and the lower insulating film 21a.

  As a method for forming the side insulating film 27 a, there is a method in which a low-temperature curing type polyimide liquid resin is applied using the inkjet head 41. Then, as shown in FIG. 14, the inkjet head 41 is moved in the horizontal direction in an appropriately inclined state, and the liquid resin may be sprayed obliquely from above, as indicated by solid line and alternate long and short dash arrows. In this case, in FIG. 13, first, the side surface insulating film 27a is formed on the right side surface of each first semiconductor structure 1a, and then the inclination direction of the inkjet head 41 is changed to the left side of each first semiconductor structure 1a. A side insulating film 27a may be formed on the surface.

  Next, as shown in FIG. 15, the side surface of the sealing film 12a above the end surface of the other end portion of the upper layer wiring 8a exposed through the expanded groove 40, and the other end portion of the upper layer wiring 8a below it. Side wiring 28a made of a material described later is formed on the end surface, the side surface of the side insulating film 27a on the lower side, the end surface on the other end of the lower layer wiring 22a on the lower side, and the side surface of the lower overcoat film 25a on the lower side.

  As a method for forming the side wiring 28 a, there is a method in which a metal nano ink is applied using the ink jet head 42. The metal nano ink is an ink in which metal particles composed mainly of copper, silver or the like having a particle size of nano order (several nm to several tens of nm) are dispersed in a polar organic solvent (aqueous or alcoholic).

  Then, as shown in FIG. 15, the inkjet head 42 is moved in the horizontal direction in an appropriately tilted state, and the metal nano ink may be sprayed obliquely from above as indicated by solid line and alternate long and short dash arrows. Also in this case, in FIG. 15, first, the side wiring 28a is formed on the right side surface of each first semiconductor structure 1a, and then the inclination direction of the inkjet head 42 is changed to change the left side of each first semiconductor structure 1a. The side wiring 28a may be formed on the surface.

  Next, when the first semiconductor structure 1a is peeled from the dicing tape 39, the first semiconductor structure 1a (and the second semiconductor structure 1b) shown in FIG. 2 is obtained. Next, as shown in FIG. 2, the solder balls 13b of the second semiconductor structure 1b are connected to the connection pad portions of the lower layer wiring 22a through the openings 26a of the lower overcoat film 25a of the first semiconductor structure 1a. By bonding, the second semiconductor structure 1b is disposed under the first semiconductor structure 1a. Thus, the semiconductor device shown in FIG. 2 is obtained.

  By the way, in the method of manufacturing the semiconductor device, as shown in FIGS. 14 and 15, the inkjet heads 41, 42 in a state where a plurality of first semiconductor structures 1 a separated from each other are attached to the dicing tape 39. Are used to form the side surface insulating film 27a and the side surface wiring 28a on the side surface of each first semiconductor structure 1a. Therefore, the side surface insulating film is formed on the side surface of the single semiconductor structure 1a that is completely separated. Compared with the case where the 27a and the side wiring 28a are formed, the productivity can be greatly improved.

  The width of the dicing street 32 shown in FIG. 12 may be the same as the width of the expanded groove 40 shown in FIG. In this case, it is not necessary to expand the dicing tape 39 by pulling it in the peripheral direction. However, if the width of the dicing street 32 shown in FIG. 12 is the same as the width of the expanded groove 40 shown in FIG. 13, the number of semiconductor wafers 31 is reduced accordingly.

(Second Embodiment)
FIG. 16 is a sectional view of a semiconductor device as a second embodiment of the present invention. This semiconductor device differs from the semiconductor device shown in FIG. 2 in that all side surfaces of the first and second semiconductor structures 1a and 1b are formed so that the cross section of the first semiconductor structure 1a has an inverted trapezoidal shape. The inclined surfaces 51a and 51b are gradually located on the inner side from the lower side to the upper side, and the side surface insulating film 27a and the side surface wiring 28a are provided on the inclined surfaces 51a and 51b.

  Next, an example of a manufacturing method of the first semiconductor structure 1a in this semiconductor device will be described. In this case, after the step shown in FIG. 11, as shown in FIG. 17, the sealing film 12a, the protective film 6a, the upper insulating film 4a, the semiconductor wafer 31, the lower insulating film 21a, and the lower overcoat on both sides of the dicing street 32 are provided. A groove 40 having an inverted trapezoidal cross section is formed in the film 25a and separated into individual first semiconductor components 1a. In this case, a dicing blade (not shown) having an inverted trapezoidal cross-sectional shape is used.

  Also in this case, the dicing tape 39 is cut to the middle in the thickness direction. Then, although it isolate | separates into each 1st semiconductor structure 1a, since each 1st semiconductor structure 1a is affixed on the upper surface of the dicing tape 39, each 1st semiconductor structure including the upper surface of the dicing tape 39 is included. A groove 40 having an inverted trapezoidal cross section is formed between the semiconductor structural bodies 1a, that is, in the dicing street 32 and regions corresponding to both sides thereof.

  In this state, in the state shown in FIG. 11 before cutting, at least a part of the upper layer wiring 8a and the lower layer wiring 22a are also formed in the region corresponding to the dicing street 32. When the trapezoidal groove 40 is formed, as shown in FIG. 17, the upper layer wiring 8a and the lower layer wiring 22a formed in the regions corresponding to the dicing street 32 and both sides thereof are cut and removed, and the cut surface (others) The end face is exposed. In this case, all the side surfaces of the first semiconductor structure 1a including the cut surface are inclined surfaces 51a.

  Next, as shown in FIG. 18, a low-temperature curing type polyimide-based liquid resin is used by using an inkjet head 41 on the inclined surface 51 a of the first semiconductor structure 1 a exposed through the groove 40 having an inverted trapezoidal cross section. Etc. are applied to form the side surface insulating film 27a. Also in this case, the inkjet head 41 is moved in the horizontal direction in a state where it is appropriately inclined, and the liquid resin is sprayed obliquely from above as indicated by the solid line and one-dot chain line arrows.

  Next, as shown in FIG. 19, the metal nano ink is applied to the inclined surface 51 a including the side insulating film 27 a of the first semiconductor structure 1 a exposed through the groove 40 having the inverted trapezoidal cross section using the inkjet head 42. Is applied to form the side wiring 28a. Also in this case, the ink jet head 42 is moved in the horizontal direction to an appropriately inclined state, and the metal nano ink is sprayed obliquely from above as indicated by solid line and one-dot chain line arrows. Next, when the first semiconductor structure 1a is peeled from the dicing tape 39, the first semiconductor structure 1a (and the second semiconductor structure 1b) shown in FIG. 16 is obtained.

  As described above, in this semiconductor device manufacturing method, the grooves 40 having the inverted trapezoidal cross section are formed in the dicing streets 32 and the regions corresponding to both sides thereof, and the entire side surfaces of the first semiconductor structure 1a are inclined surfaces 51a. Therefore, the side insulating film 27a and the side wiring 28a can be easily formed using the appropriately inclined inkjet heads 41 and 42 without expanding the width of the groove 40.

(Third embodiment)
FIG. 20 is a sectional view of a semiconductor device as a third embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 16 in that the inclined surfaces 51a and 51b of the first and second semiconductor constructs 1a and 1b including the side insulating films 27a and 27b and the side wirings 28a and 28b are epoxy bonded. It is a point covered with side sealing films 52a and 52b made of a diameter resin or the like. In this case, the side surfaces of the side sealing films 52a and 52b are surfaces orthogonal to the lower surfaces of the first and second semiconductor constructs 1a and 1b, and the upper surfaces are the first and second semiconductor constructs 1a and 1b. The lower surface is flush with the lower surfaces of the first and second semiconductor constructs 1a and 1b.

  Next, an example of a manufacturing method of the first semiconductor structure 1a in this semiconductor device will be described. In this case, if the solder ball 13a is not formed in the step shown in FIG. 10, the state shown in FIG. 21 is obtained after the step shown in FIG. In this state, the side insulating film 27a and the side wiring 28a are formed on the inclined surface 51a of the first semiconductor structure 1a attached to the upper surface of the dicing tape 39.

  Next, as shown in FIG. 22, a side surface sealing film 52a made of an epoxy resin or the like is formed in the groove 40 and above and on the upper surface of the first semiconductor structure 1a by screen printing, spin coating, or the like. Form. Therefore, in this state, the upper surfaces of the columnar electrode 11a and the sealing film 12a of the first semiconductor structure 1a are covered with the side surface sealing film 52a.

  Next, by appropriately grinding and removing the upper surface side of the side surface sealing film 52a, the upper surfaces of the columnar electrode 11a and the sealing film 12a are exposed as shown in FIG. 23, and the exposed columnar electrode is exposed. The upper surface of the side surface sealing film 52a including the upper surfaces of 11a and the sealing film 12a is planarized. Next, the dicing tape 39 is peeled off, and then the side sealing film 52a protruding to the lower surface side of the lower overcoat film 25a is ground and removed as shown in FIG. In this state, the lower surfaces of the lower overcoat film 25a and the side surface sealing film 52a are flush with each other.

  Next, as shown in FIG. 25, solder balls 13a are formed on the upper surfaces of the columnar electrodes 11a. Next, as shown in FIG. 26, when the side surface sealing film 52a is cut at the center in the width direction, the first semiconductor structure 1a (and the second semiconductor structure 1b) shown in FIG. 20 is obtained. In the first semiconductor structure 1a thus obtained, the side wiring 28a can be protected by the side sealing film 52a.

(Fourth embodiment)
FIG. 27 shows a sectional view of a semiconductor device as a fourth embodiment of the present invention. This semiconductor device is greatly different from the semiconductor device shown in FIG. 2 in that a third semiconductor structure 1c is disposed under the second semiconductor structure 1b. In this case, the third semiconductor structure 1c is provided with the connection pad 3c, the upper insulating film 4c, the protective film 6c, the upper wiring 8c, the columnar electrode 11c, the sealing film 12c, and the solder ball 13c on the silicon substrate 2c. It has a structure.

  The third semiconductor structure 1c has its solder ball 13c bonded to the connection pad portion of the lower layer wiring 22c through the opening 26b of the lower layer overcoat film 25b of the second semiconductor structure 1b. The second semiconductor structure 1b is disposed below. One or more semiconductor structures having the same structure as the second semiconductor structure 1b may be arranged between the second semiconductor structure 1b and the third semiconductor structure 1c. .

1 is a front view of a semiconductor device as a first embodiment of the present invention. Sectional drawing which follows the II-II line | wire of FIG. Sectional drawing of what was initially prepared in the case of manufacture of the semiconductor device shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 15 is a sectional view of a step following FIG. 14. Sectional drawing of the semiconductor device as 2nd Embodiment of this invention. FIG. 17 is a cross-sectional view of a predetermined process when the semiconductor device shown in FIG. 16 is manufactured. FIG. 18 is a cross-sectional view of the process following FIG. 17. FIG. 19 is a cross-sectional view of the process following FIG. 18. FIG. 20 is a cross-sectional view of the process following FIG. 19. Sectional drawing of the semiconductor device as 3rd Embodiment of this invention. Sectional drawing of a predetermined | prescribed process in the case of manufacture of the semiconductor device shown in a figure. FIG. 23 is a sectional view of a step following FIG. 22; FIG. 24 is a sectional view of a step following FIG. 23. FIG. 25 is a sectional view of a step following FIG. 24. FIG. 26 is a sectional view of a step following FIG. 25. Sectional drawing of the semiconductor device as 4th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a 1st semiconductor structure 1b 2nd semiconductor structure 2a, 2b Silicon substrate 3a, 3b Connection pad 4a, 4b Upper insulating film 6a, 6b Protective film 8a, 8b Wiring 11a, 11b Columnar electrode 12a, 12b Sealing film 13a, 13b Solder balls 21a, 21b Lower insulating film 22a, 22b Lower wiring 25a, 25b Lower overcoat film 27a, 27b Side insulating film 28a, 28b Side wiring 31 Semiconductor wafer 32 Dicing street 39 Dicing tape

Claims (28)

A semiconductor substrate;
A plurality of upper-layer wirings provided on the semiconductor substrate and exposed such that at least one end facet is flush with a side surface of the semiconductor substrate;
A plurality of lower-layer wirings provided under the semiconductor substrate and exposed such that at least one end facet is flush with a side surface of the semiconductor substrate;
Side wiring provided on the side surface of the semiconductor substrate and connecting the end end face of the exposed upper layer wiring and the end end face of the exposed lower layer wiring;
A side surface insulating film corresponding to the position of the side wiring and provided between the side surface of the semiconductor substrate and the side wiring, and wider than the side wiring,
A plurality of external connection electrodes provided on the connection pad portion of the upper wiring;
A sealing film provided around the external connection electrode on the semiconductor substrate;
A solder ball provided on the external connection electrode;
The semiconductor element according to claim 1, wherein an upper end of the side wiring is positioned below an upper surface of the sealing film.   The invention according to claim 1 is characterized in that the side surface of the semiconductor substrate is an inclined surface gradually located on the inner side as it goes from the lower side to the upper side, and the side surface wiring is provided on the inclined surface. Semiconductor element. 3. The method according to claim 2 , further comprising: a side surface sealing film extending in a direction crossing the lower surface of the semiconductor substrate so as to cover the side surface wiring on the inclined surface on which the side surface wiring is formed. A featured semiconductor element.   2. The semiconductor element according to claim 1, wherein the external connection electrode is a columnar electrode.   2. The semiconductor device according to claim 1, further comprising a lower overcoat film that covers other than the connection pad portion of the lower wiring. A semiconductor device in which first and second semiconductor structures are stacked,
The first semiconductor structure includes a semiconductor substrate;
A plurality of upper layer wirings provided on the semiconductor substrate;
A plurality of lower layer wirings provided under the semiconductor substrate,
And, at least one end portion end surface of the upper layer wiring is exposed to be flush with the side surface of the semiconductor substrate, and at least one end portion end surface of the lower layer wiring is exposed to be flush with the side surface of the semiconductor substrate. Side wiring is provided on the side surface of the semiconductor substrate so as to be connected to the end surface of the exposed upper layer wiring and the end surface of the exposed lower wiring, and is wider than the side wiring. The film corresponds to the position of the side wiring and is provided between the side surface of the semiconductor substrate and the side wiring ,
The second semiconductor structure includes a semiconductor substrate;
A plurality of external connection electrodes provided on the semiconductor substrate;
Comprising a solder ball provided on the external connection electrode,
By the solder balls of the second semiconductor structure body is joined to the connection pad portions of the lower layer wiring of said first semiconductor structure, said first semiconductor structure to said second semiconductor structure body on the A semiconductor device which is mounted. In the invention according to claim 6 , the side surface of the first semiconductor structure is an inclined surface that is gradually located on the inner side from the lower side toward the upper side, and the side surface wiring is provided on the inclined surface. A semiconductor device. 8. The side surface sealing film according to claim 7 , wherein the inclined surface of the first semiconductor structure including the side wiring extends in a direction in which the side surface intersects the lower surface of the first semiconductor structure. A semiconductor device which is covered with The invention according to claim 6 , wherein the first semiconductor structure includes a columnar electrode provided on a connection pad portion of an upper layer wiring, a sealing film provided around the columnar electrode, and the columnar electrode. A semiconductor device comprising a solder ball provided on an electrode. 7. The semiconductor device according to claim 6 , wherein the first semiconductor structure has a lower overcoat film that covers other than the connection pad portion of the lower layer wiring. 7. The invention according to claim 6 , wherein the second semiconductor structure includes an upper layer wiring as the external connection electrode, a columnar electrode provided on a connection pad portion of the upper layer wiring, and a periphery of the columnar electrode. And a solder film provided on the columnar electrode. In the invention of claim 11 ,
The second semiconductor structure has a plurality of lower layer wirings provided under the semiconductor substrate,
In addition, at least one end edge of the upper layer wiring is exposed to be flush with the side surface of the semiconductor substrate, and at least one end edge of the lower layer wiring is exposed to the side surface of the semiconductor substrate. The side wiring on the side surface of the semiconductor substrate is provided connected to one end end face of the exposed upper layer wiring and one end end face of the exposed lower layer wiring ; and A semiconductor device comprising: a side insulating film having a width wider than that of the side wiring and corresponding to the position of the side wiring and provided between the side surface of the semiconductor substrate and the side wiring . In the invention described in claim 12 , the side surface of the second semiconductor structure is an inclined surface that is gradually located on the inner side from the lower side toward the upper side, and the side surface wiring is provided on the inclined surface. A semiconductor device. 14. The side surface sealing film according to claim 13 , wherein the inclined surface of the second semiconductor structure including the side surface wiring has a side surface extending in a direction intersecting with the lower surface of the second semiconductor structure. A semiconductor device which is covered with 13. The semiconductor device according to claim 12 , wherein the second semiconductor structure has a lower overcoat film covering other than the connection pad portion of the lower layer wiring. A plurality of upper layer wirings are formed on the upper surface of the semiconductor wafer by extending at least a part thereof into a region corresponding to the dicing street, and a plurality of lower layer wirings are formed on the lower surface of the semiconductor wafer. Extending to the corresponding region and forming;
Attaching the lower surface side of the lower layer wiring to the upper surface of the dicing tape;
Cutting the semiconductor wafer in a region corresponding to at least the dicing street to form grooves to separate the individual semiconductor components, and forming the upper layer wiring formed in at least the region corresponding to the dicing street; and Cutting and removing the lower layer wiring to expose the cut surface; and
Forming a side wiring on the side surface of the semiconductor structure exposed through the groove by connecting to a cut surface of the upper layer wiring and a cut surface of the lower layer wiring;
Before the step of forming the side wiring, a side insulating film wider than the side wiring is formed on the side surface of the semiconductor structure exposed through the groove so as to correspond to the position of the side wiring. And forming the semiconductor substrate so as to be provided between the side surface of the semiconductor substrate and the side surface wiring,
Peeling the semiconductor structure from the dicing tape;
A method for manufacturing a semiconductor device, comprising: 17. The method according to claim 16 , wherein the groove is formed in a region corresponding to the dicing street. 18. The method of manufacturing a semiconductor element according to claim 17 , further comprising a step of expanding the dicing tape by extending the dicing tape in the peripheral direction after the groove is formed. 18. The groove according to claim 17 , wherein the groove is gradually inclined to the inner side as the side surfaces of the semiconductor structure individually separated from the lower side to the upper side are divided into regions corresponding to the dicing street and both sides thereof. A method for manufacturing a semiconductor element, wherein the semiconductor element is formed to be a surface. 20. The method of manufacturing a semiconductor element according to claim 16 , wherein the side wiring is formed using an ink jet head. The invention according to claim 19 ,
Before the step of peeling the semiconductor structure from the dicing tape,
Forming a side surface sealing film in the groove and covering the inclined surface of the semiconductor structure including the side surface wiring and the side surface insulating film with the side surface sealing film;
And a step of cutting the side surface sealing film at a central portion in the width direction thereof. A plurality of upper layer wirings are formed on the upper surface of the semiconductor wafer by extending at least a part thereof into a region corresponding to the dicing street, and a plurality of lower layer wirings are formed on the lower surface of the semiconductor wafer. Extending to the corresponding region and forming;
Attaching the lower surface side of the lower layer wiring to the upper surface of the dicing tape;
Cutting the semiconductor wafer in a region corresponding to at least the dicing street to form grooves to separate the individual semiconductor components, and forming the upper layer wiring formed in at least the region corresponding to the dicing street; and Cutting and removing the lower layer wiring to expose the cut surface; and
Forming a side wiring on the side surface of the semiconductor structure exposed through the groove by connecting to a cut surface of the upper layer wiring and a cut surface of the lower layer wiring;
Before the step of forming the side wiring, a side insulating film wider than the side wiring is formed on the side surface of the semiconductor structure exposed through the groove so as to correspond to the position of the side wiring. And forming the semiconductor substrate so as to be provided between the side surface of the semiconductor substrate and the side surface wiring,
Peeling the semiconductor structure from the dicing tape;
Another part having a semiconductor substrate, a plurality of external connection electrodes provided on the semiconductor substrate, and solder balls provided on the external connection electrodes under the semiconductor structure peeled from the dicing tape Bonding the solder ball to the connection pad portion of the lower layer wiring of the semiconductor structure, and placing the semiconductor structure;
A method for manufacturing a semiconductor device, comprising: 23. The method of manufacturing a semiconductor device according to claim 22 , wherein the groove is formed in a region corresponding to the dicing street. 24. The method of manufacturing a semiconductor device according to claim 23 , further comprising a step of expanding the dicing tape by extending the dicing tape in a peripheral direction after the groove is formed. 23. The invention according to claim 22 , wherein the groove is inclined inwardly as the side surfaces of the semiconductor structure individually separated from the lower side to the upper side are divided into regions corresponding to the dicing street and both sides thereof. A method for manufacturing a semiconductor device, wherein the semiconductor device is formed to have a surface. 26. The method of manufacturing a semiconductor device according to claim 22 , wherein the side wiring is formed using an ink jet head. 27. The method of manufacturing a semiconductor device according to claim 22 , wherein the side surface insulating film is formed using an ink jet head. In the invention of claim 25 ,
Before the step of peeling the semiconductor structure from the dicing tape,
Forming a side surface sealing film in the groove and covering the inclined surface of the semiconductor structure including the side surface wiring and the side surface insulating film with the side surface sealing film;
And a step of cutting the side surface sealing film at a central portion in the width direction thereof.

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