JP5034285B2 - 多層配線基板及び特性インピーダンスの測定方法 - Google Patents
多層配線基板及び特性インピーダンスの測定方法 Download PDFInfo
- Publication number
- JP5034285B2 JP5034285B2 JP2006080124A JP2006080124A JP5034285B2 JP 5034285 B2 JP5034285 B2 JP 5034285B2 JP 2006080124 A JP2006080124 A JP 2006080124A JP 2006080124 A JP2006080124 A JP 2006080124A JP 5034285 B2 JP5034285 B2 JP 5034285B2
- Authority
- JP
- Japan
- Prior art keywords
- test coupon
- signal wiring
- wiring board
- multilayer wiring
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 19
- 238000005259 measurement Methods 0.000 claims description 25
- 238000002847 impedance measurement Methods 0.000 claims description 7
- 238000005452 bending Methods 0.000 claims description 6
- 239000000523 sample Substances 0.000 description 4
- 238000000691 measurement method Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2818—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2813—Checking the presence, location, orientation or value, e.g. resistance, of components or conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09263—Meander
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Measurement Of Resistance Or Impedance (AREA)
Description
前記テストクーポンが、相互に平行に延びる複数の直線部と該複数の直線部を相互につなぐ折り返し部とから構成され、前記折り返し部は複数の折れ曲がり部から構成され、該折れ曲がり部の曲がり角度が45°以下である、ことを特徴とする。
Z0=50×電圧/(1−電圧) (1)
で表される。この(1)式に基づいて、パターン配線部の反射時間領域の電圧値から、各パターン配線部51のインピーダンスが算出できる。
11:パターン配線部(テストクーポン)
12:直線部
13:折り返し部
14:測定用パッド(テストクーポン用)
15:スルーホール
16:測定用パッド(グランド用)
17:開放端
18:スルーホール
20:コーナー部
21:折れ曲がり部
22:斜辺
Claims (5)
- 複数の信号配線層及び少なくとも1層のグランド層を有する多層配線基板において、
各信号配線層に形成したインピーダンス測定用のテストクーポンと、
前記各信号配線層のテストクーポンを直列に接続するスルーホールと、
前記直列に接続されたテストクーポンの一端に接続された測定用パッド、及び、前記グランド層に接続された測定用パッドとを備え、
前記テストクーポンは、相互に平行に延びる複数の直線部と該複数の直線部を相互につなぐ折り返し部とから構成され、
前記折り返し部は、複数の折れ曲がり部から構成され、該折れ曲がり部の曲がり角度が45°以下である、
ことを特徴とする多層配線基板。 - 前記各信号配線層に形成したテストクーポンを、多層配線基板の積層方向に実質的に重なり合うように配置した、
ことを特徴とする請求項1に記載の多層配線基板。 - 信号配線層にテストクーポンを形成した多層配線基板において、
前記テストクーポンが、相互に平行に延びる複数の直線部と該複数の直線部を相互につなぐ折り返し部とから構成され、
前記折り返し部は複数の折れ曲がり部から構成され、該折れ曲がり部の曲がり角度が45°以下である、
ことを特徴とする多層配線基板。 - 複数の信号配線層及び少なくとも1層のグランド層を有する多層配線基板の前記信号配線層の特性インピーダンスを測定する方法において、
各信号配線層に相互に平行に延びる複数の直線部と該複数の直線部を相互につなぐ折り返し部とから構成され、前記折り返し部を、複数の折れ曲がり部から構成し、各折れ曲がり部の曲がり角度を45°以下としたインピーダンス測定用のテストクーポンを形成し、
前記各信号配線層のテストクーポンを直列に接続し、該直列に接続されたテストクーポンの一端に接続された測定用パッドと、前記グランド層に接続された測定用パッドとの間にステップパルスを印加し、
前記直列に接続された各テストクーポンからの反射波の電圧を測定する、
ことを特徴とする特性インピーダンスの測定方法。 - 前記各信号配線層に形成したテストクーポンを、多層配線基板の積層方向に実質的に重なり合うように配置する、
ことを特徴とする請求項4に記載の特性インピーダンスの測定方法。
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006080124A JP5034285B2 (ja) | 2006-03-23 | 2006-03-23 | 多層配線基板及び特性インピーダンスの測定方法 |
| TW096108942A TW200746931A (en) | 2006-03-23 | 2007-03-15 | Multilayer printed wiring board and method of measuring characteristic impedance |
| KR1020070027508A KR100855815B1 (ko) | 2006-03-23 | 2007-03-21 | 다층 인쇄 배선 기판 및 특성 임피던스의 측정 방법 |
| US11/723,606 US20070222473A1 (en) | 2006-03-23 | 2007-03-21 | Multilayer printed wiring board and method of measuring characteristic impedance |
| CN2007100900541A CN101043790B (zh) | 2006-03-23 | 2007-03-23 | 多层印刷布线板和测量特性阻抗的方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006080124A JP5034285B2 (ja) | 2006-03-23 | 2006-03-23 | 多層配線基板及び特性インピーダンスの測定方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2007258400A JP2007258400A (ja) | 2007-10-04 |
| JP5034285B2 true JP5034285B2 (ja) | 2012-09-26 |
Family
ID=38532706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006080124A Expired - Fee Related JP5034285B2 (ja) | 2006-03-23 | 2006-03-23 | 多層配線基板及び特性インピーダンスの測定方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20070222473A1 (ja) |
| JP (1) | JP5034285B2 (ja) |
| KR (1) | KR100855815B1 (ja) |
| CN (1) | CN101043790B (ja) |
| TW (1) | TW200746931A (ja) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4377939B2 (ja) * | 2007-12-25 | 2009-12-02 | 株式会社東芝 | プリント配線板およびその製造方法 |
| CN101762750B (zh) * | 2008-12-25 | 2011-10-26 | 上海北京大学微电子研究院 | 通孔电阻测量结构及方法 |
| US8242784B2 (en) | 2009-12-07 | 2012-08-14 | International Business Machines Corporation | Qualifying circuit board materials |
| CN101923142A (zh) * | 2010-08-02 | 2010-12-22 | 浪潮电子信息产业股份有限公司 | 一种测试测试元件摆放方法 |
| JP2012037314A (ja) * | 2010-08-05 | 2012-02-23 | Fujitsu Ltd | 評価用基板および基板評価方法 |
| JP6149382B2 (ja) * | 2012-11-01 | 2017-06-21 | 日本電気株式会社 | 特性インピーダンス管理用テストクーポンおよびこれを備えたプリント基板 |
| CN104378909A (zh) * | 2013-08-12 | 2015-02-25 | 英业达科技有限公司 | 印刷电路板 |
| CN105228378B (zh) * | 2015-08-31 | 2019-03-08 | 北大方正集团有限公司 | 一种电路板及其阻抗量测方法 |
| CN105338728B (zh) * | 2015-10-23 | 2018-11-09 | 北大方正集团有限公司 | 一种电路板阻抗测量方法及一种电路板 |
| RU2646550C2 (ru) * | 2016-06-29 | 2018-03-05 | Федеральное государственное бюджетное образовательное учреждение высшего образования Московский авиационный институт (национальный исследовательский университет) (МАИ) | Тест-купон и способ контроля погрешностей совмещения слоев многослойной печатной платы |
| US10303838B2 (en) | 2017-06-02 | 2019-05-28 | International Business Machines Corporation | Dynamic impedance net generation in printed circuit board design |
| CN107328998B (zh) * | 2017-07-07 | 2020-06-23 | 联想(北京)有限公司 | 测量多层印刷电路板介电常数的方法和系统 |
| CN109548271B (zh) * | 2018-11-14 | 2021-04-02 | 江门崇达电路技术有限公司 | 一种用于信号发生器的印制电路板的制作方法 |
| US10334720B1 (en) * | 2018-12-04 | 2019-06-25 | Greater Asia Pacific Limited | Printed circuit board test coupon for electrical testing during thermal exposure and method of using the same |
| US10379153B1 (en) | 2018-12-04 | 2019-08-13 | Greater Asia Pacific Limited | Printed circuit board test coupon for electrical testing during thermal exposure and method of using the same |
| CN109496061A (zh) * | 2018-12-10 | 2019-03-19 | 浪潮(北京)电子信息产业有限公司 | 一种电路板的损坏判别方法和系统 |
| CN109561574B (zh) * | 2018-12-24 | 2020-06-23 | 广州兴森快捷电路科技有限公司 | 阻抗测试、线路板加工、线路板生产方法及测试组件 |
| CN112188725B (zh) * | 2020-09-25 | 2021-10-08 | 深圳市景旺电子股份有限公司 | 印刷电路板的阻抗测试模块及印刷电路板的制作方法 |
| CN112714541B (zh) * | 2020-12-14 | 2022-05-31 | 竞华电子(深圳)有限公司 | 一种多层pcb板结构及测试方法 |
| CN112730987A (zh) * | 2020-12-15 | 2021-04-30 | 红板(江西)有限公司 | 一种pcb板阻抗快速测量方法 |
| CN114397482A (zh) * | 2021-12-20 | 2022-04-26 | 百及纳米科技(上海)有限公司 | 探针装置与探针控制设备 |
| USD997896S1 (en) * | 2022-01-18 | 2023-09-05 | Jiarui Zhu | Flexible printed circuit board |
| CN114740397A (zh) * | 2022-02-28 | 2022-07-12 | 广州广合科技股份有限公司 | 多层电路板的导通孔检测方法以及检测模块 |
| KR102911631B1 (ko) * | 2023-12-15 | 2026-01-13 | 한국과학기술원 | 패드 및 비아-홀 디임베딩 기법이 적용된 임피던스 측정장치 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3494476B2 (ja) * | 1994-07-29 | 2004-02-09 | 沖電気工業株式会社 | プリント配線基板 |
| JP3528363B2 (ja) * | 1995-10-13 | 2004-05-17 | ヤマハ株式会社 | 試験用半導体装置の評価方法 |
| JP4034888B2 (ja) * | 1998-10-30 | 2008-01-16 | イビデン株式会社 | プリント配線板におけるテストクーポン |
| KR20000045926A (ko) * | 1998-12-30 | 2000-07-25 | 김영환 | 다층 인쇄회로기판의 임피던스 테스트 쿠폰 |
| JP4268266B2 (ja) * | 1999-06-10 | 2009-05-27 | 日本特殊陶業株式会社 | 配線基板の導体層形成工程の検査方法 |
| JP2001251061A (ja) * | 2000-03-02 | 2001-09-14 | Sony Corp | 多層型プリント配線基板 |
| KR100348409B1 (ko) * | 2000-12-29 | 2002-08-10 | 삼성전자 주식회사 | 복수의 패턴층을 갖는 테스트 쿠폰 및 이를 이용한 메모리모듈 기판의 유전율 측정 방법 |
| JP4079699B2 (ja) * | 2001-09-28 | 2008-04-23 | 富士通株式会社 | 多層配線回路基板 |
| US6825672B1 (en) * | 2002-06-07 | 2004-11-30 | Marvell International Ltd. | Cable tester |
| US7129577B2 (en) * | 2003-02-27 | 2006-10-31 | Power-One, Inc. | Power supply packaging system |
| CN1317923C (zh) * | 2003-09-29 | 2007-05-23 | 财团法人工业技术研究院 | 一种具内藏电容的基板结构 |
| KR200354810Y1 (ko) | 2003-12-31 | 2004-06-30 | 노틸러스효성 주식회사 | 인쇄회로기판의 임피던스 테스트 쿠폰 |
-
2006
- 2006-03-23 JP JP2006080124A patent/JP5034285B2/ja not_active Expired - Fee Related
-
2007
- 2007-03-15 TW TW096108942A patent/TW200746931A/zh unknown
- 2007-03-21 KR KR1020070027508A patent/KR100855815B1/ko not_active Expired - Fee Related
- 2007-03-21 US US11/723,606 patent/US20070222473A1/en not_active Abandoned
- 2007-03-23 CN CN2007100900541A patent/CN101043790B/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101043790A (zh) | 2007-09-26 |
| CN101043790B (zh) | 2011-04-20 |
| KR100855815B1 (ko) | 2008-09-01 |
| TW200746931A (en) | 2007-12-16 |
| KR20070096836A (ko) | 2007-10-02 |
| US20070222473A1 (en) | 2007-09-27 |
| JP2007258400A (ja) | 2007-10-04 |
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