JP5034752B2 - Drive signal generator - Google Patents

Description

  The present invention relates to a drive signal generation device and a drive signal generation method.

  A drive signal generation device that converts digital data into an analog signal and generates a drive signal by performing current amplification of the analog signal is incorporated in, for example, an inkjet printer (a type of liquid ejection device) having a piezoelectric element.

  A current amplification transistor is used for current amplification of the analog signal. In this configuration, the power consumption of the transistor during current amplification becomes a problem. In view of this point, an apparatus provided with a plurality of capacitors has been proposed in order to suppress the power consumption of the transistor (see Patent Document 1).

In this device, the charge discharged from the current amplification transistor is stored in a capacitor, and the charge stored in the capacitor is supplied to the current amplification transistor. For this reason, an electric charge can be used effectively and power consumption can be suppressed.
JP 2000-238294 A

  By the way, the potential of the capacitor in the above-described apparatus is determined by the balance between the charge discharged from the current amplification transistor and the charge supplied to the current amplification transistor. For this reason, there is a problem that it takes time until the capacitor is sufficiently charged, and it is difficult to obtain an effect of suppressing power consumption at an early stage.

  This invention is made | formed in view of such a situation, The objective is to obtain the suppression effect of electric power consumption at an early stage.

The main invention for achieving the object is as follows:
(A) an analog signal converter for converting digital data into an analog signal;
(B) a current amplification unit that generates a drive signal by amplifying the current of the analog signal, the current amplification unit including a transistor for current amplification;
(C) a plurality of types of power supply circuits having different voltages;
(D) a circuit selection unit that selects a power supply circuit used for current amplification of the analog signal from the plurality of types of power supply circuits based on the potential of the analog signal;
A drive signal generation device having (E).

  Other features of the present invention will become apparent from the description of this specification and the accompanying drawings.

At least the following will be made clear by the description of the present specification and the accompanying drawings.
That is, (A) an analog signal conversion unit that converts digital data into an analog signal, and (B) a current amplification unit that generates a drive signal by amplifying the current of the analog signal, and includes a transistor for current amplification. (C) a plurality of types of power supply circuits having different voltages; and (D) a power supply circuit used for current amplification of the analog signal among the plurality of types of power supply circuits. It is clarified that a drive signal generation device having a circuit selection unit and (E) to be selected based on the above can be realized.
According to such a drive signal generation device, since the power supply circuit having a voltage suitable for the potential of the analog signal is used during current amplification of the analog signal, an effect of suppressing power consumption can be obtained early.

In such a drive signal generation device, the potential of the amplification current terminal on the side that is not for the drive signal among the pair of amplification current terminals included in the current amplification transistor is adjusted according to the potential of the analog signal. It is preferable to have a potential adjusting unit.
According to such a drive signal generation device, since the potential of the amplified current terminal on the side not for the drive signal is adjusted by the potential adjustment unit, the effect of suppressing power consumption can be further enhanced.

In this drive signal generation device, the current amplification transistor is an NPN transistor that operates when the potential of the drive signal rises, and the analog signal is applied to the base, and the amplified current is output from the collector to the emitter. It is preferable that the potential adjusting unit adjusts the collector potential of the NPN transistor so as to be higher than the potential of the analog signal by a predetermined potential.
According to such a drive signal generation device, power consumption in the NPN type transistor can be suppressed.

In this drive signal generation device, the current amplification transistor is a PNP transistor that operates when the potential of the drive signal drops, and the analog signal is applied to the base, and the amplified current is collected from the emitter to the collector. Preferably, the potential adjusting unit adjusts the collector potential of the PNP transistor so as to be lower than the potential of the analog signal by a predetermined potential.
According to such a drive signal generation device, power consumption in the PNP transistor can be suppressed.

In this drive signal generation device, the plurality of types of power supply circuits are a main power supply circuit having the highest voltage and another power supply circuit having a voltage lower than the highest voltage, and a power supply capacity is a power supply of the main power supply circuit. It is preferable to have another power supply circuit smaller than the capacity.
According to such a drive signal generation device, the certainty of operation can be ensured.

The drive signal generation device may include a storage element that is charged by a power source generated by the other power supply circuit and is discharged by an operation of the current amplification transistor when the potential of the drive signal is increased. preferable. In addition, it is preferable that the power storage element is also charged by the electric charge discharged from the current amplification transistor when the potential of the drive signal drops.
According to such a drive signal generation device, the effect of suppressing power consumption can be enhanced.

It is also clarified that the following drive signal generation method can be realized.
That is, (A) generating a plurality of types of power supplies having different voltages by different power supply circuits, (B) converting digital data into an analog signal, (C) based on the potential of the analog signal, Selecting a specific power supply circuit from among the power supply circuits; (D) using the power supply generated by the selected power supply circuit to amplify the current of the analog signal by a current amplification transistor to generate a drive signal; In addition, it becomes clear that the drive signal generation method having (E) can be realized.

=== First Embodiment ===
<About drive signal generator>
The drive signal generation device generates a drive signal applied to an element to be controlled. This drive signal generation device is incorporated in, for example, a liquid ejection device that ejects liquid. Examples of the liquid ejecting apparatus include a printing apparatus, a color filter manufacturing apparatus, a display manufacturing apparatus, a semiconductor manufacturing apparatus, and a DNA chip manufacturing apparatus. In this specification, a liquid ejection apparatus in which a drive signal generation apparatus is incorporated will be described as an example. Specifically, an ink jet printer (hereinafter also simply referred to as a printer) as a printing apparatus will be described as an example.

=== Overall structure ===
<About the printer>
FIG. 1 is a block diagram illustrating the configuration of the printer 1. The illustrated printer 1 includes a paper transport mechanism 10, a carriage moving mechanism 20, a drive signal generation circuit 30, a head unit 40, a detector group 50, a printer-side controller 60, and a power generation unit 70.

  The paper transport mechanism 10 transports paper as a medium in the transport direction. The carriage moving mechanism 20 moves the head unit 40 in a predetermined direction (for example, the paper width direction). The head 42 of the head unit 40 ejects ink, which is a kind of liquid, toward the paper. The drive signal generation circuit 30 generates a drive signal COM. This drive signal COM is used at the time of printing on paper, and is a series of signals including, for example, the ejection pulse PS shown in FIG.

  The head unit 40 includes a head control unit 41 and a head 42. As shown in FIG. 2, the head 42 includes a piezo element 421. The piezo element 421 corresponds to an element that operates to discharge liquid, and a plurality of piezo elements 421 are provided according to nozzles (not shown) of the head 42. For example, 96 to 180 piezoelectric elements 421 are provided corresponding to one color ink. The piezo element 421 is a kind of capacitive element (capacitive load) capable of holding electric charge, and is deformed along with charge / discharge. Due to this deformation, the piezo element 421 causes a pressure change in the ink stored in a pressure chamber (not shown) in the head 42. This pressure change causes ink to be ejected from the nozzles.

  The head controller 41 selectively applies a necessary part of the drive signal COM generated by the drive signal generation circuit 30 to the piezo element 421. For this reason, the head control unit 41 includes a plurality of switches 411 provided for each piezo element 421 in the middle of the supply line of the drive signal COM. The head control unit 41 controls each switch 411 to selectively apply a necessary portion of the drive signal COM to the piezo element 421. At this time, a desired amount of ink can be ejected from the nozzles depending on how to select the necessary portion.

  The detector group 50 includes a plurality of detectors that monitor the status of the printer 1. Detection results by these detectors are output to the printer-side controller 60. The printer-side controller 60 controls the control target unit based on the print data transmitted from the computer CP and the detection results output from each detector, and prints an image on paper. The printer controller 60 will be described later.

  The power supply generation unit 70 generates power to be supplied to the current amplification transistors (NPN type transistor 32 a and PNP type transistor 32 b) included in the drive signal generation circuit 30. The power generation unit 70 will also be described later.

=== Main Parts of Printer 1 ===
<About the printer-side controller 60>
The printer-side controller 60 performs overall control in the printer 1. For example, the printer-side controller 60 controls the paper transport mechanism 10, the carriage movement mechanism 20, the drive signal generation circuit 30, and the head unit 40. As shown in FIG. 1, the printer-side controller 60 includes an interface unit 61, a CPU 62, a memory 63, and a control unit 64. The interface unit 61 exchanges data with the computer CP, which is an external device. The CPU 62 is an arithmetic processing unit for performing overall control of the printer 1. The memory 63 is used as an area for storing a computer program, a work area, or the like, and includes a storage element such as a RAM, an EEPROM, or a ROM. The CPU 62 controls each control target unit according to the computer program stored in the memory 63. For example, the CPU 62 controls the paper transport mechanism 10 and the carriage movement mechanism 20 via the control unit 64. Further, the CPU 62 transmits a head control signal for controlling the operation of the head 42 to the head control unit 41, and transmits a control signal for generating the drive signal COM to the drive signal generation circuit 30.

  The control signal for generating the drive signal COM is also called DAC data and is composed of multi-bit digital data. The DAC data of this embodiment is composed of 10-bit digital data. This DAC data is data for determining the voltage of the potential waveform signal COM ′ (corresponding to an analog signal) generated by the waveform generation circuit 31 (see FIG. 2) included in the drive signal generation circuit 30. This DAC data indirectly indicates the voltage value of the drive signal COM, and corresponds to waveform generation information for determining the potential waveform of the drive signal COM. The content of the DAC data is updated every extremely short update cycle (for example, every 0.04 μs). This DAC data is stored in a predetermined area of the memory 63, and is read out by the CPU 62 when the drive signal COM is generated. In this case, the predetermined area of the memory 63 corresponds to a DAC data storage unit. The read DAC data is transmitted through the signal line and received by the drive signal generation circuit 30 (specifically, the waveform generation circuit 31).

<About the power generation unit 70>
The power generation unit 70 generates a power used for driving the head in the printer 1. As shown in FIG. 2, in the printer 1, a plurality of types of power supplies having different voltages are generated by different power supply circuits. That is, the first power supply is a power supply of 42 V, which is the highest voltage, and is generated by the first power supply circuit 71. The first power supply circuit 71 corresponds to a main power supply circuit. The second power source is a 28V power source, which is the second highest voltage, and is generated by the second power source circuit 72. The third power supply is a power supply of 14 V, which is the lowest voltage, and is generated by the third power supply circuit 73. The second power supply circuit 72 and the third power supply circuit 73 correspond to other power supply circuits. Since the first power supply circuit 71 generates power with reference to the ground, the potential of the power supply terminal is 42V. Similarly, the potential of the power supply terminal included in the second power supply circuit 72 is 28V, and the potential of the power supply terminal included in the third power supply circuit 73 is 14V.

  The power supply terminal of the first power supply circuit 71 is connected to the collector of the first NPN transistor 33a and the collector of the second NPN transistor 33b of the first potential adjustment circuit 33. Further, the second potential adjusting circuit 34 is also connected to the collector of the second NPN transistor 34b. The power supply terminal of the second power supply circuit 72 is connected to the collector of the first NPN transistor 34 a included in the second potential adjustment circuit 34 via the first Schottky barrier diode 81, and via the third Schottky barrier diode 83. The current amplifier circuit 32 is connected to the collector of a PNP transistor 32b. The power supply terminal of the third power supply circuit 73 is connected to the collector of the NPN transistor 32 a included in the current amplifier circuit 32 via the second Schottky barrier diode 82 and is connected to the third power supply via the fourth Schottky barrier diode 84. The potential adjustment circuit 35 is connected to the collector of the first PNP transistor 35a.

  In the present embodiment, the power supply capacity of the first power supply circuit 71 is larger than the power supply capacity of the second power supply circuit 72 or the third power supply circuit 73. The output is determined so that at least current amplification of the potential waveform signal COM ′ (analog signal) can be performed. With such a configuration, even if the supply capability of the second power supply circuit 72 or the third power supply circuit 73 is insufficient at the time of current amplification of the potential waveform signal COM ′, current amplification is performed without any problem. Can be performed. Therefore, the certainty of the current amplification operation in the drive signal generation circuit 30 can be ensured.

<About the drive signal generation circuit 30>
The drive signal generation circuit 30 corresponds to a drive signal generation unit that generates the drive signal COM. As shown in FIG. 2, the drive signal generation circuit 30 includes a waveform generation circuit 31, a current amplification circuit 32, and a potential adjustment circuit (first potential adjustment circuit 33 to fourth potential adjustment circuit 36).

<About Waveform Generation Circuit 31>
The waveform generation circuit 31 generates a potential waveform signal COM ′ having a potential change pattern determined by DAC data (waveform generation information). The potential waveform signal COM ′ is a signal having a potential waveform that is the basis of the drive signal COM. The waveform generation circuit 31 has a digital-analog converter, and converts DAC data that is digital data into a potential waveform signal COM ′ that is an analog signal. Therefore, the waveform generation circuit 31 corresponds to an analog signal conversion unit that converts digital data into an analog signal.

<About the current amplifier circuit 32>
The current amplifying circuit 32 corresponds to a current amplifying unit, amplifies the current of the potential waveform signal COM ′ that is an analog signal, and outputs it as a drive signal COM. The current amplification circuit 32 includes an NPN transistor 32a and a PNP transistor 32b that are complementarily connected as current amplification transistors.

  The NPN transistor 32a is a transistor that operates when the potential of the drive signal COM rises (when the piezo element 421 is charged during printing). The NPN transistor 32a has a collector connected to a current source and an emitter connected to a drive signal COM supply line. The base of the NPN transistor 32a is connected to the supply line of the potential waveform signal COM ′. Of these terminals, the base corresponds to an analog signal terminal, and the collector and emitter correspond to an amplified current terminal. Further, the emitter corresponds to a drive signal COM terminal, and the collector corresponds to a current supply terminal.

  The PNP transistor 32b is a transistor that operates when the potential of the drive signal COM drops (also when the piezo element 421 is discharged). The PNP transistor 32b has an emitter connected to the supply line for the drive signal COM and a collector connected to the charge discharge path. The base of the PNP transistor 32b is connected to the supply line of the potential waveform signal COM ′. Of these terminals, the base corresponds to an analog signal terminal, and the collector and emitter correspond to an amplified current terminal. Further, the emitter corresponds to a drive signal COM terminal and corresponds to a charge discharge terminal.

  In the current amplifier circuit 32, the operation of each of the transistors 32a and 32b is controlled by the potential waveform signal COM ′ applied to each base terminal. As a result, the potential waveform of the drive signal COM output from the current amplifier circuit 32 follows the potential waveform of the potential waveform signal COM ′.

<About the potential adjustment circuit>
The potential adjustment circuit corresponds to a potential adjustment unit, and adjusts the collector potential of the NPN transistor 32a and the collector potential of the PNP transistor 32b included in the current amplification circuit 32 according to the potential of the potential waveform signal COM ′. The potential adjustment circuit also functions as a circuit selection unit. That is, the potential adjustment circuit selects a power supply circuit used for current amplification of the potential waveform signal COM ′ from among the plurality of types of power supply circuits 71 to 73 based on the potential of the potential waveform signal COM ′.

  The printer 1 includes a first potential adjustment circuit 33, a second potential adjustment circuit 34, a third potential adjustment circuit 35, and a fourth potential adjustment circuit 36 as potential adjustment circuits. Among these potential adjustment circuits, the first potential adjustment circuit 33 and the second potential adjustment circuit 34 adjust the collector potential of the NPN transistor 32a. Accordingly, the first potential adjustment circuit 33 and the second potential adjustment circuit 34 correspond to a supply-side terminal potential adjustment unit. The third potential adjustment circuit 35 and the fourth potential adjustment circuit 36 adjust the collector potential of the PNP transistor 32b. Therefore, the third potential adjustment circuit 35 and the fourth potential adjustment circuit 36 correspond to the emission-side terminal potential adjustment unit.

<Regarding First Potential Adjustment Circuit 33>
The first potential adjustment circuit 33 includes a first NPN transistor 33a, a second NPN transistor 33b, a diode 33c, a Zener diode 33d, a capacitor 33e, a first resistor 33f, and a second resistor 33g.

  The first NPN transistor 33 a has a collector connected to the power supply terminal of the first power supply circuit 71 and an emitter connected to the collector of the NPN transistor 32 a included in the current amplifier circuit 32. The cathode of the diode 33c is connected to the base of the first NPN transistor 33a. The second NPN transistor 33b has a collector connected to the power supply terminal of the first power supply circuit 71 and an emitter connected to the anode of the diode 33c. The cathode of the Zener diode 33d is connected to the base of the second NPN transistor 33b. In short, the first NPN transistor 33a and the second NPN transistor 33b are Darlington-connected. The diode 33c is provided to prevent an excessive reverse bias.

  The anode of the Zener diode 33d is connected to a supply line (signal output terminal of the waveform generation circuit 31) for the potential waveform signal COM ′. The Zener diode 33d sets the base potential of the second NPN transistor 33b to a potential that is higher by the Zener voltage than the potential of the potential waveform signal COM ′. In the printer 1, a Zener diode 33d having a Zener voltage of 3.6V is used.

  One end of the capacitor 33e is connected to the base of the second NPN transistor 33b, and the other end is connected to the supply line of the potential waveform signal COM ′. The first resistor 33f has one end connected to the power supply terminal of the first power supply circuit 71 and the other end connected to the base of the second NPN transistor 33b, and generates a voltage defined by the Zener diode 33d. The current is supplied to the second NPN transistor 33b. The capacitor 33e suppresses a rapid change in the base potential of the second NPN transistor 33b. The second resistor 33g is provided between the base and emitter of the first NPN transistor 33a.

  In the first potential adjustment circuit 33, the base potential of the second NPN transistor 33b is a predetermined amount (1.8V) higher than the collector potential of the NPN transistor 32a of the current amplifier circuit 32, that is, the emitter potential of the first NPN transistor 33a. When it becomes higher, the first NPN transistor 33a and the second NPN transistor 33b operate. That is, a current flows from the power supply terminal of the first power supply circuit 71 through the first NPN transistor 33a, thereby raising the collector potential of the NPN transistor 32a. In other words, current amplification of the potential waveform signal COM ′ is performed.

  The first potential adjustment circuit 33 in FIG. 2 includes two transistors 33a and 33b and one diode 33c. Therefore, when the operating voltage of each element is 0.6 V, the transistors 33 a and 33 b operate when the base potential of the second NPN transistor 33 b becomes 1.8 V or more higher than the collector potential of the NPN transistor 32 a (first Operation condition of 1 potential adjustment circuit 33). When the difference between these potentials becomes less than 1.8 V, the transistors 33a and 33b stop operating. Here, since the Zener voltage of the Zener diode 33d is 3.6V, the base potential of the second NPN transistor 33b is 3.6V higher than the potential of the potential waveform signal COM ′. Therefore, when the first potential adjustment circuit 33 operates, the collector potential of the NPN transistor 32a included in the current amplifier circuit 32 is about 1.8 V higher than the potential of the potential waveform signal COM ′.

<Regarding Second Potential Adjustment Circuit 34>
The configuration of the second potential adjustment circuit 34 is substantially the same as that of the first potential adjustment circuit 33. That is, the second potential adjustment circuit 34 includes a first NPN transistor 34a, a second NPN transistor 34b, a diode 34c, a Zener diode 34d, a capacitor 34e, a first resistor 34f, and a second resistor 34g. .

  The first NPN transistor 34a has a collector connected to the power supply terminal of the second power supply circuit 72 via the first Schottky barrier diode 81, and an emitter connected to the collector of the NPN transistor 32a included in the current amplification circuit 32. Yes. The cathode of the diode 34c is connected to the base of the first NPN transistor 34a. The second NPN transistor 34b has a collector connected to the power supply terminal of the first power supply circuit 71 and an emitter connected to the anode of the diode 34c. The cathode of the Zener diode 34d is connected to the base of the second NPN transistor 34b. The anode of the Zener diode 34d is connected to the supply line of the potential waveform signal COM ′. In the printer 1, a Zener diode 34d having a Zener voltage of 4.3V is used.

  One end of the capacitor 34e is connected to the base of the second NPN transistor 34b, and the other end is connected to the supply line of the potential waveform signal COM ′. The first resistor 34f has one end connected to the power supply terminal of the first power supply circuit 71 and the other end connected to the base of the second NPN transistor 34b, and generates a voltage defined by the Zener diode 34d. Is supplied to the second NPN transistor 34b. The capacitor 34e suppresses a rapid change in the base potential of the second NPN transistor 34b. The second resistor 34g is provided between the base and emitter of the first NPN transistor 34a.

  Also in the second potential adjusting circuit 34, when the base potential of the second NPN transistor 34b becomes higher than the collector potential of the NPN transistor 32a (the emitter potential of the first NPN transistor 34a) of the current amplifier circuit 32 by a predetermined amount or more. The first NPN transistor 34a and the second NPN transistor 34b operate, and the current waveform of the potential waveform signal COM ′ is amplified.

  Also in the second potential adjustment circuit 34 of FIG. 2, when the base potential of the second NPN transistor 34b becomes 1.8 V or more higher than the collector potential of the NPN transistor 32a, the transistors 34a and 34b operate (second potential adjustment circuit 34). Operating conditions). Then, when the difference between these potentials becomes less than 1.8 V, the transistors 34a and 34b stop operating. Here, since the Zener voltage of the Zener diode 34d is 4.3V, the base potential of the second NPN transistor 34b is 4.3V higher than the potential of the potential waveform signal COM ′. Therefore, when the second potential adjustment circuit 34 operates, the collector potential of the NPN transistor 32a included in the current amplifier circuit 32 is about 2.5 V higher than the potential of the potential waveform signal COM ′.

<Regarding Third Potential Adjustment Circuit 35>
The third potential adjustment circuit 35 includes a first PNP transistor 35a, a second PNP transistor 35b, a diode 35c, a Zener diode 35d, a capacitor 35e, a first resistor 35f, and a second resistor 35g.

  The first PNP transistor 35 a has an emitter connected to the collector of the PNP transistor 32 b included in the current amplifier circuit 32, and a collector connected to the power supply terminal of the third power supply circuit 73 via the fourth Schottky barrier diode 84. ing. The anode of the diode 35c is connected to the base of the first PNP transistor 35a. The second PNP transistor 35b has an emitter connected to the cathode of the diode 35c and a collector grounded. The anode of the Zener diode 35d is connected to the base of the second PNP transistor 35b.

  The cathode of the Zener diode 35d is connected to the supply line of the potential waveform signal COM ′. For this reason, the base potential of the second PNP transistor 35b is set lower than the potential of the potential waveform signal COM ′ by the Zener diode 35d by the Zener voltage. In the printer 1, a Zener diode 35d having a Zener voltage of 4.3V is used.

  One end of the capacitor 35e is connected to the supply line of the potential waveform signal COM ', and the other end is connected to the base of the second PNP transistor 35b. The first resistor 35f has one end connected to the base of the second PNP transistor 35b and the other end connected to the collector of the second PNP transistor 35b, and generates a voltage defined by the Zener diode 35d. The capacitor 35e suppresses a rapid change in the base potential of the second PNP transistor 35b. The second resistor 35g has one end connected to the emitter of the first PNP transistor 35a and the other end connected to the base of the first PNP transistor 35a.

  In the third potential adjustment circuit 35, when the base potential of the second PNP transistor 35b is lower than the collector potential of the PNP transistor 32b of the current amplifier circuit 32 (emitter potential of the first PNP transistor 35a) by a predetermined amount or more, The first PNP transistor 35a and the second PNP transistor 35b operate, and current amplification of the potential waveform signal COM ′ is performed.

  In the third potential adjusting circuit 35 of FIG. 2, when the operating voltage of the transistor or the like is 0.6V, each transistor is changed when the base potential of the second PNP transistor 35b becomes 1.8V or more lower than the collector potential of the PNP transistor 32b. 35a and 35b operate (operating conditions of the third potential adjusting circuit 35). When the difference between these potentials becomes less than 1.8 V, the transistors 35a and 35b stop operating. Here, since the Zener voltage of the Zener diode 35d is 4.3V, the base potential of the second PNP transistor 35b is 4.3V lower than the potential of the potential waveform signal COM ′. Therefore, when the third potential adjustment circuit 35 operates, the collector potential of the PNP transistor 32b included in the current amplifier circuit 32 is about 2.5 V lower than the potential of the potential waveform signal COM ′.

<Regarding Fourth Potential Adjustment Circuit 36>
The configuration of the fourth potential adjustment circuit 36 is substantially the same as that of the third potential adjustment circuit 35. That is, the fourth potential adjustment circuit 36 includes a first PNP transistor 36a, a second PNP transistor 36b, a diode 36c, a Zener diode 36d, a capacitor 36e, a first resistor 36f, and a second resistor 36g. .

  The first PNP transistor 36a has an emitter connected to the collector of a PNP transistor 32b included in the current amplifier circuit 32, and a collector grounded. The anode of the diode 36c is connected to the base of the first PNP transistor 36a. The second PNP transistor 36b has an emitter connected to the cathode of the diode 36c and a collector grounded. The anode of the Zener diode 36d is connected to the base of the second PNP transistor 36b.

  The cathode of the Zener diode 36d is connected to the supply line of the potential waveform signal COM ′. For this reason, the base potential of the second PNP transistor 36b is set lower by the Zener voltage than the potential of the potential waveform signal COM ′ by the Zener diode 36d. In the printer 1, a Zener diode 36d having a Zener voltage of 3.6V is used.

  One end of the capacitor 36e is connected to the supply line of the potential waveform signal COM ', and the other end is connected to the base of the second PNP transistor 36b. The first resistor 36f has one end connected to the base of the second PNP transistor 36b and the other end connected to the collector of the second PNP transistor 36b, and generates a voltage defined by the Zener diode 36d. The second resistor 36g has one end connected to the emitter of the first PNP transistor 36a and the other end connected to the base of the first PNP transistor 36a.

  Also in the fourth potential adjusting circuit 36, when the base potential of the second PNP transistor 36b becomes lower than the collector potential of the PNP transistor 32b of the current amplifier circuit 32 by a predetermined amount (for example, 1.8 V) or more, each of the transistors 36a and 36b. (Operating condition of the fourth potential adjusting circuit 36), and the current amplification of the potential waveform signal COM ′ is performed. Since the Zener voltage of the Zener diode 36d is 3.6V, when the fourth potential adjustment circuit 36 operates, the collector potential of the PNP transistor 32b included in the current amplification circuit 32 is about the potential of the potential waveform signal COM ′. 1.8V lower.

=== About operation ===
<Operation of each potential adjustment circuit>
Each of the potential adjusting circuits described above uses the potential waveform of the collector potential of the NPN transistor 32a and the collector potential of the PNP transistor 32b included in the current amplifier circuit 32 when the potential waveform signal COM ′ as an analog signal is amplified. Adjustment is made according to the potential of the signal COM ′. Hereinafter, the adjustment of the potential will be described.

<When the potential of the potential waveform signal COM ′ rises>
As described above, the power supply terminal of the third power supply circuit 73 is connected to the collector of the NPN transistor 32a via the second Schottky barrier diode 82. For this reason, the collector potential of the NPN transistor 32a does not become lower than the potential determined by the power supply generated by the third power supply circuit 73. In this example, if the power supply capability of the third power supply circuit 73 is sufficient and the loss due to the second Schottky barrier diode 82 can be ignored, the collector potential of the NPN transistor 32a is the power supply of the third power supply circuit 73. It is not less than the terminal potential of 14V.

  Therefore, when the potential of the potential waveform signal COM ′ is low and does not satisfy the operating conditions of the first potential adjustment circuit 33 and the second potential adjustment circuit 34, the third power supply circuit 73 is selected, as shown by a thick line in FIG. In addition, the power supply generated by the third power supply circuit 73 is used for current amplification of the potential waveform signal COM ′. In this case, the voltage between the collector and emitter of the NPN transistor 32a included in the current amplifier circuit 32 is the difference between the potential of the power supply terminal of the third power supply circuit 73 and the potential of the drive signal COM. , 72 is selected. Therefore, power consumption can be suppressed.

  As described above, the first potential adjustment circuit 33 operates when the base potential of the second NPN transistor 33b is higher than the collector potential of the NPN transistor 32a included in the current amplifier circuit 32 by a predetermined amount or more. The same applies to the second potential adjustment circuit 34. Here, the Zener voltage (4.3V) of the Zener diode 34d included in the second potential adjustment circuit 34 is larger than the Zener voltage (3.6V) of the Zener diode 33d included in the first potential adjustment circuit 33. The anode potentials of the Zener diodes 33d and 34d are common to the potential of the potential waveform signal COM ′. Further, since the base potential of the second NPN transistor 34b is higher than the base potential of the second NPN transistor 33b, and the emitter potentials of the first NPN transistor 34a and the first NPN transistor 33a are common, the second potential adjustment circuit 34 This preferentially operates over the first potential adjustment circuit 33. In this example, when the potential of the potential waveform signal COM ′ reaches 11.5V, the base potential of the second NPN transistor 34b included in the second potential adjustment circuit 34 becomes 15.8V. Since this base potential is 1.8V higher than 14V, which is the emitter potential of the first NPN transistor 34a, each transistor 34a, 34b included in the second potential adjustment circuit 34 satisfies the operating condition. At this time, the base potential of the second NPN transistor 33b included in the first potential adjustment circuit 33 is 14.1V. For this reason, the transistors 33a and 33b included in the first potential adjustment circuit 33 do not satisfy the operating conditions.

  Therefore, when the potential waveform signal COM ′ becomes 11.5 V or more, the second potential adjustment circuit 34 operates in preference to the first potential adjustment circuit 33 as shown by a thick line in FIG. The collector potential of the NPN transistor 32a is raised. At this time, the collector potential of the NPN transistor 32a is set to a potential approximately 2.5V higher than the potential of the potential waveform signal COM ′, as described in the section <About the second potential adjustment circuit 34>. Accordingly, the potential difference from the drive signal COM can be reduced, and power consumption in the NPN transistor 32a can be suppressed.

  The power supply terminal of the second power supply circuit 72 is connected to the collector of the first NPN transistor 34 a of the second potential adjustment circuit 34 via the first Schottky barrier diode 81. Therefore, it can be said that the second power supply circuit 72 is selected by the second potential adjustment circuit 34. The collector potential of the first NPN transistor 34a becomes the potential (28V) of the power supply terminal of the second power supply circuit 72 when the loss of the first Schottky barrier diode 81 is ignored. Therefore, the power consumption of the first NPN transistor 34a can be suppressed as compared with the case where the first power supply circuit 71 is used.

  Meanwhile, the first NPN transistor 34a of the second potential adjustment circuit 34 operates using the second power supply circuit 72 as a current source. For this reason, the potential that can be adjusted by the second potential adjustment circuit 34 has an upper limit. When the potential of the potential waveform signal COM ′ further rises when the collector potential of the NPN transistor 32a included in the current amplifier circuit 32 is at the upper limit value adjustable by the second potential adjustment circuit 34, the first potential adjustment circuit 33 operating conditions are satisfied. In this example, when the base potential of the second NPN transistor 33 b included in the first potential adjustment circuit 33 is 1.8 V or more higher than the collector potential of the NPN transistor 32 a included in the current amplification circuit 32, the first potential adjustment circuit 33. The operating conditions are satisfied. Assume that the upper limit value of the potential that can be adjusted by the second potential adjustment circuit 34 is 27 V, which is slightly lower than the voltage of the second power supply. In this case, when the potential of the potential waveform signal COM ′ reaches 25.2V, the base potential of the second NPN transistor 33b becomes 28.8V, which satisfies the operating condition of the first potential adjustment circuit 33.

  Therefore, when the potential of the potential waveform signal COM ′ becomes 25.2 V or more, as shown by a thick line in FIG. 5, the first potential adjustment circuit 33 operates, and the collector potential of the NPN transistor 32a included in the current amplification circuit 32 is set. Raise. In this case, the first power supply circuit 71 is selected as the current source, and the NPN transistors 33a and 33b operate. Accordingly, the NPN transistor 32 a of the current amplifier circuit 32 operates in a state where the collector potential is adjusted by the first potential adjustment circuit 33.

<When the potential of the potential waveform signal COM ′ drops>
The collector of the PNP transistor 32 b included in the current amplifier circuit 32 is connected to the power supply terminal of the second power supply circuit 72 via the third Schottky barrier diode 83. Therefore, assuming that the loss due to the third Schottky barrier diode 83 can be ignored, the collector potential of the PNP transistor 32b does not exceed 28V. Accordingly, when the potential of the potential waveform signal COM ′ is high and does not satisfy the operating conditions of the third potential adjustment circuit 35 and the fourth potential adjustment circuit 36, the second power supply circuit 72 is selected, as shown by a thick line in FIG. In addition, the charge discharged from the collector of the PNP transistor 32 b moves to the second power supply circuit 72. In this case, the voltage between the emitter and the collector of the PNP transistor 32b of the current amplifier circuit 32 is the difference between the potential of the drive signal COM and the potential of the power supply terminal of the second power supply circuit 72, and the third power supply circuit 73 and It becomes smaller than the case where the ground is used. Therefore, power consumption can be suppressed.

  The third potential adjustment circuit 35 operates when the base potential of the second PNP transistor 35b becomes a predetermined amount or more lower than the collector potential of the PNP transistor 32b included in the current amplifier circuit 32. The same applies to the fourth potential adjustment circuit 36. Here, the Zener voltage (4.3V) of the Zener diode 35d included in the third potential adjustment circuit 35 is larger than the Zener voltage (3.6V) of the Zener diode 36d included in the fourth potential adjustment circuit 36. The cathode potentials of the Zener diodes 35d and 36d are common to the potential of the potential waveform signal COM ′. For this reason, the third potential adjustment circuit 35 operates preferentially over the fourth potential adjustment circuit 36. In this example, when the potential of the potential waveform signal COM ′ reaches 30.5V, the base potential of the second PNP transistor 35b is 26.2V, which satisfies the operating condition. At this time, the base potential of the PNP transistor 36b included in the fourth potential adjustment circuit 36 is 26.9V, which does not satisfy the operating condition.

  Therefore, when the potential of the potential waveform signal COM ′ becomes 30.5 V or less, the third potential adjustment circuit 35 operates in preference to the fourth potential adjustment circuit 36 as shown by a thick line in FIG. The collector potential of the PNP transistor 32b included in is lowered. At this time, the collector potential of the PNP transistor 32b is set to a potential that is 2.5 V lower than the potential of the potential waveform signal COM ′. Accordingly, the potential difference from the drive signal COM can be reduced, and the power consumption in the PNP transistor 32b can be suppressed. The power supply terminal of the third power supply circuit 73 is connected to the collector of the first PNP transistor 35 a included in the third potential adjustment circuit 35 via the fourth Schottky barrier diode 84. Therefore, it can be said that the third power supply circuit 73 is selected by the third potential adjustment circuit 35. The collector potential of the first PNP transistor 35a becomes the potential (14V) of the power supply terminal of the third power supply circuit 73 when the loss of the fourth Schottky barrier diode 84 is ignored. For this reason, the power consumption of the first PNP transistor 35a can be suppressed more than when the collector is grounded.

  Meanwhile, the first PNP transistor 35 a of the third potential adjustment circuit 35 discharges the charge to the third power supply circuit 73. For this reason, the potential that can be adjusted by the third potential adjustment circuit 35 has a lower limit. When the potential of the potential waveform signal COM ′ further decreases when the collector potential of the PNP transistor 32b included in the current amplifier circuit 32 is at the lower limit value adjustable by the third potential adjustment circuit 35, the fourth potential adjustment circuit. 36 operating conditions are satisfied. In this example, when the base potential of the second PNP transistor 36b included in the fourth potential adjustment circuit 36 becomes 1.8 V or more lower than the collector potential of the PNP transistor 32b included in the current amplification circuit 32, the fourth potential adjustment circuit 36 is used. The operating conditions are satisfied. It is assumed that the lower limit value of the potential that can be adjusted by the third potential adjustment circuit 35 is 15V. In this case, when the potential of the potential waveform signal COM ′ reaches 16.8V, the base potential of the second PNP transistor 36b becomes 13.2V, which satisfies the operating condition of the fourth potential adjustment circuit 36.

  Therefore, when the potential of the potential waveform signal COM ′ becomes 16.8 V or less, the fourth potential adjustment circuit 36 operates and the collector potential of the PNP transistor 32 b included in the current amplification circuit 32 is set as shown by a thick line in FIG. Lower. Accordingly, the PNP transistor 32 b of the current amplifier circuit 32 operates in a state where the collector potential is adjusted by the fourth potential adjustment circuit 36.

<Operation during drive signal generation>
FIG. 9 shows an example of the drive signal COM generated by the drive signal generation circuit 30. This drive signal COM includes a plurality of ejection pulses PS for ejecting ink from the head 42. The ejection pulse PS includes a first constant potential portion Pa that is constant at the intermediate potential VC, a first potential increasing portion Pb that increases the potential from the intermediate potential VC to the maximum potential VH at a certain degree, and a first potential VH that maintains the maximum potential VH. 2 a constant potential portion Pc, a potential lowering portion Pd that lowers the potential from the highest potential VH to the lowest potential VL with a certain degree, a third constant potential portion Pe that maintains the lowest potential VL, and from the lowest potential VL to the intermediate potential VC And a second potential raising portion Pf that raises the potential. Then, the drive signal generation circuit 30 periodically generates the ejection pulse PS.

  In the generation period (up to the period T1) of the first constant potential portion Pa, the drive signal COM is constant at the intermediate potential VC (about 14V). During this period, the second potential adjustment circuit 34 is operable, but no current is amplified because the potential of the corresponding potential waveform signal COM ′ is constant.

  In the generation period (period T1 and period T2) of the first potential increase portion Pb, the potential of the drive signal COM is increased at a certain degree. In the period T1, the second potential adjustment circuit 34 operates, and current amplification of the potential waveform signal COM ′ is performed as indicated by a thick line and an arrow in FIG. That is, the drive signal COM is generated using the power supply (28 V power supply) generated by the second power supply circuit 72. Further, in the period T2, as shown in FIG. 5, the first potential adjustment circuit 33 operates to perform current amplification of the potential waveform signal COM ′. That is, the drive signal COM is generated using the power supply (42V power supply) generated by the first power supply circuit 71. When the drive signal COM reaches the maximum potential VH, the current amplification of the potential waveform signal COM ′ ends. Thereafter, in the generation period of the second constant potential portion Pc, the drive signal COM maintains the maximum potential VH. For this reason, current amplification of the potential waveform signal COM ′ is not performed.

  In the generation period (period T3 to period T5) of the potential decrease unit Pd, the potential of the drive signal COM is decreased by a certain degree. In the period T3, neither the third potential adjustment circuit 35 nor the fourth potential adjustment circuit 36 operates. Therefore, as shown in FIG. 6, the power supply terminal of the second power supply circuit 72 is connected to the collector of the PNP transistor 32 b included in the current amplifier circuit 32. That is, when the drive signal COM is generated, the second power supply circuit 72 is selected as a charge discharge destination. In the period T4, the third potential adjustment circuit 35 operates as shown in FIG. As a result, the power supply terminal of the third power supply circuit 73 is connected to the collector of the first PNP transistor 35a. That is, when the drive signal COM is generated, the third power supply circuit 73 is selected as a charge discharge destination. In the period T5, as shown in FIG. 8, the fourth potential adjustment circuit 36 operates. As a result, the collector of the first PNP transistor 36a is grounded. That is, when the drive signal COM is generated, the ground is selected as the charge discharge destination. When the drive signal COM reaches the lowest potential VL, the current amplification of the potential waveform signal COM ′ ends. Thereafter, in the generation period of the third constant potential portion Pe, the drive signal COM maintains the minimum potential VL. For this reason, current amplification of the potential waveform signal COM ′ is not performed.

  In the generation period (period T6 and period T7) of the second potential increase portion Pf, the potential of the drive signal COM is increased at a certain degree. In the period T6, neither the first potential adjustment circuit 33 nor the second potential adjustment circuit 34 operates. For this reason, as shown in FIG. 3, the power supply terminal of the third power supply circuit 73 is connected to the collector of the NPN transistor 32 a included in the current amplifier circuit 32. That is, the drive signal COM is generated using the power supply (14V power supply) generated by the third power supply circuit 73. In the period T7, as shown in FIG. 4, the second potential adjustment circuit 34 operates, so that the drive signal COM is generated using the 28V power supply. When the drive signal COM reaches the intermediate potential VC, the current amplification of the potential waveform signal COM ′ ends.

<Summary>
As described above, in the printer 1, the DAC data of the digital data is converted into the potential waveform signal COM ′ of the analog signal by the waveform generation circuit 31 as the analog signal conversion unit. Then, in the potential adjustment circuits 33 to 36 as the circuit selection unit, the power supply circuit used for current amplification of the potential waveform signal COM ′ is selected from the plurality of types of power supply circuits 71 to 73 having different voltages. The selection is based on the potential of ′. For this reason, the effect of suppressing power consumption can be obtained quickly (early). Further, by using the selected power supply circuit, power consumption during current amplification can be suppressed.

=== Second Embodiment ===
Next, a second embodiment of the printer 1 will be described. FIG. 10 is a diagram for explaining a main part of the printer 1 according to the second embodiment. The second embodiment is characterized in that capacitors 87 and 88 charged by the power generated by the second power circuit 72 and the third power circuit 73 are provided. The basic configurations of the potential adjustment circuits 33 to 36 are the same, but the manner of connection and the types of the Zener diodes 33d to 36d are different. Therefore, the configuration will be described focusing on the differences from the first embodiment.

<About configuration>
One terminal (corresponding to a charge / discharge terminal) of the first capacitor 87 is connected to the power supply terminal of the second power supply circuit 72 via the first power supply resistor 85, and the other terminal is grounded. One terminal of the second capacitor 88 is connected to the power supply terminal of the third power supply circuit 73 via the second power supply resistor 86, and the other terminal is grounded. Accordingly, the first capacitor 87 is charged by the current flowing through the first power supply resistor 85, and the second capacitor 88 is charged by the current flowing through the second power supply resistor 86.

  Regarding the first potential adjustment circuit 33, the collector of the first NPN transistor 33 a is connected to the emitter of the first NPN transistor 34 a included in the second potential adjustment circuit 34. In addition, a Zener diode 33d having a Zener voltage of 4.3V is used. Regarding the second potential adjustment circuit 34, the collector of the second NPN transistor 34b is connected to the collector of the first NPN transistor 34a. Further, a Zener diode 34d having a Zener voltage of 3.6V is used. Regarding the third potential adjustment circuit 35, the collector of the first PNP transistor 35 a is connected to the emitter of the first PNP transistor 36 a included in the fourth potential adjustment circuit 36. The fourth potential adjustment circuit 36 has the same configuration as the fourth potential adjustment circuit 36 of the first embodiment.

<Operation during drive signal generation>
The basic operation when generating a drive signal in the printer 1 of the second embodiment is the same as that of the first embodiment. Briefly, when the potential of the potential waveform signal COM ′ is increased, if the potential is low and neither of the operating conditions of the first potential adjustment circuit 33 and the second potential adjustment circuit 34 is satisfied, as shown in FIG. The electric potential waveform signal COM ′ is amplified using the electric charge stored in the second capacitor 88. Thereafter, when the potential of the potential waveform signal COM ′ rises to satisfy the operating condition of the second potential adjustment circuit 34, the potential waveform is generated using the charge stored in the first capacitor 87 as shown in FIG. Current amplification of the signal COM ′ is performed. Thereafter, when the potential of the potential waveform signal COM ′ further rises to satisfy the operating condition of the first potential adjustment circuit 33, the first potential adjustment circuit 33 and the second potential adjustment circuit 34 are shown in FIG. Operate together, and the first power source generated by the first power source circuit 71 is used for current amplification of the potential waveform signal COM ′.

  On the other hand, when the potential of the potential waveform signal COM ′ drops, if the potential is high and does not satisfy the operating conditions of the third potential adjustment circuit 35 and the fourth potential adjustment circuit 36, as shown in FIG. The charge discharged from the collector of the PNP transistor 32 b included in is moved to the first capacitor 87. After that, when the potential of the potential waveform signal COM ′ decreases and the operating condition of the third potential adjustment circuit 35 is satisfied, the first PNP transistor 35a of the third potential adjustment circuit 35 has a configuration as shown in FIG. The electric charge discharged from the collector moves to the second capacitor 88. Thereafter, when the potential of the potential waveform signal COM ′ further falls and the operating condition of the fourth potential adjustment circuit 36 is satisfied, as shown in FIG. 16, the third potential adjustment circuit 35 and the fourth potential adjustment circuit 36 are displayed. Operate together, and charge is discharged from the collector of the first PNP transistor 36a of the fourth potential adjustment circuit 36 to the ground.

<Summary>
The first capacitor 87 and the second capacitor 88 are charged by the power generated by the second power circuit 72 or the third power circuit 73 (corresponding to another power circuit). The charges stored in these capacitors 87 and 88 are discharged when the potential of the drive signal COM rises and are used for current amplification of the potential waveform signal COM ′ in the current amplification circuit 32. Further, these capacitors 87 and 88 are charged by charges discharged from the PNP transistor 32b included in the current amplifier circuit 32 when the potential of the drive signal COM is lowered. Therefore, by providing these capacitors 87 and 88, it is possible to enhance the effect of suppressing power consumption during the current amplification of the potential waveform signal COM ′. Further, once the capacitors 87 and 88 are charged, the second power supply circuit 72 and the third power supply circuit 73 do not need to operate so much and do not require a large power supply capacity.

=== Other Embodiments ===
The above-described embodiment has been described with respect to the printer 1, which includes disclosure of a method for generating the drive signal COM. The above-described embodiments are for facilitating understanding of the present invention, and are not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and it is needless to say that the present invention includes equivalents thereof.

<About current amplifier>
In the above-described embodiment, the current amplifying circuit 32 including the NPN transistor 32a and the PNP transistor 32b is exemplified as the current amplifying unit. In this regard, the current amplifying unit may have another configuration as long as it has a current amplifying transistor.

<About other devices>
The printer 1 in each embodiment is configured to reciprocate the head 42 in the carriage movement direction, but is not limited to this configuration. For example, it may be a line head printer having a line head in which a plurality of nozzles are arranged across the width direction of the medium.

  Further, an apparatus to which the drive signal generation apparatus is applied is not limited to a printer (liquid ejection apparatus). For example, the drive signal generating device can be applied to a micro pump, sounding body (speaker, etc.), and micro actuator using this element.

FIG. 2 is a block diagram illustrating a configuration of a printer. It is a figure explaining a drive signal generation circuit and its peripheral part. FIG. 6 is a diagram illustrating a state in which neither the first potential adjustment circuit nor the second potential adjustment circuit is operating when the potential of the drive signal increases. It is a figure which shows the state which is the time of the potential rise of a drive signal, and is operating the 2nd potential adjustment circuit. FIG. 6 is a diagram illustrating a state in which the first potential adjustment circuit is operating when the potential of the drive signal is rising. FIG. 10 is a diagram illustrating a state in which neither the third potential adjustment circuit nor the fourth potential adjustment circuit is operating when the potential of the drive signal is lowered. FIG. 10 is a diagram illustrating a state in which a third potential adjustment circuit is operating when the potential of the drive signal drops. FIG. 10 is a diagram showing a state where the fourth potential adjustment circuit is operating when the potential of the drive signal is lowered. It is a figure explaining the relationship between the drive signal produced | generated and the operation period of an electric potential adjustment circuit. It is a figure explaining the drive signal generation circuit and its peripheral part in 2nd Embodiment. FIG. 6 is a diagram illustrating a state in which neither the first potential adjustment circuit nor the second potential adjustment circuit is operating when the potential of the drive signal increases. It is a figure which shows the state which is the time of the potential rise of a drive signal, and is operating the 2nd potential adjustment circuit. FIG. 6 is a diagram illustrating a state in which the first potential adjustment circuit and the second potential adjustment circuit are operating when the potential of the drive signal increases. FIG. 10 is a diagram illustrating a state in which neither the third potential adjustment circuit nor the fourth potential adjustment circuit is operating when the potential of the drive signal is lowered. FIG. 10 is a diagram illustrating a state in which a third potential adjustment circuit is operating when the potential of the drive signal drops. FIG. 10 is a diagram illustrating a state in which the third potential adjustment circuit and the fourth potential adjustment circuit are operating when the potential of the drive signal drops.

Explanation of symbols

1 printer, 10 paper transport mechanism, 20 carriage movement mechanism,
30 drive signal generation circuit, 31 waveform generation circuit, 32 current amplification circuit,
32a NPN transistor, 32b PNP transistor,
33 first potential adjustment circuit, 33a first NPN type transistor,
33b second NPN transistor, 33c diode,
33d Zener diode, 33e capacitor, 33f first resistor,
33g second resistance,
34 second potential adjustment circuit, 34a first NPN type transistor,
34b second NPN transistor, 34c diode,
34d Zener diode, 34e capacitor,
34f 1st resistance, 34g 2nd resistance,
35 third potential adjustment circuit, 35a first PNP type transistor,
35b second PNP transistor, 35c diode,
35d Zener diode, 35e capacitor,
35f first resistor, 35g second resistor,
36 fourth potential adjustment circuit, 36a first PNP type transistor,
36b Second PNP transistor, 36c diode,
36d Zener diode, 36e capacitor, 36f first resistor,
36g second resistance,
40 head units, 41 head control units, 411 switches,
42 heads, 421 piezo elements, 50 detector groups,
60 printer-side controller, 61 interface section,
62 CPU, 63 memory, 64 control unit, 70 power generation unit,
71 1st power supply circuit, 72 2nd power supply circuit, 73 3rd power supply circuit,
81 first Schottky barrier diode,
82 second Schottky barrier diode,
83 Third Schottky barrier diode,
84 4th Schottky barrier diode,
85, first power source resistor, 86 second power source resistor, 87 first capacitor,
88 Second capacitor, COM drive signal, COM 'potential waveform signal,
PS discharge pulse, Pa first constant potential portion, Pb first potential rise portion,
Pc second constant potential portion, Pd potential lowering portion, Pe third constant potential portion,
Pf Second potential rise unit, CP computer

Claims (7)

(A) an analog signal converter for converting digital data into an analog signal;
(B) a current amplification unit that generates a drive signal by amplifying the current of the analog signal, the current amplification unit including a transistor for current amplification;
(C) a plurality of types of power supply circuits having different voltages;
(D) a circuit selection unit that selects a power supply circuit used for current amplification of the analog signal from the plurality of types of power supply circuits based on the potential of the analog signal;
A drive signal generation device having (E). The drive signal generation device according to claim 1,
Drive signal generation having a potential adjustment unit that adjusts the potential of the amplification current terminal on the side that is not for the drive signal among the pair of amplification current terminals of the current amplification transistor according to the potential of the analog signal apparatus. The drive signal generation device according to claim 2,
The transistor for current amplification is
An NPN transistor that operates when the potential of the drive signal rises, the NPN transistor having the analog signal applied to a base and flowing an amplified current from the collector toward the emitter;
The potential adjustment unit includes:
A drive signal generation device that adjusts a collector potential of the NPN transistor so as to be higher than a potential of the analog signal by a predetermined potential. The drive signal generation device according to claim 2,
The transistor for current amplification is
A PNP transistor that operates when the potential of the drive signal drops, the PNP transistor having the analog signal applied to a base and flowing an amplified current from an emitter toward a collector;
The potential adjustment unit includes:
A drive signal generation device that adjusts a collector potential of the PNP transistor so as to be lower than a potential of the analog signal by a predetermined potential. The drive signal generation device according to any one of claims 1 to 4,
The plurality of types of power supply circuits are:
The main voltage circuit with the highest voltage,
A drive signal generation device comprising: another power supply circuit having a voltage lower than the highest voltage, the power supply capacity being smaller than the power supply capacity of the main power supply circuit. The drive signal generation device according to claim 5,
A drive signal generation device comprising a storage element that is charged by a power source generated by the other power supply circuit and discharged by the operation of the current amplification transistor when the potential of the drive signal rises. The drive signal generation device according to claim 6,
The power storage element is
A drive signal generation device that is also charged by electric charges released from the current amplification transistor when the potential of the drive signal drops.

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