JP5035254B2 - Sample rate converter - Google Patents

Description

  The present invention relates to a sample rate converter used in digital audio equipment.

  In recent years, devices for recording / reproducing digital audio such as CD / DVD are increasing, and there is a demand for mixing outputs from a plurality of devices and for putting CD sound into a DVD. For example, the sampling frequency of CD is 44.1 kHz, and the sampling frequency of DVD is 48 kHz. Therefore, when these are to be converted mutually, D / A conversion is performed once and processed in an analog state. Although it is possible to record after D conversion, noise and distortion are added via analog, so a sample rate converter is used to convert these sampling frequencies in the digital domain.

  A block diagram of an example of a conventional sample rate converter is shown in FIG. In FIG. 4, the sample rate converter 405 includes a frequency detection circuit 401, an interpolation filter 402, a FIFO (first-in first-out) memory circuit 403, and a correction circuit 404. A digital audio interface reception circuit (hereinafter referred to as a DAI reception circuit) 400 generates a transfer clock and data from an input signal from an external device and outputs it to the sample rate converter 405. The frequency detection circuit 401 detects the frequency of the clock signal generated by the DAI reception circuit 400. The interpolation filter 402 estimates the output signal at the output clock frequency based on the frequency information detected by the frequency detection circuit 401. The FIFO memory circuit 403 temporarily holds the output signal generated by the interpolation filter 402 and sequentially outputs it at an accurate output clock frequency. The correction circuit 404 controls the FIFO.

  Next, the operation of the sample rate converter 405 will be described.

  The DAI receiving circuit 400 receives a serial signal such as a standard AES / EBU interface such as a coaxial cable or an optical cable, and outputs three signals, that is, a bit clock, a word clock, and data. In general, the bit clock is 64 times the sampling frequency fs, the word clock is the frequency of fs itself, and the data is 16 to 24 bits of audio data and other additions in 32 samples of each L / R. It is a signal that contains information.

  First, the frequency detection circuit 401 receives the bit clock of the output of the DAI receiving circuit 400 as an input, and counts for a certain period with a signal that is an integer multiple of the bit clock on the output side. Find the ratio. For example, when the input clock fs is 44.1 kHz, the bit clock is 2.8224 MHz, and when the output fs is 48 kHz, the counting clock is fs * 64 * 8 = 512 times 24.576 MHz. Therefore, 8.70748 output clocks are input, and fs conversion is performed based on this ratio.

  In the interpolation filter 402, the input data is first oversampled and passed through a low-pass filter that removes unnecessary band signals, and then the values between samples are linearly interpolated based on the ratio signal, for example, 8/8. Calculate the value every 70748 = 0.91875. It is known that the conversion accuracy is determined by the oversample ratio and the number of points of linear interpolation at this time, and the amplitude error is 20 bits or less if 512 fs and 2048 points.

  The converted output data obtained in this way is temporarily held in the FIFO memory circuit 403, read out in accordance with the timing of a fixed output word clock, and output together with the output bit clock for external processing. used.

In general, the FIFO processing is controlled while constantly checking the remaining memory so that the number of input data and the number of output data are balanced. In the case of the FIFO of the sample rate converter, since the timing of the output data is determined by the converted frequency, the control is performed by changing the input side. That is, the operation is performed while correcting the frequency detection result so that the frequency detection time constant is always in the center direction.
Non-Patent Document 1 proposes a method for controlling the FIFO by correcting the value of the frequency ratio by a process of correcting the re-sampling time.

The correction circuit 404 corrects the output of the frequency detection circuit 401 and changes the number of data to be sent to the FIFO memory circuit 403 when the remaining amount of the FIFO memory circuit 403 increases in order to perform the above-described FIFO control. In order to reduce the remaining amount of the FIFO memory circuit 403, for example, when data is accumulated in the FIFO excessively, the number of input data is reduced by correcting the frequency ratio to be increased. It works to reduce the remaining amount.
Radio Technology May 1994 Issue p133-144

  However, performing such FIFO control changes the sampling frequency conversion ratio, which causes a problem that distortion occurs in output data.

  Although the original 20-bit precision is used, when the resampling time is corrected by 1 LSB, the linear interpolation value changes, so that only 1-bit less precision can be obtained. Also, since the output of the frequency detection circuit often fluctuates slightly due to the influence of power supply noise, etc., the same accuracy degradation occurs in this case as well, and this fluctuation occurs constantly. As a result, the input audio signal and the fluctuation amount cause cross modulation distortion, which causes deterioration in sound quality due to sample rate conversion.

  An object of the present invention is to provide a sample rate converter capable of solving such problems and realizing high-accuracy conversion with a simple circuit.

The present invention is a sample rate converter for converting a sample rate of an input signal and outputting the sample signal, receiving means for generating a clock signal from the input signal, and a frequency for detecting the frequency of the clock signal generated by the receiving circuit. A detection means, an interpolation filter for estimating an output signal based on frequency information detected by the frequency detector, and temporarily holding the output signal generated by the interpolation filter and outputting an output signal at a predetermined frequency And a holding means for quantizing and holding the frequency information detected by the frequency detector and outputting the frequency information to the interpolation filter. The holding means includes the FIFO remaining amount information. Based on this, the output frequency to the interpolation filter is determined.

  In this way, the sample rate converter of the present invention does not always use the output of the frequency detector as it is as in the prior art, but retains the quantized value and performs frequency conversion with the retained value. Since the frequency of change is changed so as to give new frequency information only when the remaining amount of FIFO decreases, it is possible to use a frequency detection output that does not normally change at all. With this fixed frequency information, a theoretically high-performance sample rate conversion process is performed over most of the time, and as a result, there is an effect that sample rate conversion with high sound quality that has not been possible in the past becomes possible.

  Preferably, the frequency detected by the frequency detector is output to the interpolation filter when the FIFO remaining amount information deviates from a preset upper threshold or lower threshold.

  In this way, a constant frequency detection result is output to the interpolation filter within the FIFO capacity range, so that the operation of the interpolation filter is not changed as much as possible. Long frequency detection can be performed, and fluctuation components that are unnecessarily superimposed on the input signal can be ignored. As a result, high-quality sample rate conversion with little cross-modulation noise is possible. Can be performed.

  Preferably, it further comprises lock detecting means for detecting whether or not the frequency detected by the frequency detecting means is within a predetermined range, and when the frequency is out of the predetermined range, the frequency detection output to the interpolation filter is a high-speed detection value. Switch to.

  In this way, when a sudden frequency fluctuation occurs, such as when the input signal frequency is switched from DVD to CD, the lock detection is removed, so that the fluctuation can be followed quickly. Converges into a predetermined range and returns to normal operation when a lock is detected, thereby enabling highly accurate sample rate conversion.

  That is, according to the present invention, high-quality sample rate conversion with less cross modulation noise can be performed.

(Embodiment 1)
<1. Configuration of sample rate converter>
FIG. 1 shows a block diagram of a sample rate converter 105 according to Embodiment 1 of the present invention. In FIG. 1, a digital audio interface receiving circuit (hereinafter referred to as a DAI receiving circuit) 400 and a sample rate converter 105 are composed of a frequency detection circuit 101, an interpolation filter 102, a FIFO (first-in first-out) memory circuit 103, and a holding circuit 104. The

  The frequency detection circuit 101 detects the frequency of the clock signal generated by the DAI reception circuit 400. The interpolation filter 102 estimates an output signal at the output clock frequency based on the frequency information output from the holding circuit 104. A FIFO (first-in first-out) memory circuit 103 temporarily holds the output signal generated by the interpolation filter 102 and sequentially outputs it at an accurate output clock frequency. The holding circuit 104 quantizes and holds the output of the frequency detection circuit 101 based on the remaining amount information of the FIFO memory circuit 103, and outputs the output to the interpolation filter 102. Each configuration will be specifically described below.

  The frequency detection circuit 101 can be composed of a counter that counts the number of changes in the input clock signal for a fixed time, for example, 0.1 second. When counting 2.8224 MHz, it becomes 28224 (6E40h in hexadecimal), so the 15-bit counter A 17-bit counter is prepared in order to widen the corresponding range from 32 kHz to 192 kHz. In order to further improve the accuracy, a 20-bit counter is sufficient even if a signal obtained by averaging the measurement results eight times is generated. This is compared with an output frequency, for example, a count number 30720 at 48 kHz (hexadecimal number 7800h) to obtain a frequency ratio.

  The interpolation filter 102 performs normal band limiting filter processing and oversampling processing, calculates the ratio with the output sample rate based on the frequency information obtained by the frequency detection circuit 101, and determines the timing of the output samples. calculate. Based on this timing information, for example, if the value is 153/2048 after the current timing, a linear interpolation value between the current sample value and the next sample value is calculated and used as an output signal.

  The FIFO memory circuit 103 temporarily stores the output signal of the interpolation filter 102 at the timing when the above calculation result is output, holds the signal to some extent, and then outputs it in accordance with the constant output timing after conversion.

The holding circuit 104 monitors the remaining amount information of the FIFO memory circuit 103, and holds the frequency information of the output of the frequency detection circuit 101 when a predetermined state is reached. Basically, when the remaining amount information is greatly swung to the positive side or the negative side, and it is desired to reduce the remaining amount, new frequency information is held, and this is quantized according to the desired direction and output to the interpolation filter 102 Therefore, the number of samples of the output signal of the interpolation filter 102 calculated based on the new frequency information changes, and the remaining amount information of the FIFO memory circuit 103 changes accordingly.
<2. Correspondence between Embodiment 1 and the Present Invention>
The sample rate converter 105 is an example of a sample rate converter. The DAI receiving circuit 400 is an example of a receiving unit. The frequency detection circuit 101 is an example of a frequency detection unit. The interpolation filter 102 is an example of an interpolation filter. The FIFO memory circuit 103 is an example of a FIFO. The holding circuit 104 is an example of a holding unit.
<3. Operation of sample rate converter>
The operation of the sample rate converter 105 includes a normal operation and an operation when the input frequency changes. Each operation will be described.
<3.1 Normal operation>
In a normal operation state, the output of the frequency detection circuit 101 is quantized by the holding circuit 104, and further, the sample rate conversion process is performed with a value that is held after being rounded down. Assuming that the remaining amount of the FIFO 103 is reduced by the error between the actual input clock frequency and the held value, the FIFO 103 is likely to underflow after a certain period of time. A threshold value is provided before that occurs, and a signal is output to the holding circuit 104 when this threshold value is reached. The holding circuit 14 receives the signal from the FIFO 103 and re-fetches the output of the frequency detection circuit 101. This time, the holding value is determined in a state where the quantization method is changed from rounding down to rounding up and output to the interpolation filter 102. . As a result, the error between the actual input clock frequency and the held value is set on the opposite side, and the remaining amount of the FIFO 103 is set to increase.

  Quantizing the frequency detection result in this way is also effective for removing the influence of minute fluctuations, and the stability of the frequency detection becomes high instead of lowering the frequency detection accuracy, and by combining with the FIFO unit of the present invention, Sample rate conversion with higher stability can be realized.

  A process of adding / subtracting 1LSB to the normal detection result instead of switching the quantization method can provide the same function. However, the larger the change amount, the larger the change rate of the remaining amount of the FIFO 103. When it is desired to move in the fixed state for the same time, the capacity of the FIFO 103 needs to be a little larger.

  FIG. 2 shows a time change graph of the remaining amount of the FIFO 103. In FIG. 2, 16 is a remaining amount change when the conventional correction circuit is used, 17 is a remaining amount change when the holding circuit 104 of the present invention is used, 18 is an upper threshold for remaining amount detection, and 19 is a threshold value. This is the lower threshold of the remaining amount detection.

When the conventional correction circuit is used, since the output of the frequency detection circuit 101 is directly used, the remaining amount changes relatively frequently as 16 due to the quantization error of the detection output, etc. When the holding circuit 104 is used, since the fixed frequency information is used, the remaining amount changes at a constant ratio as indicated by 17 based on the fixed error. When the remaining amount reaches the upper threshold value 18, new frequency information is set in the holding circuit 104, so that the remaining amount is changed so as to decrease this time. Thereafter, when the remaining amount reaches the lower threshold value, new frequency information is set in the holding circuit 104, and this time, the remaining amount changes in the direction of increasing. Since such a frequency error is usually a very small value, the time to reach the FIFO 103 threshold is often in the order of minutes instead of seconds. In such a case, it operates at a fixed frequency for hearing. Conversion results with high sound quality. Thus, by effectively using the capacity of the FIFO 103, the interval for changing the frequency information can be made very long, thereby enabling high-accuracy sample rate conversion as described above.
<3.2 Operation when changing input frequency>
When the input frequency changes slightly, since the conversion ratio in the interpolation filter 102 is fixed, the rate of change in the remaining amount of FIFO increases as the frequency detection error due to the input change increases. Accordingly, the basic operation is the same as in the normal operation, only the time for reaching the threshold value of the FIFO 103 is shortened. However, when the fluctuation continues for a long time in a certain direction, the frequency detection information is constantly updated in the vicinity of the threshold value, and the frequency conversion is performed with the fixed value that is the object of the present invention. Although the operation is different from the state, there is no problem in the operation itself even at this time, the performance is equivalent to that of the conventional sample rate converter.

(Embodiment 2)
<1. Configuration of sample rate converter>
The lock detection circuit 106 uses a part of the detection circuit of the frequency detection circuit 101 to detect whether the input signal frequency is within a predetermined range.

  FIG. 3 shows a block diagram of the sample rate converter 305 according to Embodiment 2 of the present invention. In FIG. 3, the sample rate converter 305 according to the second embodiment of the present invention includes a lock detection circuit 106 in addition to the configuration of the first embodiment.

The lock detection circuit 106 detects whether or not the input frequency is within a predetermined range.
<2. Correspondence between Embodiment 2 and the Present Invention>
The lock detection circuit 106 is an example of lock detection means.
<3. Operation of sample rate converter>
Even when the input signal frequency changes more greatly, such as when the input sampling frequency is switched, the operation of the sample rate converter alone does not change, so until the remaining amount of the FIFO 103 reaches the threshold value. I cannot respond. Therefore, since the conversion output is adjusted to the wrong sampling frequency in the middle of the change of the input, the pitch is changed or abnormal noise is generated. Even in this case, if the switching time is waited, the output is switched to a normal output. However, since the efficiency is not good, the lock detection circuit 106 operates in order to speed up the response. By checking the value of the counter in the frequency detection circuit 101 with low accuracy, approximate frequency information can be obtained at high speed. For example, if the time required for high-precision 20-bit counting is 1 second, if the accuracy is reduced to 1/64, the time can also be 1/64 and 14-bit counting can be performed. It is possible to obtain rough information that it seems that the frequency has changed from 44.1 kHz to 48 kHz, and this detection signal is output to the holding circuit 104 and the FIFO 103 to re-fetch the detected data detected at high speed and clear the FIFO. By doing so, conversion to a new sampling frequency at high speed can be started.

  In this example, the value of the internal counter of the frequency detection circuit is used for high-speed lock detection, but this may be used if there is any external switching signal.

  The present invention is applicable to a digital audio recording / reproducing system that requires high-quality audio output.

Block diagram of sample rate converter according to Embodiment 1 of the present invention FIFO remaining amount diagram in the sample rate converter according to the first embodiment of the present invention Block diagram of sample rate converter according to Embodiment 2 of the present invention Block diagram of a conventional sample rate converter

DESCRIPTION OF SYMBOLS 100 DAI receiving circuit 101 Frequency detection circuit 102 Interpolation filter 103 FIFO
104 holding circuit 105 sample rate converter 106 lock detection circuit

Claims (3)

A sample rate converter that converts a sample rate of an input signal and outputs the sample rate.
Receiving means for generating a clock signal from the input signal;
Frequency detecting means for detecting the frequency of the clock signal generated by the receiving circuit;
An interpolation filter that estimates an output signal based on the quantized frequency information detected by the frequency detector;
A FIFO that temporarily holds the output signal generated by the interpolation filter and outputs the output signal at a predetermined frequency;
The frequency information detected by the frequency detector is quantized and held, and holding means for outputting the quantized frequency information to the interpolation filter,
The sample rate converter characterized in that the holding means determines an output frequency to the interpolation filter based on the remaining amount information of the FIFO. The holding means outputs the quantized frequency information detected by the frequency detector to the interpolation filter when the FIFO remaining amount information deviates from a preset upper threshold or lower threshold. The sample rate converter according to claim 1, wherein: Lock detection means for detecting whether or not the frequency detected by the frequency detection means is within a predetermined range;
The sample rate converter according to claim 1 or 2, wherein when the frequency is out of a predetermined range, the frequency detection output to the interpolation filter is switched to a high-speed detection value.

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