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JP5040804B2 - Semiconductor device manufacturing method and semiconductor element inspection structure - Google Patents
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JP5040804B2 - Semiconductor device manufacturing method and semiconductor element inspection structure - Google Patents

Semiconductor device manufacturing method and semiconductor element inspection structure Download PDF

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JP5040804B2
JP5040804B2 JP2008129052A JP2008129052A JP5040804B2 JP 5040804 B2 JP5040804 B2 JP 5040804B2 JP 2008129052 A JP2008129052 A JP 2008129052A JP 2008129052 A JP2008129052 A JP 2008129052A JP 5040804 B2 JP5040804 B2 JP 5040804B2
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semiconductor element
wiring board
gap
semiconductor device
semiconductor
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JP2009277955A (en
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博幸 浜口
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NEC Corp
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)

Description

本発明は、配線基板上に半導体素子がフェイスダウンで実装される半導体装置の製造方法及び半導体素子検査構造に関する。   The present invention relates to a method for manufacturing a semiconductor device in which semiconductor elements are mounted face-down on a wiring board, and a semiconductor element inspection structure.

各種電子装置の機能,性能向上に伴い、使用される電子デバイスの性能を十分引き出すために、モールドが形成されていない半導体素子であるベアチップをフェイスダウンで配線基板に搭載するフリップチップ実装を採用する例が増えてきている。実装の半導体素子をケースに収容し、配線基板に実装する構造に比べてケースが存在しないためケースの抵抗が無く、より高速信号に対応できるからである。   As the functions and performance of various electronic devices improve, flip-chip mounting is adopted in which bare chips, which are semiconductor elements without molds, are mounted face-down on a wiring board in order to bring out the performance of the electronic devices used. Examples are increasing. This is because there is no case resistance compared to a structure in which the mounted semiconductor element is accommodated in the case and mounted on the wiring board, so that the case has no resistance and can cope with higher-speed signals.

フリップチップ実装は、図2(a)の模式断面図に示すように、シリコンウエハ等の下面に電子回路が形成されており、該電子回路と配線基板との接続用の図示しない電極が下面に形成されているフェイスダウン実装用の半導体素子2を使用する。半導体素子2の図示しない電極にバンプと称するはんだ等の金属突起(バンプ3)を設け、これをフェイスダウンで配線基板4と対向させ、バンプ3を溶融させて配線基板4の電極に接合し、半導体素子2と配線基板4相互の電極をバンプ3を介して接続するものである。ワイヤボンディング実装などに比べ高密度実装が可能である。   In flip chip mounting, as shown in the schematic cross-sectional view of FIG. 2A, an electronic circuit is formed on the lower surface of a silicon wafer or the like, and an electrode (not shown) for connecting the electronic circuit and the wiring board is formed on the lower surface. The formed semiconductor element 2 for face-down mounting is used. A metal projection (bump 3) such as a solder called a bump is provided on an electrode (not shown) of the semiconductor element 2, and this is face-down opposed to the wiring board 4, and the bump 3 is melted and joined to the electrode of the wiring board 4. The electrodes of the semiconductor element 2 and the wiring board 4 are connected via bumps 3. High-density mounting is possible compared to wire bonding mounting.

ベアチップ実装では、図2(b)に示すように、半導体素子2と配線基板4との熱膨張係数差に起因する応力を緩和するために半導体素子2と配線基板4間にアンダーフィル樹脂5を充填する構造が採用されている(特許文献1参照)。
また、このアンダーフィル樹脂5は半導体素子2と配線基板4の信頼性を確保するために高強度樹脂が使用されるため、アンダーフィル樹脂5を充填した後では半導体素子2を交換することができない。そのため、ベアチップ実装後のベアチップ検査では、半導体素子2交換を可能とするため,アンダーフィル樹脂5を充填しない状態で行われる。
In the bare chip mounting, as shown in FIG. 2B, an underfill resin 5 is provided between the semiconductor element 2 and the wiring board 4 in order to relieve stress caused by a difference in thermal expansion coefficient between the semiconductor element 2 and the wiring board 4. A filling structure is employed (see Patent Document 1).
In addition, since the underfill resin 5 is made of a high-strength resin in order to ensure the reliability of the semiconductor element 2 and the wiring substrate 4, the semiconductor element 2 cannot be replaced after the underfill resin 5 is filled. . Therefore, the bare chip inspection after the bare chip mounting is performed without filling the underfill resin 5 in order to allow the semiconductor element 2 to be replaced.

また、図3に示すように、大量の熱を発生する半導体素子2には、アルミニウム又は銅等の熱伝導性が高い材料からなり、半導体素子から発生する熱を周囲に放熱し、半導体素子の周辺温度を一定以下にするヒートシンク6が取り付けられて検査される。
半導体素子2の大型化に伴い、半導体素子2の反り等の理由から半導体素子2とヒートシンク6との間に間隙が生じ、ヒートシンク6と半導体素子2とを密着させることが困難になってきている。そのため、半導体素子2とヒートシンク6との間の間隙をサーマルグリースや熱伝導性コンパウンド等の熱伝導性を有する材料の熱伝導性充填層7で埋めることが行われる(特許文献2参照)。
特開2001−291805号公報 特開昭57−208149号公報
Further, as shown in FIG. 3, the semiconductor element 2 that generates a large amount of heat is made of a material having high thermal conductivity such as aluminum or copper. A heat sink 6 is attached and inspected to keep the ambient temperature below a certain level.
With the increase in size of the semiconductor element 2, a gap is generated between the semiconductor element 2 and the heat sink 6 for reasons such as warpage of the semiconductor element 2, and it is difficult to bring the heat sink 6 and the semiconductor element 2 into close contact with each other. . For this reason, the gap between the semiconductor element 2 and the heat sink 6 is filled with a thermally conductive filling layer 7 made of a material having thermal conductivity such as thermal grease or a thermally conductive compound (see Patent Document 2).
JP 2001-291805 A JP-A-57-208149

ベアチップ実装後の半導体素子検査では、半導体素子2と配線基板4間に間隙があるため、図3に示すように、ヒートシンク6と半導体素子2の間隙を埋めるグリース等の熱伝導性充填層7などがこの間隙に浸入することがある。一旦浸入したグリース等は、洗浄しても完全に除去できず、アンダーフィル樹脂5を充填する際にボイドが発生し、接着不良による半導体装置の信頼性が低下する不具合が発生する。   In the semiconductor element inspection after the bare chip mounting, since there is a gap between the semiconductor element 2 and the wiring board 4, as shown in FIG. 3, a thermally conductive filling layer 7 such as grease that fills the gap between the heat sink 6 and the semiconductor element 2, etc. May penetrate into this gap. Once the grease or the like has entered, it cannot be completely removed by washing, and voids are generated when the underfill resin 5 is filled, resulting in a problem that the reliability of the semiconductor device is deteriorated due to poor adhesion.

半導体素子2と配線基板4の間隙へのグリース等の熱伝導性充填層7の浸入を防ぐために、図4に示すように流動性の低い熱伝導性シート8を使用する場合があるが、熱伝導性シート8は熱抵抗が高く、半導体素子冷却性能が低下するため、半導体素子電力を制限しなければならないという問題がある。   In order to prevent the heat conductive filling layer 7 such as grease from entering the gap between the semiconductor element 2 and the wiring substrate 4, a heat conductive sheet 8 having low fluidity may be used as shown in FIG. Since the conductive sheet 8 has a high thermal resistance and the semiconductor element cooling performance decreases, there is a problem that the power of the semiconductor element must be limited.

本発明の目的は、上述した課題である半導体素子と配線基板間の間隙にグリースなどの異物が浸入することによるアンダーフィル樹脂のボイド発生を抑制することができる半導体装置の製造方法を提供することにある。   An object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing the occurrence of voids in an underfill resin due to the entry of foreign matter such as grease into the gap between a semiconductor element and a wiring board, which is the problem described above. It is in.

また、本発明の他の目的は、上述した課題である半導体素子と配線基板間の間隙にグリースなどの異物が浸入することによるアンダーフィル樹脂のボイド発生を抑制することができる半導体素子検査構造を提供することにある。   Another object of the present invention is to provide a semiconductor element inspection structure capable of suppressing the occurrence of voids in the underfill resin caused by foreign matter such as grease entering the gap between the semiconductor element and the wiring board, which is the problem described above. It is to provide.

上記目的を達成するため、本発明の半導体装置の製造方法は、配線基板上に半導体素子をフェイスダウンで実装する実装工程と、前記半導体素子の周囲に洗浄除去可能な材料で構成される保護部を前記半導体素子と前記配線基板との間隙を埋めて形成する保護部形成工程と、前記半導体素子の動作検査及び前記半導体素子と前記配線基板との接続検査を行う検査工程と、前記保護部を洗浄除去する保護部除去工程とを有する。   In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a mounting step of mounting a semiconductor element face down on a wiring board, and a protective part made of a material that can be washed and removed around the semiconductor element. A protection part forming step for filling the gap between the semiconductor element and the wiring substrate; an inspection step for performing an operation inspection of the semiconductor element and a connection inspection between the semiconductor element and the wiring substrate; and And a protective part removing step for washing and removing.

また、本発明の半導体素子検査構造は、配線基板と、前記配線基板上にフェイスダウンで実装された半導体素子と、洗浄除去可能な材料で前記半導体素子の周囲に前記半導体素子と前記配線基板との間隙を埋めて形成された保護部とを有する構成としてある。   Further, the semiconductor element inspection structure of the present invention includes a wiring board, a semiconductor element mounted face down on the wiring board, and the semiconductor element and the wiring board around the semiconductor element with a material that can be cleaned and removed. And a protective part formed by filling the gap.

本発明の半導体装置の製造方法によれば、配線基板上に半導体素子をフェイスダウンで搭載する実装後に、半導体素子の周囲に洗浄除去可能な材料で構成される保護部を配線基板との間隙を埋めて形成することにより、その後のサーマルグリースや熱伝導性コンパウンド等を半導体素子表面に塗布しても、検査工程でそれらが半導体素子と配線基板との間隙に浸入することを保護部が阻止することができる。検査工程後にグリース等と保護部を洗浄除去して半導体素子と配線基板との間隙に残留物を残すことを防止できるため、半導体素子と配線基板との間隙にアンダーフィル樹脂を充填する際に、障害物がないことからボイドが発生することを抑制できる。その結果、ボイドの無いアンダーフィル樹脂で半導体素子を強固に配線基板に固定して信頼性の高い半導体装置を製造することができる。   According to the method for manufacturing a semiconductor device of the present invention, after mounting the semiconductor element on the wiring board in a face-down manner, the protective portion made of a material that can be washed and removed around the semiconductor element is provided with a gap between the wiring board and the wiring board. By filling and forming, even if the subsequent thermal grease or thermal conductive compound is applied to the surface of the semiconductor element, the protective part prevents them from entering the gap between the semiconductor element and the wiring board in the inspection process. be able to. After the inspection process, the grease and the protective part can be washed away to prevent the residue from remaining in the gap between the semiconductor element and the wiring board, so when filling the gap between the semiconductor element and the wiring board with underfill resin, Since there is no obstacle, it can suppress that a void generate | occur | produces. As a result, it is possible to manufacture a highly reliable semiconductor device by firmly fixing the semiconductor element to the wiring board with an underfill resin having no voids.

以下、本発明の好ましい実施形態について図を参照して説明する。
図1(a)〜(e)は、本発明の一実施形態に係る半導体装置の製造方法の工程を順次示す半導体装置の断面図である。
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
1A to 1E are cross-sectional views of a semiconductor device sequentially illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

図1(a)に示す半導体装置1aは、ベアチップの半導体素子2がバンプ3を介して配線基板4にフェイスダウンで搭載されたフリップチップ実装構造を示している。
半導体素子2は、シリコンなどの半導体基板に電気信号を処理するためのトランジスタ等が設けられ、アルミニウムなどの配線で相互に接続されている。半導体素子2の表面に外部と電気的に接続すべき箇所に引き出された再配線層の露出した図示しない電極が例えばマトリクス状の配置で設けられている。
この電極に配線基板4の電極と金属接合するための突起としてバンプ3が形成されている。
A semiconductor device 1a shown in FIG. 1A shows a flip chip mounting structure in which a bare chip semiconductor element 2 is mounted face-down on a wiring substrate 4 via bumps 3.
The semiconductor element 2 is provided with a transistor or the like for processing an electric signal on a semiconductor substrate such as silicon, and is connected to each other by wiring such as aluminum. On the surface of the semiconductor element 2, exposed electrodes (not shown) of a rewiring layer drawn out to a place to be electrically connected to the outside are provided, for example, in a matrix arrangement.
Bumps 3 are formed on the electrodes as protrusions for metal bonding to the electrodes of the wiring board 4.

バンプ3の形成は、アルミニウム電極上に接着層や、拡散防止層を設け、電気メッキによりバンプ3を形成する方法、ボールボンディングの手法を利用してアルミニウム電極上にボールバンプを形成する方法、アルミニウム電極上に無電解メッキによってバンプを形成する方法、アルミニウム電極上に半田に濡れる金属を着膜した後に、溶融した半田槽に浸漬して形成する方法、物理的成膜法などがある。バンプ3の素材としては、金、銅、ニッケルや、スズ・鉛・インジウム等からなる半田を単独で、あるいは2種以上のバンプを積層して使用することもできる。   The bump 3 is formed by a method in which an adhesive layer or a diffusion prevention layer is provided on the aluminum electrode and the bump 3 is formed by electroplating, a method in which a ball bump is formed on the aluminum electrode by using a ball bonding method, aluminum There are a method of forming bumps on an electrode by electroless plating, a method of forming a metal that gets wet with solder on an aluminum electrode, and then immersing it in a molten solder bath, a physical film forming method, and the like. As a material of the bump 3, a solder made of gold, copper, nickel, tin, lead, indium or the like can be used alone, or two or more kinds of bumps can be laminated.

配線基板4は、ガラス、セラミック、ガラスエポキシ、ポリイミド、フェノール樹脂などを用いることができる。
配線基板4に形成されている配線パターンとしては、ニッケル、銅、チタン、ITO(インジウム・スズ・オキサイド)、クロム、アルミニウム、モリブデン、タンタル、タングステン、金、銀の単体、これらの合金ないしは復合した金属材料を用いて、スパッタリング、蒸着、メッキ及び印刷などの方法で形成することができる。
半導体素子2のバンプ3が位置する箇所に対応する配線パターンの位置に例えばはんだペーストが印刷された図示しない内部接続端子が設けられている。
For the wiring board 4, glass, ceramic, glass epoxy, polyimide, phenol resin, or the like can be used.
The wiring pattern formed on the wiring board 4 includes nickel, copper, titanium, ITO (indium tin oxide), chromium, aluminum, molybdenum, tantalum, tungsten, gold, silver alone, an alloy thereof or a combination thereof. It can be formed by a method such as sputtering, vapor deposition, plating and printing using a metal material.
For example, an internal connection terminal (not shown) on which a solder paste is printed is provided at the position of the wiring pattern corresponding to the position where the bump 3 of the semiconductor element 2 is located.

フェイスダウン実装工程は、例えば配線基板4の内部接続端子と半導体素子2のバンプ3とを位置合わせをして合致させて搭載し、リフロー炉を通してはんだペーストを溶融してはんだ接合を形成する。
これによって、半導体素子2と配線基板4とがバンプ3を介して電気的に接続された半導体装置1aを得ることができる。
In the face-down mounting process, for example, the internal connection terminals of the wiring board 4 and the bumps 3 of the semiconductor element 2 are mounted in alignment with each other, and solder paste is melted through a reflow furnace to form a solder joint.
Thereby, the semiconductor device 1a in which the semiconductor element 2 and the wiring board 4 are electrically connected via the bumps 3 can be obtained.

フェイスダウン実装された半導体装置1aは、検査で異常が発見され、半導体素子2の交換が必要になったときに容易に交換できるようにする場合、半導体素子2と配線基板4との間隙にアンダーフィル樹脂を充填する工程の前に、半導体装置1aの検査工程を行う。
更に、本発明においては、検査工程の前に、保護部形成工程を行う。
When the semiconductor device 1a mounted face down is found to be abnormal when an inspection is found and the semiconductor element 2 needs to be replaced, the gap between the semiconductor element 2 and the wiring board 4 can be changed. Prior to the process of filling the fill resin, an inspection process of the semiconductor device 1a is performed.
Furthermore, in the present invention, a protective part forming step is performed before the inspection step.

保護部形成工程では、図1(b)に示すように、半導体素子2の全部の周縁と配線基板4との間隙を埋める保護部9を形成する。
この保護部9は、配線基板4と半導体素子2との間隙へ異物の浸入を阻止する機能を有する。
そのため、保護部9は半導体素子2と配線基板4との間の間隙の入口である半導体素子2の周縁と配線基板4との間隙を埋めるように形成する。また、半導体素子2と配線基板4間の間隙全てを埋めるように形成しても良い。
In the protective part forming step, as shown in FIG. 1B, a protective part 9 that fills the gap between the entire periphery of the semiconductor element 2 and the wiring substrate 4 is formed.
The protection unit 9 has a function of preventing foreign matter from entering the gap between the wiring board 4 and the semiconductor element 2.
Therefore, the protection unit 9 is formed so as to fill the gap between the peripheral edge of the semiconductor element 2 that is the entrance of the gap between the semiconductor element 2 and the wiring board 4 and the wiring board 4. Further, it may be formed so as to fill all the gaps between the semiconductor element 2 and the wiring board 4.

保護部9を構成する材料は、洗浄により除去できることが必要であり、アンダーフィル樹脂を充填する以前に痕跡を残さずに容易に除去できることが望ましい。
そのため、水で洗浄除去可能な材料又は有機溶剤で洗浄除去可能な材料を用いることが望ましい。
その他に、アルカリ水溶液で洗浄除去又は酸水溶液で洗浄除去可能な材料も用いることができる。
The material constituting the protective part 9 needs to be removable by washing, and it is desirable that the material can be easily removed without leaving a trace before filling with the underfill resin.
Therefore, it is desirable to use a material that can be washed and removed with water or a material that can be washed and removed with an organic solvent.
In addition, materials that can be removed by washing with an aqueous alkali solution or washed with an aqueous acid solution can also be used.

水で洗浄除去可能な材料としては、例えばポリビニルアルコール、デンプン、紙加工用の水溶性樹脂等を挙げることができる。
有機溶剤に溶解性の材料としては、例えばポリ酢酸ビニル、ポリスチレン等を例示することができる。
アルカリ可溶性の材料としては、例えばカルボキシル基やスルホン酸基を有する樹脂を例示することができる。
酸可溶性の材料としては、アクリル酸あるいはメタクリル酸の、モノ又はジメチルアミノエチルエステル、モノ又はジエチルアミノエチルエステル等を例示することができる。
現在の半導体装置の生産工程では、水洗浄,水系溶剤を使用した洗浄が主であるため、水で洗浄除去可能な材料を好ましく用いることができる。
Examples of the material that can be washed and removed with water include polyvinyl alcohol, starch, and a water-soluble resin for paper processing.
Examples of the material soluble in the organic solvent include polyvinyl acetate and polystyrene.
Examples of the alkali-soluble material include a resin having a carboxyl group or a sulfonic acid group.
Examples of the acid-soluble material include mono- or dimethylaminoethyl ester, mono- or diethylaminoethyl ester of acrylic acid or methacrylic acid.
In the current production process of semiconductor devices, water cleaning and cleaning using an aqueous solvent are mainly used. Therefore, a material that can be cleaned and removed with water can be preferably used.

保護部9の形成方法は、例えばポリビニルアルコールを含有する粘稠性の水溶液を細いノズルから半導体素子2の周縁と配線基板4との間に向けて押し出し、半導体素子2の周縁と配線基板4の間隙をポリビニルアルコール水溶液で満たしつつ半導体素子2を囲むように全周囲に半導体素子2と配線基板4の間隙を埋める液体の保護部を形成する。
次に、液体の保護部を加熱して水を蒸発させて硬化した保護部9を形成する。この場合、保護部9は異物が半導体素子2と配線基板4との間隙に浸入することを防止できればよいので、内部まで硬化させる必要はなく、表面だけの部分硬化でも良い。部分硬化とすることにより洗浄除去が容易になる。
硬化した保護部9は、ポリビニルアルコールを含有しているため、水で容易に洗浄除去可能である。
The protective part 9 is formed by, for example, extruding a viscous aqueous solution containing polyvinyl alcohol from a thin nozzle between the peripheral edge of the semiconductor element 2 and the wiring substrate 4, and the peripheral edge of the semiconductor element 2 and the wiring substrate 4. A liquid protection portion for filling the gap between the semiconductor element 2 and the wiring board 4 is formed on the entire periphery so as to surround the semiconductor element 2 while filling the gap with an aqueous polyvinyl alcohol solution.
Next, the protective part 9 which is cured by heating the liquid protective part to evaporate water is formed. In this case, since the protective part 9 is only required to prevent foreign matter from entering the gap between the semiconductor element 2 and the wiring board 4, it is not necessary to cure to the inside, and partial curing of only the surface may be used. By using partial curing, cleaning and removal are facilitated.
Since the cured protective part 9 contains polyvinyl alcohol, it can be easily washed away with water.

このようにして得られた半導体装置1bは、本発明の半導体素子検査構造であり、配線基板4と、配線基板4上にフェイスダウンで実装された半導体素子2と、洗浄除去可能な材料で半導体素子2の周囲に半導体素子2と配線基板4との間隙を埋めて形成された保護部9とを有する構造を有する。
保護部9によって、検査工程において異物が半導体素子2と配線基板4との間隙に浸入することを防止することができる。
The semiconductor device 1b thus obtained is a semiconductor element inspection structure according to the present invention. The semiconductor device 1b has a wiring substrate 4, a semiconductor element 2 mounted face-down on the wiring substrate 4, and a semiconductor that can be cleaned and removed. It has a structure having a protective portion 9 formed by filling the gap between the semiconductor element 2 and the wiring substrate 4 around the element 2.
The protection unit 9 can prevent foreign matter from entering the gap between the semiconductor element 2 and the wiring board 4 in the inspection process.

検査工程の前に、電力が大きく発熱量の大きな半導体素子2が検査工程中に高温となることを防止して所望の検査をすることができるように、図1(c)に示すように、検査用のヒートシンク10を半導体素子2の表面に一時的に設置するヒートシンク設置工程がある場合がある。
近年、半導体素子2の大型化に伴い、半導体素子2の反り等の理由から半導体素子2とヒートシンク10との間に間隙が生じ、ヒートシンク10と半導体素子2とを密着させることが困難になってきている。
そのため、ヒートシンク設置工程においては、サーマルグリースや熱伝導性コンパウンド等の熱伝導性を有する材料で半導体素子2とヒートシンク10との間の間隙を埋める熱伝導性充填層11を設けてヒートシンク10による熱の放散を良好にすることが行われる。
Before the inspection process, as shown in FIG. 1C, in order to prevent the semiconductor element 2 having a large electric power and a large calorific value from becoming high temperature during the inspection process, a desired inspection can be performed. There may be a heat sink installation step of temporarily installing the heat sink 10 for inspection on the surface of the semiconductor element 2.
In recent years, with an increase in size of the semiconductor element 2, a gap is generated between the semiconductor element 2 and the heat sink 10 due to warpage of the semiconductor element 2, and it becomes difficult to make the heat sink 10 and the semiconductor element 2 adhere to each other. ing.
Therefore, in the heat sink installation step, a heat conductive filling layer 11 is provided to fill a gap between the semiconductor element 2 and the heat sink 10 with a material having thermal conductivity such as thermal grease or a heat conductive compound, and the heat generated by the heat sink 10. It is done to improve the emission of

検査工程では、半導体素子2の動作検査や半導体素子2と配線基板4との接続検査を行う。
このとき異常がある半導体素子2の交換が必要になった場合には、半導体素子2はアンダーフィル樹脂で配線基板4に接着されていないので、容易に交換できる。
検査工程は、例えばプローバーに半導体素子2を搭載した配線基板4をセッティングして行う。
In the inspection process, an operation inspection of the semiconductor element 2 and a connection inspection between the semiconductor element 2 and the wiring board 4 are performed.
If it is necessary to replace the defective semiconductor element 2 at this time, the semiconductor element 2 can be easily replaced because it is not bonded to the wiring board 4 with the underfill resin.
The inspection process is performed, for example, by setting the wiring board 4 on which the semiconductor element 2 is mounted on a prober.

ヒートシンク設置工程あるいは検査工程で、図1(c)に示す半導体装置1cは、半導体素子2の周囲に半導体素子2と配線基板4の間隙を埋めて形成した保護部9が設けられているため、ヒートシンク10と半導体素子2との間に充填した流動性の熱伝導性充填層11が流下しても、保護部9によって熱伝導性充填層11が半導体素子2と配線基板4との間隙に浸入することを防止することができる。   In the heat sink installation process or the inspection process, the semiconductor device 1c shown in FIG. 1C is provided with the protective portion 9 formed by filling the gap between the semiconductor element 2 and the wiring board 4 around the semiconductor element 2. Even if the fluid heat conductive filler layer 11 filled between the heat sink 10 and the semiconductor element 2 flows down, the heat conductive filler layer 11 enters the gap between the semiconductor element 2 and the wiring substrate 4 by the protection unit 9. Can be prevented.

検査工程後、ヒートシンクを取り外し、サーマルグリース等11を有機溶剤で洗浄して除去し、保護部除去工程で更に保護部9を水などで洗浄除去する。
洗浄方法としては、例えば洗浄液中に半導体素子2を搭載した配線基板4を浸漬し、超音波を与えることによって洗浄する方法を採用することができる。
これによって、図1(d)に示すように、半導体素子2と配線基板4との間隙にバンプ3以外何もない検査済のフェイスダウン実装構造1dが実現される。
After the inspection process, the heat sink is removed and the thermal grease 11 is washed away with an organic solvent, and the protective part 9 is further washed away with water in the protective part removing process.
As a cleaning method, for example, a method of cleaning by immersing the wiring board 4 on which the semiconductor element 2 is mounted in a cleaning liquid and applying ultrasonic waves can be employed.
As a result, as shown in FIG. 1D, an inspected face-down mounting structure 1d in which there is nothing other than the bump 3 in the gap between the semiconductor element 2 and the wiring board 4 is realized.

次のアンダーフィル樹脂充填工程で、半導体素子2と配線基板4との間隙にアンダーフィル樹脂5を例えば細いノズルから押し出して充填する。
アンダーフィル樹脂としては、例えば無機フィラーを含有する液状の熱又は紫外線硬化性樹脂組成物を例示することができる。
無機フィラーの配合は熱膨張率を低下させ、ボイドの発生を抑制することができる。
無機フィラーとしては、例えば、Al23、MgO、BN、AlN、SiO2等が使用できる。また、熱硬化性樹脂としては、エポキシ樹脂、フェノール樹脂、シアネート樹脂、またはポリフェニレンエーテル樹脂が使用できる。耐熱性の点からエポキシ樹脂を好ましく使用することができる。
In the next underfill resin filling step, the underfill resin 5 is filled into the gap between the semiconductor element 2 and the wiring board 4 by, for example, being extruded from a thin nozzle.
Examples of the underfill resin include a liquid heat or ultraviolet curable resin composition containing an inorganic filler.
The blending of the inorganic filler can reduce the coefficient of thermal expansion and suppress the generation of voids.
As the inorganic filler, for example, Al 2 O 3 , MgO, BN, AlN, SiO 2 or the like can be used. Moreover, as a thermosetting resin, an epoxy resin, a phenol resin, cyanate resin, or polyphenylene ether resin can be used. From the viewpoint of heat resistance, an epoxy resin can be preferably used.

アンダーフィル樹脂充填工程では、半導体素子2と配線基板4との間隙にサーマルグリース等の残存が無くバンプ3以外何もない状態であるため、半導体素子2と配線基板4との間隙に液状硬化性樹脂組成物を注入すると、毛細管現象によって液状硬化性樹脂組成物は半導体素子2と配線基板4との間隙に間隙無く充填され、ボイドの発生が可及的に抑制される。   In the underfill resin filling process, no thermal grease or the like remains in the gap between the semiconductor element 2 and the wiring board 4 and there is nothing other than the bump 3, so that the liquid curable property is formed in the gap between the semiconductor element 2 and the wiring board 4. When the resin composition is injected, the liquid curable resin composition is filled in the gap between the semiconductor element 2 and the wiring substrate 4 without a gap by capillary action, and generation of voids is suppressed as much as possible.

アンダーフィル樹脂充填工程後、アンダーフィル樹脂を加熱して又は紫外線を照射して硬化させ、半導体素子2と配線基板4の間隙に充填したアンダーフィル樹脂5で半導体素子2を配線基板4へ接着させる。
アンダーフィル樹脂5で半導体素子2と配線基板4が固着されて半導体素子2と配線基板4の熱膨張差が反り変形で吸収され、バンプ3に大きな剪断応力や引張り応力を生じさせないため、断線不良に至る寿命が大幅に改善する。
After the underfill resin filling step, the underfill resin is heated or cured by irradiating ultraviolet rays, and the semiconductor element 2 is adhered to the wiring board 4 with the underfill resin 5 filled in the gap between the semiconductor element 2 and the wiring board 4. .
Since the semiconductor element 2 and the wiring board 4 are fixed by the underfill resin 5, the thermal expansion difference between the semiconductor element 2 and the wiring board 4 is absorbed by warp deformation, and a large shearing stress or tensile stress is not generated in the bump 3, thus causing disconnection failure The life to reach is greatly improved.

以上のように、本実施形態に係る半導体装置の製造方法により製造された半導体装置1eは、配線基板4にフェイスダウン実装された半導体素子2と配線基板4の間隙に充填されたアンダーフィル樹脂5にボイドの発生が可及的に抑制されたものであるため、アンダーフィル樹脂5の十分な接合強度が得られ、半導体素子2と配線基板4との接続信頼性が高い半導体装置を提供することができる。   As described above, the semiconductor device 1e manufactured by the semiconductor device manufacturing method according to the present embodiment has the underfill resin 5 filled in the gap between the semiconductor element 2 face-down mounted on the wiring board 4 and the wiring board 4. Since the generation of voids is suppressed as much as possible, a sufficient bonding strength of the underfill resin 5 can be obtained, and a semiconductor device having a high connection reliability between the semiconductor element 2 and the wiring substrate 4 can be provided. Can do.

本発明は、上述した実施形態に限定されるものではない。
例えば、保護部は洗浄除去可能であればよいので、硬化しない素材のパテ状のものであっても良い。
The present invention is not limited to the embodiment described above.
For example, the protective part only needs to be washable and removable, and may be a putty-like material that does not harden.

本発明の半導体装置の製造方法は、接続信頼性の高いフリップチップ実装された半導体装置を製造することができる。
また、本発明の半導体素子検査構造は、フリップチップ実装された半導体装置の検査工程での接続信頼性を低下させない半導体装置を製造することができる。
The semiconductor device manufacturing method of the present invention can manufacture a flip-chip mounted semiconductor device with high connection reliability.
In addition, the semiconductor element inspection structure of the present invention can manufacture a semiconductor device that does not deteriorate the connection reliability in the inspection process of a flip-chip mounted semiconductor device.

(a)〜(e)は、本発明の一実施形態に係る半導体装置の製造方法の工程を順次示す半導体装置の断面図である。(A)-(e) is sectional drawing of the semiconductor device which shows the process of the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention sequentially. (a)はフリップチップ実装された半導体装置の概略断面図、(b)はアンダーフィル樹脂を充填した半導体装置を示す概略断面図である。(A) is a schematic sectional drawing of the semiconductor device by which the flip chip mounting was carried out, (b) is a schematic sectional drawing which shows the semiconductor device filled with underfill resin. サーマルグリース等が半導体素子と配線基板の間隙に浸入した状態を示す概略断面図である。It is a schematic sectional drawing which shows the state in which thermal grease etc. penetrate | invaded into the clearance gap between a semiconductor element and a wiring board. 熱伝導性シートを用いた半導体装置を示す概略断面図である。It is a schematic sectional drawing which shows the semiconductor device using a heat conductive sheet.

符号の説明Explanation of symbols

1a〜1e 半導体装置
2 半導体素子
3 バンプ
4 配線基板
5 アンダーフィル樹脂
9 保護部
10 ヒートシンク
11 熱伝導性充填層
DESCRIPTION OF SYMBOLS 1a-1e Semiconductor device 2 Semiconductor element 3 Bump 4 Wiring board 5 Underfill resin 9 Protection part 10 Heat sink 11 Thermally conductive filling layer

Claims (7)

配線基板上に半導体素子をフェイスダウンで実装する実装工程と、
前記半導体素子の周囲に洗浄除去可能な材料で構成される保護部を前記半導体素子と前記配線基板との間隙を埋めて形成する保護部形成工程と、
前記半導体素子の動作検査及び前記半導体素子と前記配線基板との接続検査を行う検査工程と、
前記保護部を洗浄除去する保護部除去工程と、
前記検査工程の前に、前記半導体素子の表面にヒートシンクを設置するヒートシンク設置工程と、
を有することを特徴とする半導体装置の製造方法。
Mounting process for mounting semiconductor elements face-down on a wiring board;
A protective part forming step of forming a protective part made of a material that can be washed and removed around the semiconductor element by filling a gap between the semiconductor element and the wiring board;
An inspection process for performing an operation inspection of the semiconductor element and a connection inspection between the semiconductor element and the wiring board;
A protective part removing step for washing and removing the protective part;
Before the inspection step, a heat sink installation step of installing a heat sink on the surface of the semiconductor element,
A method for manufacturing a semiconductor device, comprising:
前記保護部除去工程の後に、前記配線基板と前記半導体素子との間隙にアンダーフィル樹脂を充填するアンダーフィル充填工程を有することを特徴とする請求項1記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, further comprising an underfill filling step of filling an underfill resin in a gap between the wiring board and the semiconductor element after the protective part removing step. 前記ヒートシンクと前記半導体素子の間に熱伝導性充填層を設ける工程を有することを特徴とする請求項1又は2記載の半導体装置の製造方法。 The method according to claim 1, wherein further comprising the step of providing a thermally conductive filler layer between said heat sink and said semiconductor element. 前記検査工程後、設置した前記ヒートシンクと前記熱伝導性充填層を取り除く工程を有することを特徴とする請求項記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 3 , further comprising a step of removing the installed heat sink and the thermally conductive filling layer after the inspection step. 前記保護部が、水溶性、油溶性、アルカリ可溶性又は酸可溶性の材料で構成されていることを特徴とする請求項1乃至4のいずれか一項記載の半導体装置の製造方法。 The protective portion is water-soluble, a manufacturing method of an oil-soluble, the semiconductor device of any one of claims 1 to 4, characterized in that it is composed of a material of an alkali-soluble or acid-soluble. 前記保護部がポリビニルアルコールを含有することを特徴とする請求項記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5, wherein the protective part contains polyvinyl alcohol. 配線基板と、前記配線基板上にフェイスダウンで実装された半導体素子と、洗浄除去可能な材料で前記半導体素子の周囲に前記半導体素子と前記配線基板との間隙を埋めて形成された保護部とを有するとともに、
前記半導体素子の上に熱伝導性充填層を介してヒートシンクが設置されていることを特徴とする半導体素子検査構造。
A wiring board; a semiconductor element mounted face-down on the wiring board; and a protective part formed by filling a gap between the semiconductor element and the wiring board around the semiconductor element with a material that can be cleaned and removed. and it has a,
A semiconductor element inspection structure, wherein a heat sink is installed on the semiconductor element via a thermally conductive filling layer .
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