JP5041402B2 - Interface circuit and electronic equipment - Google Patents

Description

  The present invention particularly relates to an interface circuit and an electronic apparatus suitable for use in controlling data transfer between a processing device such as a CPU and a memory.

  In data transfer between a CPU and a memory, burst mode transfer is known in which a plurality of data is transferred continuously by a single address designation. Burst mode transfer is frequently used in electronic devices such as mobile phones because the data transfer speed is improved by the amount that it is not necessary to execute a cycle for transferring addresses every time data is transferred.

  FIG. 4 shows a configuration example of a memory interface when a CPU mounted on a mobile phone uses the burst mode described above to acquire data from a memory in synchronization with a clock (Clock).

In the memory interface of FIG. 4, the main body chip 100 on which the CPU is mounted receives a wait signal (M_WAIT) from the memory 200, and outputs a chip select signal (CS) in synchronization with the timing to obtain necessary data. To do.
At this time, the wait signal (M_WAIT) is pulled up by a resistor, but the wait signal (M_WAIT) received from the memory 200 contains noise due to problems such as inter-signal interference and external circuit routing. At this time, the CPU may erroneously determine that the wait has been released, fail to establish synchronization, and may malfunction or hang up.

  Conventionally, in order to prevent malfunction due to noise at the time of fetching memory data, two types of delay circuits are added to the data strobe signal, a signal to which a delay is added by one delay circuit is used as a clock, and the other delay circuit is used. A memory device control circuit that takes in data from a memory using a signal with a delay as an enable signal has been proposed (for example, see Patent Document 1).

We also propose a VCR recording circuit with a snow noise removal function that uses two types of counters and timers to record only normal state signals without recording snow noise that occurs when a TV broadcast signal is interrupted. (For example, refer to Patent Document 2).
JP 2006-40318 A JP-A-7-192205

  However, according to the technique disclosed in Patent Document 1, a DDR SDRAM called a DDR (double data rate) mode, in which data is read and written at both rising and falling of a clock to realize a normal double transfer rate. (Double Data Rate Synchronous Dynamic Random Access Memory) is intended for memory devices, which cannot be directly applied to clock synchronous burst mode transfer.

  Further, according to the technique disclosed in Patent Document 2, since a noise is removed using a counter, the upper limit of an allowable operating frequency is low, and a mobile phone on which a CPU operating at a high speed of 100 MHz or more is mounted. It cannot be used for electronic equipment.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an interface circuit and an electronic apparatus that can accurately identify a regular signal and noise and realize highly reliable data transfer. And

In order to solve the above-described problem, an interface circuit according to a first aspect of the present invention provides a signal between the first device and the second device in synchronization with a clock generated by the first device. A phase control unit that delays the phase of the clock by a predetermined time, and a signal generated and output by the second device based on a clock output from the phase control unit a signal generator for generating a timing signal determining whether a synchronizing signal, the possess, the signal generator, a clock output by the phase control unit is connected to a clock input terminal, said second A reset signal generated and output by the first device is connected to the D input terminal and the set terminal, and a control signal generated and output by the first device is connected to the reset terminal. It is a D-type flip-flop with a terminal.

  Further, in the interface circuit of the present invention, the signal generator transfers the signal to the first device when the synchronization signal generated and output by the second device has a predetermined time margin, and the time If there is no margin, the signal may not be transferred to the first device.

  In the interface circuit of the present invention, when the signal generation unit receives a normal synchronization signal generated and output by the second device, the signal generation unit generates a control signal in synchronization with the timing, and generates the control signal. You may comprise so that data may be acquired from this apparatus.

  Further, in the interface circuit of the present invention, the phase control unit is configured by a delay element having a delay time suitable for a time margin added for discrimination of a synchronization signal generated and output by the second device. Also good.

  In the interface circuit of the present invention, the synchronization signal generated and output by the second device is output for synchronization with the first device in a burst mode in which data is transferred in synchronization with a clock. It may be a wait signal.

An electronic device according to a second aspect of the present invention includes an electronic device main body on which a processing device is mounted, a memory module in which data is read / written in synchronization with a clock generated by the processing device, and a phase of the clock. A phase control unit that delays by a predetermined time, and a signal generation unit that generates a timing signal that determines whether or not the weight signal generated and output by the memory module is a normal signal based on a clock output from the phase control unit have a, a memory interface circuit wherein the signal generator, the clock signal output by the phase control unit is connected to the clock input terminal, a synchronization signal is generated and outputted by the second device D input A set connected to a terminal and a set terminal, and a control signal generated and output by the first device connected to a reset terminal Set is a D-type flip-flop with a terminal.

  According to the present invention, it is possible to accurately identify a regular signal and noise and realize highly reliable data transfer.

  FIG. 1 is a block diagram showing a configuration of an electronic apparatus according to an embodiment of the present invention. Here, a portable information terminal such as a mobile phone is exemplified as the electronic device.

  The mobile phone includes a main body chip 1 (electronic device) on which a CPU (processing device) is mounted as a first device, and a plurality of clock-synchronized memory modules (MEM) 20 such as SDRAM and flash memory as a second device. The high-frequency circuit 2 that performs modulation / demodulation for communication with a base station (not shown) is a main component. Note that circuit blocks that manage user interfaces such as an operation unit, a display unit, and a voice input / output unit are not shown.

  In addition to the CPU 11, the main body chip 1 is mounted with a memory controller (MEMC) 12 that reads / writes data of the MEM 20 in one chip. Here, the MEMC 12 is connected to a plurality of MEMs 20 via a memory bus 21, and the memory bus 21 is connected to a plurality of MEMs 20 via an interface circuit 22 (here, a memory interface) of the present invention.

  The interface circuit 22 controls an interface for signal transmission / reception between the MEMC 12 and the MEM 20, and is based on a phase control unit that delays a phase of a clock generated by the CPU 11 by a predetermined time, and a clock output from the phase control unit. And a signal generator that generates a timing signal that determines whether or not the weight signal generated and output by the MEM 20 is a regular signal. Details will be described later.

  FIG. 2 is a circuit configuration diagram of the interface circuit 22 according to the embodiment of the present invention. Here, the connection relationship with peripheral circuits is also shown.

  In FIG. 2, blocks denoted by the same reference numerals as those shown in FIG. 1 are the same as those shown in FIG. As shown in FIG. 2, the interface circuit 22 includes a delay element 221, a D-type flip flop 222 with a set / reset terminal, and an inverter 223.

  The delay element 221 generates a confirmation clock (DCLK) obtained by delaying the clock (Clock) generated by the CPU 11 by an amount corresponding to a margin set in interface design described later, and has a set / reset terminal. It is supplied to the clock input terminal (CLK) of the D type flip-flop 222. For this reason, the delay element 221 operates as a phase control unit that delays the phase of the clock by a predetermined time.

  On the other hand, the chip select signal (CS) generated by the MEMC 12 is supplied not only to the MEM 20 but also to the reset terminal (R) of the D-type flip flop 222 with a set reset terminal. Also, the D input terminal (D) and the set terminal (S) of the D type flip flop 222 with a set reset terminal are supplied with a wait signal (M_WAIT) generated and output by the MEM 20 via the inverter 223. The output (/ Q) is supplied to the CPU 11 via the MEMC 12 as a determination timing signal.

  In the circuit configuration of the interface circuit 22 described above, on the CPU 11 side, in order to synchronize with the MEM 20, a wait signal (M_WAIT) output by the MEM 20 is captured at the rising edge of the generated clock (Clock). Here, a wait signal (M_WAIT) in the case where the inverter 223 is added to be active low will be described. The active low wait signal (M_WAIT) indicates a wait state when M_WAIT is at a low level, and indicates a wait release state when M_WAIT is at a high level.

  The CPU 11 determines that the wait has been released in a state where the high level is maintained for the setup time or more at the rising edge of the clock (Clock), and proceeds to the next stage operation such as data reading.

Here, the confirmation clock (DCLK) obtained by delaying the clock (Clock) supplied to the MEM 20 is input to the D-type flip-flop 222 with a set / reset terminal, so that the designer can connect the CPU 11 and the memory module 20. The M_WAIT signal having no margin provided when designing the interface is determined to be noise and the M_WAIT signal is not input to the CPU 11, but the M_WAIT signal having a margin is input to the CPU 11 as a normal signal, and the It prevents malfunction. Therefore, the delay element 221 needs to have a delay capacity that matches the set margin.
Therefore, the D-type flip-flop 222 with the set / reset terminal described above determines whether the signal (M_WAIT) generated and output by the MEM 20 is a normal signal based on the clock (DCLK) output from the delay element 221. It operates as a signal generator that generates the determined timing signal.

  FIG. 3 is a timing diagram cited for explaining the operation of the interface circuit 22 according to the embodiment of the present invention.

  3A shows a clock (Clock) supplied from the CPU 11 to the MEM 20, FIG. 3B shows a confirmation clock (DCLK) output from the delay element 221, and FIG. 3C shows a read generated by the CPU 11. A chip select signal (CS) generated by the MEMC 12 based on the write command and supplied to the memory 20, FIG. 3D shows a wait signal (M_WAIT) supplied from the MEM 20 to the CPU 11, and FIG. 3 shows the reset terminal input (CS) of the D-type flip-flop 222, FIG. 3F shows the set terminal input (/ M_WAIT), FIG. 3G shows the D input terminal (/ M_WAIT), and FIG. ) Indicates the / Q output terminal (/ Q), respectively.

In the timing chart of FIG. 3, at the true wait release timing (indicated by reference sign B in FIG. 3), the MEM 20 waits for a wait signal (low level) with respect to the rising edge of the clock (Clock) supplied from the CPU 11. Set M_WAIT) to high level at the timing of wait release and output.
The interface designer employs the MEM 20 that has no problem even if the time margin M corresponding to the delay capacity of the delay element 221 is added to the minimum setup time S (for example, 5 ns) set in advance by the CPU 11. For this reason, the phase of the original clock (Clock) is controlled by the delay element 221 so that the rising portion of the confirmation clock (DCLK) just overlaps the portion corresponding to the time margin M.

  The high-level wait signal (M_WAIT) is input via the inverter 223. The output (/ Q) of the D-type flip flop 222 with set / reset terminal becomes high level, and the CPU 11 has the D-type flip with set / reset terminal. The true wait release timing can be determined by referring to the output (/ Q) of the flop 222. That is, the CPU 11 determines that the wait has been released while the high level is maintained for the setup time S + time margin M at the rising edge of the confirmation clock (DCLK), and proceeds to the next stage operation such as data reading. To do.

  On the other hand, when a logically high level noise signal that is not the original wait signal is output (indicated by symbol A in FIG. 3), the noise signal is a signal that does not satisfy the time margin M set by the designer. Because there is a deviation from the rising edge of the corresponding confirmation clock (DCLK), the output (/ Q) of the D-type flip flop 222 with the set-reset terminal remains low at the rising edge of the confirmation clock (DCLK). Therefore, the CPU 11 does not determine the noise signal as the wait release timing.

  As described above, the interface circuit 22 according to the embodiment of the present invention sets the phase of the clock generated by the first device (for example, the CPU 11) to a predetermined time by the phase control unit including the delay element 221 and the like. A confirmation clock is output with a delay, and a timing generator such as the D flip-flop 222 with a set / reset terminal based on the confirmation clock generates a synchronization signal generated and output by the second device (for example, MEM20). A timing signal for determining whether or not the signal is generated is generated and output to the CPU 11. Thus, the CPU 11 can determine whether or not the synchronization signal is a regular synchronization signal output from the MEM 20, and can avoid a malfunction or hang-up that occurs due to the failure to establish synchronization.

The electronic device according to the embodiment of the present invention includes an electronic device main body on which the CPU 11 is mounted, and a MEM 20 in which data is read / written in synchronization with a clock generated by the CPU 11, and the CPU 11 and the MEM 20 are provided. A memory interface (for example, the interface circuit 22) to be interfaced outputs a confirmation clock by delaying a clock phase by a predetermined time by a phase control unit including a delay element 221 and the like, and sets and resets based on the confirmation clock The timing generation unit such as the terminal-equipped D flip-flop 222 or the like generates a timing signal that determines whether or not the wait signal generated and output by the MEM 20 is a regular signal, and outputs the generated timing signal to the CPU 11.
As a result, the main body chip 1 can receive only a legitimate signal among the wait cancellation signals output from the memory 20, and avoids malfunctions or hang-ups that occur due to failure to establish synchronization. Therefore, highly reliable data transfer can be realized. In addition, since the restriction on the operating frequency is eliminated compared with a method of removing noise using a counter, it can be used for electronic devices such as mobile phones on which a CPU operating at a high speed of 100 MHz or more is mounted. it can.

  In addition, according to the above-described embodiment of the present invention, only a mobile phone is illustrated as an electronic device. However, the present invention is not limited to a mobile phone and can be similarly applied to a PDA (Personal Digital Assistants), a game machine, and the like. .

It is a block diagram which shows the structure of the electronic device which concerns on embodiment of this invention. It is a block diagram of the interface circuit which concerns on embodiment of this invention. FIG. 5 is an operation timing diagram cited for explaining the operation of the interface circuit according to the embodiment of the present invention. It is a block diagram of the interface circuit which does not have the conventional noise countermeasure circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Main body chip (electronic device), 2 ... High frequency circuit part, 11 ... CPU (1st apparatus), 12 ... Memory controller (MEMC), 20 ... Memory module (MEM) (2nd apparatus), 21 ... Memory Bus, 22 ... interface circuit, 221 ... delay element, 222 ... D type flip-flop with set / reset terminal, 223 ... inverter.

Claims (6)

An interface circuit that transmits and receives signals between the first device and the second device in synchronization with a clock generated by the first device,
A phase controller that delays the phase of the clock by a predetermined time;
A signal generation unit that generates a timing signal that determines whether or not a signal generated and output by the second device is a regular synchronization signal based on a clock output by the phase control unit;
I have a,
The signal generator is
A clock output from the phase control unit is connected to a clock input terminal, and a synchronization signal generated and output by the second device is connected to a D input terminal and a set terminal and generated and output by the first device. An interface circuit comprising a D-type flip-flop with a set-reset terminal, wherein a control signal is connected to a reset terminal . The signal generator is
When the synchronization signal generated and output by the second device has a predetermined time margin, the synchronization signal is transmitted to the first device. When the synchronization signal does not have the time margin, the synchronization signal is transmitted to the first device. The interface circuit according to claim 1, wherein the interface circuit is not transmitted to a device. The signal generator is
The control signal is generated at the timing when a normal synchronization signal generated and output by the second device is received, and data is acquired from the second device. Or the interface circuit of 2. The phase control unit
4. The delay element according to claim 1, wherein the delay element has a delay time suitable for a time margin added for discrimination of a synchronization signal generated and output by the second device. 5. Interface circuit. The synchronization signal generated and output by the second device is a wait signal output for synchronization with the first device in a burst mode in which data is transferred in synchronization with a clock. The interface circuit according to claim 1. An electronic device main body on which the processing device is mounted;
A memory module in which data is read and written in synchronization with a clock generated by the processing device;
A phase control unit that delays the phase of the clock by a predetermined time, and a timing signal that determines whether or not the wait signal generated and output by the memory module is a regular signal based on the clock output by the phase control unit A memory interface circuit including a signal generation unit for generating;
I have a,
The signal generator is
A clock output from the phase control unit is connected to a clock input terminal, and a synchronization signal generated and output by the second device is connected to a D input terminal and a set terminal and generated and output by the first device. An electronic apparatus comprising a D-type flip-flop with a set-reset terminal, wherein a control signal is connected to a reset terminal .

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