JP5043682B2 - Output buffer with slew rate control using inversely proportional process dependent reference current - Google Patents

Description

  The present invention relates to output buffers for use in integrated circuits, and more particularly to slew rate control of such output buffers.

High-speed data buses such as PCIX 2.0 have requirements regarding fluctuations in slew rate. In this case, the slew rate is the rate of change of the output signal voltage . For example, in PCI 2.0, the slew rate requirement is 1.8 V / ns <slew rate <3.0 V / ns.
One technique for performing slew rate control is to construct an output buffer replication circuit that accurately indicates the output slew rate.
The slew rate control current is then adjusted until the replicate slew rate measurement is within range.

  To properly adjust the replication circuit, an external time base and slew rate measurement technique is required.

  In the manufacture of integrated circuits, even if the same parts are manufactured at the same manufacturing facility, the performance capability of the integrated circuits manufactured varies as the manufacturing process varies. Thus, the integrated circuit behaves differently depending on process variations and operating ranges. As a result, the integrated circuit is classified into “first corner” and “slow corner” based on performance. In the first corner, integrated circuits perform faster due to variations in factors such as process, voltage, or temperature. Process variations can include factors such as threshold voltage (VT), gate length, input capacitance, sheet resistance, and gate-drain capacitance.

  Integrated circuits operating in the first corner typically have process characteristics that make performance faster. Such process characteristics include low threshold voltage, short gate length, low input capacitance, and the like. Similarly, a high supply voltage VDD can also improve the performance of the integrated circuit. The operation of the slow corner integrated circuit is slow due to factors such as low VDD and high VT. Of particular interest herein is changing the performance of the output driver circuit due to changes in process, voltage, and / or temperature (PVT).

  As performance changes due to process, voltage, and temperature, it becomes difficult to reliably meet slew rate requirements through normal process variations. That is, the output signal changes too early or too late to meet the slew rate requirement.

  Accordingly, it is desirable to provide an output driver circuit that provides a more constant slew rate when the process, voltage, and / or temperature (PVT) affecting performance changes. . As the PVT changes, one open-ended (no feedback) solution is used that provides a more constant slew rate.

  In one embodiment, this solution provides a way to reduce the slew rate variation of the integrated circuit output drive. In the method, generating a first performance dependent current, generating a reference current, and generating a third current inversely proportional to the performance using the reference current and the performance dependent current And supplying this third current to the gate of the first transistor circuit that forms part of the output drive circuit and thereby controls the slew rate when the PVT varies.

  In another embodiment, an integrated circuit comprising an output circuit including a first transistor connecting an output terminal of the integrated circuit to a first power supply node when data output from the output circuit is a first value. Is provided. This first transistor is connected to receive a gate current that is inversely proportional to the performance of the output circuit. Therefore, the slew rate remains constant even if the performance changes due to PVT variations.

BEST MODE FOR CARRYING OUT THE INVENTION

  The present invention can be further understood with reference to the following drawings, and various objects, features, and advantages will be apparent to those skilled in the art.

  FIG. 1 shows the pull-down portion of the output stage of the integrated circuit. Transistor 101 pulls pad 103 low when it is turned on and activated as a result of the DATA sent to node 102 being zero. If the gate current from the power supply 107 is ideally constant, the output slew rate variation with respect to process, voltage and temperature (PVT) will be substantial (2: 1 or greater). Alternatively, if the gate current is inversely proportional to the PVT, that is, if the gate current decreases for improved performance due to PVT variations, the gate current may be reduced by process, voltage, and / or temperature. Will more closely match the gate current required for a more constant or substantially constant output slew rate through the variation of.

  The high level block diagram of FIG. 2 shows gate current inversely proportional to performance changes due to process, voltage, and temperature. That is, the current decreases as performance improves. The reverse is also true. In the embodiment of FIG. 2, a reference current is generated in the reference current generation circuit 201, and a process dependent current is generated in the process dependent current generation circuit 203. Next, this processing dependent current is subtracted from the reference current of the subtraction circuit 205. This difference current is supplied as the gate current of the transistor of the output drive stage 207.

FIG. 3 shows an embodiment of the reference current generation circuit 201. The external register REXT 301 is connected to the output terminal of the integrated circuit of the pad 303. Since this register is external, for example, a high-precision register having an accuracy of 1% or more can be used. The voltage at pad 303 is compared with voltage VREF310. This voltage VREF 310 is a voltage supplied to the comparator 305 from the voltage divider formed by the registers 307 and 308. The current through variable resistor (R _TRIM ) 309 is mirrored through transistors 311 and 315. The reference current I _OUT is used as the output of the reference current generation circuit 201.

In operation, the voltage on the pad 303 is changed by the variable register 309 until the comparator 305 detects a match between the voltage on the pad 303 and the voltage supplied to the comparator from the voltage divider. When matching occurs, VIO, registers 307, 308, and current is determined by the known voltage of the pad 303 is determined by the known resistance of REXT301, said current generates a reference current _{I OUT} are mirrored internally .

In one embodiment shown in FIG. 3, resistor 301R _EXT = 114Ω, N = 37 (N is the transistor size ratio), resistor 309R _TRIM = N × R _EXT , and I _{OUT to} transistor 315 is
I _out = (V _IO / 2) × (1 / R _EXT ) × (1 / N) = V _IO / 4000
It is.

Note that a more stable supply voltage may be used if the voltage _VIO fluctuates unacceptably. Other errors in the output current I _OUT may be caused by the N ratios of the transistors 311, 313, and 315 not being perfectly matched. In addition, the low differential amplification gain in the comparator 305 may cause a certain amount of error.

FIG. 4 shows an embodiment of the process dependent current generation circuit 203. The embodiment of FIG. 4 shows the steps of generating a process dependent current proportional to the performance using PMOS transistors 401, 403, and 405 and the performance using NMOS transistors 411, 413, and 415. Next, in obtaining the gate current used to drive the transistor in the output stage 207, a current proportional to performance, such as shown as _IPVT , is used in the subtractor circuit 205 (see FIG. 2). .

Two subtracting circuits may be used to supply current to the pull-up and pull-down portions of the output driver circuit. The process dependent current is subtracted from the reference current. The resulting differential current functions as a current reference that drives an output transistor that connects its output terminal to either the high or low power supply voltage of the output stage. For integrated circuits operating in the first corner, the process dependent current supplied by the circuit shown in FIG. 4 is higher than in integrated circuits operating in the slow corner. In this case, the process-dependent current at the slow corner is low. Without the teachings herein, these integrated circuits operating in the fast corner and slow corner could each have unacceptably different slew rates.

FIG. 5A is a schematic diagram of an output buffer circuit that utilizes the slew rate control discussed herein. Current references 501 and 503 supply current to the gates of transistors 505 and 507, respectively. As a result, the pad 502 is pulled up or pulled down in accordance with a control signal supplied to the gates of the transistors 501 and 503. Other parts of the output driver, such as the additional description shown in FIG. 1, are omitted for simplicity. The pull-down portion of the output driver, including current reference 503, supplies current to the gate of transistor 507 (generated by the method described with respect to FIG. 2). An integrator including a transistor 507 and a gate-drain capacitance Cgd 509 associated with the transistor 507 is formed in the output stage. The pull-up portion of the output buffer operates in a similar manner.

なお、Ｃは定数である。
Ａｖが大きい場合、入力がゲートの増幅器のしきい値に到達する前のスルーレートは、

であり、ｎＩ_ＲＥＦは電流源５１０により供給される電流である。出力スルーの間、

である。 The integrator formed by the circuit shown in FIG. 5A can also be represented as shown in FIG. 5B. The integrator includes a current source 510 that supplies an amplifier 511 having a gain Av, and a capacitor 512. Current source 510 represents current source 501 or 503, and capacitor 512 represents the gate-drain capacitance associated with transistor 505 or 507. The integrator of FIG. 5 is expressed by the following equation.

C is a constant.
If Av is large, the slew rate before the input reaches the gate amplifier threshold is

NI _REF is the current supplied by the current source 510. During output through

It is.

FIG. 6 shows the operation of the subtraction circuit 205 of FIG. 2 for supplying the current used in FIG. The reference current I _REF 601 is supplied by the reference current generation circuit 201. This current may be substantially constant through process and voltage variations, or may vary somewhat as described further herein. The process-dependent current I _PVT 603 generated by the circuit as shown in FIG. 4 is subtracted from the reference current, and the difference current I _SLEW is supplied as a gate current to the transistor 507 (see FIG. 5) and the like. . Note that this gate current I _SLEW decreases as performance improves.

7, as an I _in constant (see 510 in FIG. 5), which is exemplified how the pad voltage and V _in is how to change, V _in the supply voltage pad (e.g. The voltage of the gate of the output transistor connected to the power supply or ground), and Av represents the gain of the output circuit. Note that I _in quickly charges the input capacitance before and after output slew.

FIG. 8 illustrates an embodiment of an output buffer circuit according to an embodiment of the present invention. The generated reference current as shown in FIG. 3 is supplied to the node 801. Process dependent current generation circuits 803 and 805 supply current, which varies directly with performance due to, for example, process, voltage, and temperature changes. Process dependent current generation circuits 803 and 805 supply current to summing nodes 807 and 809, respectively. Here, a copy of the reference current supplied to node 801 is also supplied. The process dependent current is subtracted from the reference current at summing nodes 807 and 809 to generate the gate current 605 (I _SLEW ) shown in FIG. When the input data supplied to the node 815 is 0, the value is I _REF −I _PVT , and the current supplied to the gate of the transistor 811 through the node 862 and the transistor 812 is generated in the branch 807a. Transistor 812 functions as a pass gate that is controlled to turn on when skew control is used. If the output buffer is configured to operate without using skew control to provide protection when VIO is 3.3V, in certain embodiments, the pass gate may be turned off. In the illustrated embodiment, VIO is approximately 1.5V in the skew control mode.

If the data value supplied to node 815 is 1, a current is generated at branch 809a. The value of this current is I _REF −I _PVT and is supplied to pull-up transistor 817 through node 860 and pass transistor 818. The pass transistor 818 is configured in the same manner as the pass transistor 812. Transistor 814 provides feedback to complete the pre-drive swing. Although not necessary to understand the present invention, the control units CTL1, CTL2, CTL3, CTL4 can be operated in 3.3 volt mode with other circuits (not shown) where skew control is not used. It is configurable. This allows the same output driver to be used in different operating modes and limits the output capacity in certain embodiments of the invention. In 3.3 volt operation, skew control is not used. Therefore, since it is not necessary for understanding the present invention, details for providing such a function are omitted. In the skew control mode, VIO is about 1.5V, CTL1, CTL2, and CTL4 are about 3.3V, and CTL3 = 0.

Output logic often utilizing the VDD without example V _io, provided in different power plane, between the two power planes, for example where the data at node 815 is received, the well-known in the art Note that a suitable circuit as an interface may be required to connect in a manner.

  Further, FIG. 8 shows an embodiment where additional pull-up and pull-down circuits are provided to complete the pre-drive switch. Such a circuit may be utilized to assist in changing the logic level within an allotted time, eg, bit time. In the exemplary embodiment, the value of output pad 869 is fed back to node 850. As a result, either the transistor 851 or 853 is activated. Thus, when the value of the output pad reaches the target value, the pre-drive is completed more quickly. For example, if the output pad is approaching a logic 1 level, the voltage is fed back to node 850, which causes transistor 853 to begin operation. Due to the data value entered at node 815, transistor 855 is already active. Thus, node 869 is pulled down more fully at the allotted time. Thus, in order to avoid inter-symbol interference (ISI), assistance is provided to ensure that the internal node swing is completed in the allocated time.

であり、Ｖ_ｇｓは、プロセス、電圧、および温度とレジスタ許容度との関数である。図１０を参照すると、電流Ｉ_ＰＶＴが生成される。この電流のプロセス依存はさらに大きく、

である。次に、Ｉ_ＰＶＴはＩ_ＲＥＦから減算されて、図１１に示すゲートＲ電流Ｉ_ＳＬＥＷを生成する。Ｉ_ＰＶＴのカーブはＩ_ＲＥＦのカーブよりも急勾配となっていることから、結果として生じるＩ_ＳＬＥＷは依然としてパフォーマンスに対して反比例している点に留意されたい。さらに、図１１に示すように、Ｒが変化すると電流Ｉ_ＰＶＴとＩ_ＲＦＥも同様に変化する点に留意されたい。Ｒに基づくＩ_ＲＥＦとＩ_ＰＶＴ双方の最小および最大のカーブを図示する。Ｉ_ＲＥＦに対する単一のカーブが図示されているが、カーブは、Ｉ_ＳＬＥＷを生成するためにＩ_ＰＶＴとＩ_ＲＥＦのうち、どちらが使用されたかに基づいても同様に変化することになる。 Referring to FIG. 9, in another embodiment, the reference current is a current that is directly related to performance, such as based on process changes. The reference current is

V _gs is a function of process, voltage, and temperature and resistor tolerance. Referring to FIG. 10, a current I _PVT is generated. The process dependence of this current is even greater,

It is. Next, I _PVT is subtracted from I _REF to generate the gate R current I _SLEW shown in FIG. Note that because the I _PVT curve is steeper than the I _REF curve, the resulting I _SLEW is still inversely proportional to performance. Furthermore, as shown in FIG. 11, it should be noted that as R changes, currents I _PVT and I _RFE change as well. _{Figure 6} illustrates the minimum and maximum curves for both R based I _REF and _{IP PVT} . Although a single curve for I _REF is shown, the curve will change as well based on which of I _PVT or I _REF was used to generate I _SLEW .

  Accordingly, various embodiments have been described for controlling skew with an output buffer. The description set forth herein is exemplary and is not intended to limit the scope of the invention as described in the following claims. Other variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope of the invention as set forth in the claims below. Good.

Pull-down part of the integrated circuit output stage. FIG. 5 is a high-level block diagram illustrating an embodiment for providing a gate current that is inversely proportional to performance changes due to process, voltage, and temperature. FIG. 3 is an explanatory diagram of an embodiment of the reference current generation circuit shown in FIG. 2. FIG. 3 is an explanatory diagram of an embodiment of the process-dependent current generation circuit illustrated in FIG. 2. 1 is a schematic diagram illustrating an embodiment of an output buffer circuit using slew rate control as discussed herein. FIG. 5B is another diagram showing an integrator formed by the circuit shown in FIG. 5A. FIG. 6 is an explanatory diagram showing the operation of the subtraction circuit of FIG. 2 for supplying the current used in FIG. 5. As the voltage at the gate of the output transistor of V _in, when it is I _in is constant, illustration voltage pad showed how varying how in response to changes in V _in. Explanatory drawing of embodiment of the output buffer circuit which concerns on embodiment of this invention. FIG. 6 is an illustration of another embodiment in which the generated reference current is inversely proportional to performance based on, for example, process changes. Explanatory drawing which showed the production | generation of the process dependence electric current stronger and inversely proportional to the electric current of FIG. FIG. 11 is an explanatory diagram showing the operation of another embodiment of the present invention using the generated current as shown in FIGS. 9 and 10;

Claims (8)

A method for reducing fluctuations in the output slew rate of an output driver circuit of an integrated circuit,
Supplying a first current having a constant magnitude inversely proportional to integrated circuit performance to a node connected to the gate of the first transistor of the output driver circuit;
Providing an additional current (855) to the node connected to the gate of the first transistor via a feedback circuit so that the output driver circuit reaches a stable output value. Wherein the output value corresponds to one each of the first and second output supply nodes and the additional current is based on the value of the signal at the output driver. The method further comprises the step of reducing slew rate variation by supplying a second input current having a constant magnitude inversely proportional to performance to a node connected to the gate of the second transistor of the output driver circuit. The method according to 1.   In response to data on an input node having a first value, the first transistor connects the output of the output driver circuit to a first power supply node;
  The method of claim 2, wherein the second transistor connects the output of the output driver circuit to a second power supply node in response to data on the input node having a second value. The method of claim 1, wherein the first current is generated using a reference current and a second current directly related to performance .   An integrated circuit comprising an output circuit and one or more additional transistors (855),
  The output circuit includes a first transistor (817) that connects an output terminal (869) of the integrated circuit to a first power supply node in response to data on an input node having a first value, the first transistor (817). A gate of the transistor is connected to a first node (860) configured to receive a first current inversely proportional to the performance of the output circuit;
  The additional transistor (855) connected to the first node provides an additional current to the first node when the output circuit signal reaches a given output value. Integrated circuit configured in.   The output circuit further comprises a second transistor;
  A gate of the second transistor is connected to a second node configured to receive a second current inversely proportional to the performance of the output circuit;
  6. The integrated circuit of claim 5, wherein the second transistor connects the output terminal to a second power supply node when the data is at a second value.   A first current source for supplying a process dependent current; and a second current source for supplying a reference current, wherein the current through the first node (860) combines the process dependent current and the reference current. The integrated circuit of claim 5 formed by: 8. The integrated circuit according to claim 7, further comprising a current mirror that generates a current corresponding to the reference current proportional to a current value determined by an external resistor and a voltage at an output terminal of the integrated circuit.

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