JP5044323B2 - Semiconductor integrated circuit development support system - Google Patents

Description

  The present invention relates to a support system for development of a semiconductor integrated circuit.

In recent years, with the development of semiconductor technology, the advancement and diversification of semiconductor integrated circuits such as LSI (Large Scale Integration) have progressed, and the development efficiency has become important.
A procedure for developing a semiconductor integrated circuit, that is, a procedure from design to manufacture is generally as follows. When developing a semiconductor integrated circuit, first, a system design, which is an operation level design centering on a functional operation, is performed. Next, logic design at the logic gate level and circuit design for expressing it at the element level are performed. Then, a mask is manufactured, and a wafer manufacturing process called a pre-process for forming a semiconductor integrated circuit on the wafer using the mask is started.

After that, the wafer manufactured in the previous process is tested by the probe test to determine pass / fail, the wafer is divided into chips, and the chips that are determined to be non-defective by the probe test (non-defective chips) are selected and assembled into packages. Do.
The assembled product is debugged by the characteristic evaluation, and when the characteristic is recognized as satisfying a desired value, it is transferred to mass production through a final test by a test program based on a final test specification.

For each of these tests, a device called a tester is used. The tester is an expensive device of tens of millions to hundreds of millions of yen per unit, and the use cost is high. The selection of the tester is an important problem for the user.
For example, Patent Document 1 discloses a technique for selecting a usable tester based on a test program.
JP 2003-270305 A

  However, in the technique of Patent Document 1, a tester can be selected, but a jig used for the test must be appropriately selected from a wide variety, and the jig is selected from various conditions such as performance and cost. There was a problem that it was difficult or complicated to select appropriately. The jig is an auxiliary tool (such as a test board) for testing.

  Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to appropriately select and display a jig candidate used for a test from various conditions in a semiconductor integrated circuit development support system. To do.

In order to solve the above problems, the present invention provides a control device owned by a tester of a test of a semiconductor integrated circuit using a tester and a jig, and a terminal held by a test requester and connected to the control device via a network And a semiconductor integrated circuit development support system. The terminal device includes a display unit that displays an input screen for a client to input a test condition including a test frequency condition and the number of semiconductor integrated circuits simultaneously measured. The control device has a storage unit and a processing unit, and the storage unit stores jig information storing test conditions including a compatible frequency condition and the number of semiconductor integrated circuits that can be measured simultaneously for each of a plurality of jigs. Remember. Processing unit, if the requester has received a test conditions including the frequency condition and simultaneous measurement number input to the input screen of the display unit of the terminal device from the terminal device, refers to the jig information, tests that the received A jig satisfying the condition is extracted, and an instruction is given to display the extracted jig on the display unit of the terminal device.

  According to the present invention, in a semiconductor integrated circuit development support system, candidates for jigs to be used for testing can be appropriately selected and displayed from various conditions, and the user can easily view jigs by looking at the display. You can choose.

The semiconductor integrated circuit development support system of the present invention will be described below with reference to the drawings. Each configuration of the semiconductor integrated circuit development support system 1000 will be described with reference to FIGS. 1 to 5, each process of the semiconductor integrated circuit development support system 1000 will be described with reference to FIGS. 6 to 10, and FIGS. A screen display example will be described with reference to FIG.
In the following description, “test” is a general term for “wafer test (inspection in a wafer state)” and “final test (final inspection after being formed into chips)” regarding a semiconductor integrated circuit.

  FIG. 1 is an overall configuration diagram of a semiconductor integrated circuit development support system. The semiconductor integrated circuit development support system 1000 includes a test company (a test trustee) 1 and a circuit design company (a test client) 2, and each of these devices is connected to each other via a network 4 such as the Internet. ing.

Although only one circuit design company 2 is shown in the drawing, a plurality of circuit design companies 2 may be used.
Although not shown, development of a semiconductor integrated circuit may involve a wafer manufacturing company, a mask manufacturing company, a test jig manufacturing company, or the like.

The test company 1 is an organization that tests semiconductor integrated circuits, includes a control device 10, and owns a plurality of types of testers (not shown). The control device 10 is a computer device such as a personal computer. The control device 10 includes a communication unit 11 for communicating with an external device, a keyboard and the like, an input unit 12 for inputting data, a display unit, and the like, and outputs data. An output unit 13, a storage unit 14 for storing various data, a processing unit 15 configured by a CPU (Central Processing Unit) and the like, and a calculation area of the processing unit 15 configured by a RAM (Random Access Memory) and the like The memory 16 is provided.
The storage unit 14 stores tester model information 141, probe card information 142, tester board information 143, and socket information 144 (details will be described later).

  The circuit design company 2 is an organization that specializes in circuit design of semiconductor integrated circuits, and has a terminal device 20. The terminal device 20 is a computer device such as a personal computer, and includes a display unit 21 that performs screen display.

  FIG. 2 is a diagram showing a basic configuration of a tester and the like. As shown in FIG. 2, the tester 300 includes a power supply unit 301 that supplies a power supply voltage to the semiconductor integrated circuit L to be tested, a driver 302 that inputs a signal to an input terminal of the semiconductor integrated circuit L, and the semiconductor integrated circuit L A comparator 303 that compares the signal output from the output terminal of the semiconductor device with an expected value signal, a pattern generator 304 that generates test data and an expected value input to the semiconductor integrated circuit L, and a signal input to the semiconductor integrated circuit L A timing generator 305 that generates an application timing, a controller 306 that performs each control according to a test program, and a DC test circuit 307 that performs a DC test such as voltage level detection of an output pin are configured.

  The semiconductor integrated circuit L is fixed and connected to the tester 300 by a jig 308 during a test. The jig 308 is, for example, a tester board, a probe card, or a socket. The semiconductor integrated circuit L is fixed and connected to the tester 300 by a tester board and a probe card in the wafer test, and fixed and connected to the tester 300 by a tester board and a socket in the final test.

  FIG. 3 is a configuration diagram of the tester model information 141 (see FIG. 1 as appropriate). The tester model information 141 includes, for each tester model (A to H), the number of pins (“32” to “640”), the maximum frequency (MHz: “20” to “125”), and the simultaneously measurable number (“1”). ”To“ 16 ”) and information on the level of use cost (may be a specific number).

FIG. 4 is a configuration diagram of probe card information 142, tester board information 143, and socket information 144 (see FIG. 1 as appropriate).
The probe card information 142 includes, for each of four types of probe cards (cantilever, vertical probe, thin film probe, and carbon thin film probe), a corresponding frequency (“˜80 MHz” to “˜7 GHz”) and a corresponding number of pins (“˜128”). ~ "257 ~"), simultaneous measurement (degree to which a plurality can be measured simultaneously: "△ (small, for example, corresponding to only one)""○ (medium, for example, corresponding to up to four)""◎ (large. 16))), development cost level (can be a specific number), development / production days ("30 days" to "90 days"), price (per 128 pins: "200,000 yen" ~ Information on “4 million yen”) is stored.

  The tester board information 143 includes four types of tester boards (general-purpose board / manual wiring, custom board / pattern wiring, custom board / layer design, and burn-in board (a board that can support burn-in evaluation, which is a test performed at high temperature)). ), Corresponding frequency ("~ 80MHz" ~ "~ 1GHz"), simultaneous measurement (correspondence to: "△" "○" "◎"), high or low development cost (may be a specific number), development Stores information relating to the production days (“15 days” to “70 days”) and prices (per 128 pins: “300,000 yen” to “1.5 million yen”).

  The socket information 144 includes four types of sockets (general sockets, high-performance sockets, custom sockets, and burn-in sockets (sockets that can support burn-in evaluation)) corresponding frequencies (“˜80 MHz” to “˜125 MHz”). ), Development cost level (may be a specific number), development / production days ("3 days (general product)" to "90 days"), price (per 128 pins: "200,000 yen" to "500,000") Information on “circle”) is stored.

FIG. 5 is an example of an input screen of the display unit 21 (see other figures as appropriate). The outline will be described here, and the details of each process and display will be described later.
When the tester search execution button 2111 is operated by a user of the circuit design company 2 (hereinafter simply referred to as “user”), the tester search is executed. The search result is displayed in the tester model adaptability display area 2115 (for each tester model, “X” is displayed for non-adaptation, “◯” is displayed for adaptability, and “◎” is displayed for adaptability is large).
When the cost estimation execution button 2112 is operated by the user, cost estimation is executed. The cost estimation may be performed separately for the wafer test and the final test, or may be performed simultaneously.

  The target cost input area 2113 is an area where the user inputs a wafer test cost, a final test cost, a wafer jig manufacturing cost, and a final jig manufacturing cost. The total test cost and the total jig manufacturing cost are automatically calculated by the processing unit 15 as the sum of the two immediately above costs.

  The approximate cost display area 2114 is an area for displaying the wafer test cost, final test cost, wafer jig manufacturing cost, and final jig manufacturing cost automatically calculated from various conditions (details will be described later) input by the user. The total test cost and the total jig manufacturing cost are automatically calculated by the processing unit 15 as the sum of the two immediately above costs.

  The notification area 2119 is an area for notifying (displaying) the user about the comparison result between the target cost and the approximate cost, various conditions input by the user, and the like.

  The device outline setting input area 2116 includes a device type, device application, 1 power supply system number, die size (chip area), 1 device pin number, package (type), on-chip memory, AD (analog / This is an area where the user inputs digital) conversion and option settings (when the “valid” is selected, the “perform device detailed setting” button is operated).

  The test outline setting area 2117 is DFT (Design for Testability) / BIST (Built In Self Test) / SCAN (Semiconductor integrated circuit by flip-flop chaining) Test method for circuit L. For details, refer to Japanese Patent Application Laid-Open No. 2001-141784, etc., BOST (Built Out Self Test: test method for semiconductor integrated circuit L performed by adding a test function on a tester board), 1), Test category (No. 2), Test content, Wafer test maximum frequency, Total wafer test pattern size, Final test maximum frequency, Final test total pattern size, Option setting (When “Enable” is selected, “Detailed setting of test” This is an area in which the user inputs the “operate” button.

  The simultaneous measurement setting input area 2118 is an area where the user inputs the number of simultaneously measured semiconductor integrated circuits L in the wafer test and final test.

  FIG. 6 is a flowchart of tester search (see other figures as appropriate). The processing unit 15 of the control device 10 determines whether or not the tester search execution button 2111 has been operated by the user (step S61). If it has not been operated (No), this processing is repeated, and if it has been operated (Yes) ) Proceed to step S62.

  In step S62, the processing unit 15 extracts a tester model that clears the pin number condition. Specifically, the determination is made by comparing the user input of the item “number of pins of one device” in the device outline setting input area 2116 with the “number of pins” of each tester model in the tester model information 141. For example, if “128 pins or less” is selected (input) in the “number of pins of one device” item in the device overview setting input area 2116, tester models “A” to “E” in the tester model information 141 are extracted. Is done.

  Next, in step S63, the processing unit 15 further extracts a tester model that clears the maximum frequency condition from the tester models extracted in step S62. Specifically, the determination is made by comparing the user input of the item “wafer test maximum frequency (or final test maximum frequency)” in the test summary setting area 2117 with the “maximum frequency” for each tester model in the tester model information 141. To do. For example, if “20 MHz or less” is selected (input) in the “wafer test maximum frequency (or final test maximum frequency)” item in the test summary setting area 2117, the tester model “A” and “ B "is extracted.

  Subsequently, in step S64, the processing unit 15 further extracts tester models that satisfy the simultaneous measurable number condition from the tester models extracted in step S63. Specifically, the user input of the item “simultaneous wafer test measurement (or final test simultaneous measurement)” in the simultaneous measurement setting input area 2118 is compared with the “number of simultaneously measurable” for each tester model in the tester model information 141. To judge. For example, if “two” is selected (input) in the “wafer test simultaneous measurement (or final test simultaneous measurement)” item in the simultaneous measurement setting input area 2118, the tester model “B” in the tester model information 141 is selected. Extracted.

Next, in step S65, the processing unit 15 displays the fitness of each tester model in the tester model fitness display area 2115. In the above example, for example, the fitness of the tester model “B” is displayed as “◎”, the fitness of the tester model “A” is “◯”, and the fitness of the other tester models is displayed as “x”. .
In this way, it is possible to determine the fitness of each tester model with respect to user input and display the determination result.

  FIG. 7 is a flowchart for cost estimation (see other figures as appropriate). The processing unit 15 of the control device 10 determines whether or not the cost estimation execution button 2112 has been operated by the user (step S71). If it has not been operated (No), this process is repeated, and if it has been operated (Yes) ) Proceed to step S72.

  In step S72, the processing unit 15 determines whether or not there is a BOST. If there is no BOST (No), the process proceeds to step S74, and if there is a BOST (Yes), the process proceeds to step S73. Whether or not there is a BOST can be specifically determined from a user input (“None” or “Yes”) in the item “BOST” in the test summary setting area 2117.

  In step S <b> 73, the processing unit 15 displays a display indicating that an inexpensive tester model can be used due to the presence of the BOST and guidance of a specialized company that can handle the BOST, and ends the processing.

In step S74, the processing unit 15 selects a probe card. The detailed processing will be described with reference to FIG. FIG. 8 is a detailed flowchart of step S74 in FIG.
In step S81, the processing unit 15 extracts a probe card that clears the corresponding frequency condition. Specifically, determination is made by comparing the user input of the item “wafer test maximum frequency (or final test maximum frequency)” in the test summary setting area 2117 with the “corresponding frequency” for each probe card in the probe card information 142. To do. For example, if “40 MHz or less” is selected (input) in the “wafer test maximum frequency (or final test maximum frequency)” item in the test summary setting area 2117, all four types of probe cards in the probe card information 142 are stored. Extracted. However, extracting the “thin film probe” and the “carbon thin film probe” with the maximum frequency of “40 MHz or less” is not preferable from the viewpoint of cost and the like, and therefore, they may not be extracted.

  Next, in step S82, the processing unit 15 further extracts a probe card that clears the corresponding pin number condition from the probe cards extracted in step S81. Specifically, the user input of the item “number of pins of one device” in the device outline setting input area 2116 is compared with the “corresponding number of pins” of each probe card in the probe card information 142 for determination. For example, if “64 pins or less” is selected (input) in the “number of pins of one device” item in the device outline setting input area 2116, “cantilever” and “vertical probe” in the probe card information 142 are extracted. The

  Subsequently, in step S83, the processing unit 15 further extracts a probe card that clears the simultaneous measurement condition from the probe cards extracted in step S82. Specifically, the user input of the item “simultaneous measurement of wafer test (or simultaneous measurement of final test)” in the simultaneous measurement setting input area 2118 is compared with the item of “simultaneous measurement” of the probe card information 142 for determination. . For example, if “four” is selected (input) in the item “simultaneous measurement of wafer test (or simultaneous measurement of final test)” in the simultaneous measurement setting input area 2118, “vertical probe” in the probe card information 142 is extracted. Is done.

Returning to FIG. 7, in step S <b> 75, the processing unit 15 selects a tester board. The detailed processing will be described with reference to FIG. 9. FIG. 9 is a detailed flowchart of step S75 in FIG.
In step S91, the processing unit 15 determines whether or not the test classification (part 1) is burn-in evaluation, and if it is not burn-in evaluation (No), the process proceeds to step S93, and if it is burn-in evaluation (Yes), step S92. Proceed to Specifically, whether or not the test classification (part 1) is burn-in evaluation is determined by whether the user input of the item “test classification (part 1)” in the test summary setting area 2117 is “burn-in evaluation”. It can be done depending on whether or not.

  In step S92, the processing unit 15 refers to the tester board information 143, selects a burn-in board, and ends the process. This is because the only tester board that can support burn-in evaluation is burn-in board.

  In step S93, the processing unit 15 extracts a tester board that clears the corresponding frequency condition. Specifically, determination is made by comparing the user input of the item “wafer test maximum frequency (or final test maximum frequency)” in the test summary setting area 2117 and the “corresponding frequency” for each tester board in the tester board information 143. To do. For example, if “40 MHz or less” is selected (input) in the “wafer test maximum frequency (or final test maximum frequency)” item in the test summary setting area 2117, the four types of tester board information 143 are directly selected. All of the tester boards are extracted. However, for example, in consideration of cost, only “general board / manual wiring” and “custom board / pattern wiring” may be extracted.

  Subsequently, in step S94, the processing unit 15 further extracts a tester board that clears the simultaneous measurement condition from the tester boards extracted in step S93. Specifically, the user input of the item “simultaneous measurement of wafer test (or final test simultaneous measurement)” in the simultaneous measurement setting input area 2118 is compared with the item of “simultaneous measurement” in the tester board information 143 for determination. . For example, if “4” is selected (input) in the item of “simultaneous measurement of wafer test (or final test simultaneous measurement)” in the simultaneous measurement setting input area 2118, “general purpose board / manual wiring” in the tester board information 143. Are extracted.

Returning to FIG. 7, in step S <b> 76, the processing unit 15 selects a socket. The detailed processing will be described with reference to FIG. 10. FIG. 10 is a detailed flowchart of step S76 in FIG.
In step S101, the processing unit 15 determines whether or not the test classification (part 1) is burn-in evaluation, and if it is not burn-in evaluation (No), the process proceeds to step S103, and if it is burn-in evaluation (Yes), step S102. Proceed to Specifically, whether or not the test classification (part 1) is burn-in evaluation is determined by whether the user input of the item “test classification (part 1)” in the test summary setting area 2117 is “burn-in evaluation”. It can be done depending on whether or not.

  In step S102, the processing unit 15 refers to the socket information 144, selects a burn-in socket, and ends the process. This is because the only socket that can support burn-in evaluation is burn-in socket.

  In step S103, the processing unit 15 extracts a socket that clears the corresponding frequency condition. Specifically, determination is made by comparing the user input of the item “wafer test maximum frequency (or final test maximum frequency)” in the test summary setting area 2117 with the “corresponding frequency” for each socket in the socket information 144. For example, if “40 MHz or less” is selected (input) in the “wafer test maximum frequency (or final test maximum frequency)” item in the test summary setting area 2117, the four types of sockets in the socket information 144 are directly selected. Are all extracted. However, for example, in consideration of cost, only two of “general socket” and “high characteristic socket” may be extracted.

  Returning to FIG. 7, in step S77, the processing unit 15 calculates (approximate) the cost. Specifically, the processing unit 15 can obtain the wafer test cost by referring to the use cost (column) of the corresponding model in the tester model information 141. Further, the processing unit 15 can obtain the final test cost by referring to the usage cost (column) of the corresponding model in the tester model information 141.

Further, the processing unit 15 refers to the wafer jig manufacturing cost with reference to the development cost (column) of the corresponding probe card in the probe card information 142 and the development cost (column) of the corresponding tester board in the tester board information 143. It can be calculated by adding these values.
Further, the processing unit 15 refers to the final jig manufacturing cost with reference to the development cost (column) of the corresponding socket in the socket information 144 and the development cost (column) of the corresponding tester board in the tester board information 143. It can be calculated by adding the values.

  Finally, in step S78, the processing unit 15 performs screen display. Specifically, the processing unit 15 displays the wafer test cost and final test cost calculated in step S77 in the approximate cost display area 2114 (see FIG. 5) of the display unit 21, and displays the total as the total test cost. To do. Similarly, the processing unit 15 displays the wafer jig manufacturing cost and the final jig manufacturing cost calculated in step S77, and displays the total as the total jig manufacturing cost.

  Further, the processing unit 15 compares the value of each cost in the target cost input area 2113 with the value of each cost in the approximate cost display area 2114, and “the approximate cost is high” according to the comparison result. Please review the cost, the maximum test frequency, etc. "A warning message such as" It is difficult to manufacture jigs because of simultaneous measurement settings too much. "

Further, the processing unit 15 also performs display as shown in FIGS. 11A to 11C are display examples of a list screen of test conditions, testers, jigs, and the like.
The display screen 212 in FIG. 11A is a table showing test conditions and tools used when the approximate cost (the total test cost in the approximate cost display area 2114 in FIG. 5 and the total jig manufacturing cost) is 5 million yen or more ( List screen). For each item of maximum frequency, number of pins, tester model, number of simultaneous measurements, probe card, tester board, and socket, applicable is white background, non-applicable is dark background, if maximum frequency is reduced Applicable items are shaded with a light background, and only when “Burn evaluation” is selected, the background is shaded.

  By viewing this display, the user can use a wide variety of testers, jigs such as a variety of probe cards, tester boards, sockets, etc., depending on the estimated cost and test conditions (maximum frequency, number of pins, number of simultaneous measurements, etc.). Can be used or not, and can be appropriately selected. That is, the user can appropriately select various testers and jigs from conditions such as performance and cost. Here, the maximum frequency is “61 (MHz) ˜”, the number of pins is “257˜”, the tester models are “G” and “H”, the simultaneously measurable numbers are “4” and “16”, and the probe card is “ “Vertical probe”, “Thin film probe” and “Carbon thin film probe”, “Custom board / pattern wiring” and “Custom board / layer design” for tester board, “High performance socket” and “Custom socket” for socket respectively It has become.

  Since the display screens 213 to 216 are the same as the display screen 212, detailed description thereof is omitted. For example, the user can see from the display screen 213 that the tester model E cannot be used under the test conditions at that time, but the tester model E can be used if the maximum frequency is reduced.

  Further, the user can see at a glance how the tester models and jigs that can be used differ depending on the test conditions by looking at the display screens 214 to 216 displayed side by side.

  In this manner, according to the semiconductor integrated circuit development support system 1000, even a user who is not familiar with the tester or jig can select an appropriate tester or jig that meets the test conditions. At that time, tester and jig candidates are selected and displayed in consideration of BOST and burn-in evaluation, so that the user can more appropriately select the tester and jig.

This is the end of the description of the embodiments, but the aspects of the present invention are not limited to these.
For example, the present invention can be applied not only to LSIs but also to general semiconductor integrated circuits such as ICs (Integrated Circuits).
Test conditions for selecting tester and jig candidates include not only the maximum frequency, the number of pins, and the number of simultaneously measurable, but also die size, on-chip memory, presence of DFT, wafer Other conditions such as the total test pattern size may be considered.

Further, the socket may be displayed as a separate treatment if it has not been specially coated.
In addition, it is possible to accumulate information on test conditions obtained from the user and create a database to improve the accuracy and variation of the system.
In addition, specific configurations such as hardware and flowcharts can be appropriately changed without departing from the spirit of the present invention.

1 is an overall configuration diagram of a semiconductor integrated circuit development support system. It is the figure which showed basic composition, such as a tester. It is a block diagram of tester model information. It is each block diagram of probe card information, tester board information, and socket information. It is an example of the input screen of a display part. It is a flowchart of a tester search. It is a flowchart of cost estimation It is a detailed flowchart of step S74 of FIG. It is a detailed flowchart of step S75 of FIG. It is a detailed flowchart of step S76 of FIG. It is a display example of a list screen of test conditions, testers, jigs, and the like. It is a display example of a list screen of test conditions, testers, jigs, and the like. It is a display example of a list screen of test conditions, testers, jigs, and the like.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Test company 2 Circuit design company 4 Network 10 Control apparatus 14 Memory | storage part 15 Processing part 20 Terminal apparatus 21 Display part

Claims (4)

Development of a semiconductor integrated circuit comprising a control device owned by a tester and a tester of a semiconductor integrated circuit using a jig, and a terminal device owned by the test requester and connected to the control device via a network A support system,
The terminal device includes a display unit that displays an input screen for the client to input a test condition including a frequency condition of the test and a simultaneous measurement number of the semiconductor integrated circuits,
The control device includes a storage unit and a processing unit,
The storage unit stores jig information storing test conditions including a frequency condition that can be handled and a number of the semiconductor integrated circuits that can be simultaneously measured for each of the plurality of jigs.
Wherein the processing unit, if the requester has received said frequency condition and test conditions including the simultaneous measurement number input to the input screen of the display unit of the terminal device from the terminal device, by referring to the jig information extracts test satisfies the jig the received semiconductor integrated circuit development, characterized in that an instruction to display and enable a jig and the extracted to the display unit of the terminal device Support system. The jig is a probe card for inputting and outputting an electrical signal from the tester to the semiconductor integrated circuit,
The jig information further stores, as the test condition, the pin number condition of the semiconductor integrated circuit that can be handled for each of the plurality of probe cards,
Wherein the processing unit, if the requester has received said frequency condition input to the input screen of the display unit of the terminal device, the test conditions including the simultaneous measurement number and pin number Articles matter from the terminal device, the jig The device information is referred to, the probe card satisfying the received test condition is selected, and the display unit of the terminal device is instructed to display that the selected probe card is usable. The semiconductor integrated circuit development support system according to Item 1. The jig is a tester board for mounting the semiconductor integrated circuit on the tester,
The processor is
The requester is input to the input screen of the display unit of the terminal device, whether the information burn-in test or not a test carried out at elevated temperature, the test condition from the terminal apparatus including the frequency condition and the simultaneous measurement number When received
When it is received that it is a burn-in test, refer to the jig information, select a tester board for burn-in test among a plurality of tester boards,
When receiving a message indicating non-burn-in test, with reference to the jig information, select the test condition is satisfied tester board with the received,
The semiconductor integrated circuit development support system according to claim 1, wherein at any time, the display unit of the terminal device is instructed to display that the selected tester board is usable. The jig information further stores development cost information for each of the plurality of jigs,
The processor is
When the client receives from the terminal device a test condition including the frequency condition and the simultaneous measurement number input on the input screen of the display unit of the terminal device,
Of the development cost information obtained by referring to the jig information, the development cost information of the extracted jig is used as an approximate value of the production cost of the jig, and the jig is produced for the display unit of the terminal device. The semiconductor integrated circuit development support system according to claim 1, wherein an instruction to display an approximate cost value is displayed.

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