JP5044595B2 - A / D converter and control method thereof - Google Patents

Description

  The present invention relates to an A / D converter applied to an input circuit of a digital device, and more particularly to a pipeline type A / D converter (A / D converter) operating at high speed and a control method thereof.

As a conventional pipeline type A / D converter, for example, the one shown in the following Patent Document 1 has been proposed.
FIG. 11 is a block diagram of a conventional pipeline A / D converter described in Patent Document 1. In FIG.
This pipeline type A / D converter converts an analog input signal Ain into an N-bit digital output Dout, and therefore, an input sample hold circuit S / H that samples and holds the analog input signal Ain and a bit for determining each bit. A series of k stages S1, S2,... Sk and a memory 102 for storing an n-digit digital value dj (j is 1, 2,... K) determined in each stage S1, S2,. And an arithmetic circuit 101 for calculating an A / D conversion value Dout of the analog input signal Ain based on the digital value dj (j is 1, 2,... K) stored in the memory 102.

The sample hold circuit S / H and the circuit 1103 of the stage S1 are circuits that output an analog output Vout based on an analog continuous input signal Ain as shown in FIG.
The circuit 1103 then transfers the value based on Ain to the stage S1, and the sample cap Cap 106c for transferring the value to the stage S1, and the output based on the discretized Ain output from the sample hold circuit S / H to the subsequent stage. It includes sample caps CAP 106a and Cap 106b for transferring, and an A / D conversion circuit 104 for A / D converting the values based on the discretized Ain. The circuit 1103 further includes a multi-value output circuit 105 that distributes the output of the sample cap Cap 106b to predetermined multi-value outputs, an amplifier 107 for transferring the value to the stage S1 based on Ain, and a sample hold circuit S. And an amplifier 108 that amplifies the value of / H based on the discretized Ain with a predetermined gain G corresponding to the number of bits of the digital output of the A / D conversion circuit 104.

In the pipeline type A / D converter, the gain G of the amplifier 107 must be 2 (n-1) when the number of digits of the input digital output signal dj of the A / D conversion circuit 104 is n. .
Note that reference numerals SW305a, SW305b, SW305c, SW305d, SW305e, SW305f, SW305g, SW305h, SW1205k, SW1205l, SW1205m, and SW1205n in FIG.

In FIG. 12, symbols φ1 and φ2 are non-overlapping clocks having a section in which the signal value is not High (H). When the clock is H, the analog switches SW305a to SW1205n are turned on, When the signal value is Low (L), the analog switches SW305a to SW1205n are turned off.
When the clock φ2 is H, the sample hold circuit S / H performs a sample operation, and the stage S1 performs a hold operation.

  That is, when the clock φ2 is H, the switch SW1205m is turned on, and the analog continuous input signal Ain is guided to the sample cap cap106c. Further, since the switch SW1205n is turned on, the sample cap cap106c is charged and the sample operation is performed. When the clock φ2 is H, the sample caps caps 106a and 106b perform an operation on the charges stored in the summing node 312 one cycle ago by turning on the switches SW305b and 305e, and the next stage. Transferred to S2. As a result of the transfer, the analog output signal Vout is output to the stage S2 as a target value.

On the other hand, when the clock φ1 is H, the sample hold circuit S / H performs a hold operation, and the stage S1 performs a sample operation.
That is, when the clock φ1 is H, the charge sampled in the sample cap cap 106c in the clock φ2 is transferred to the stage S1 by turning on the switch SW1205l. When the clock φ1 is H, the switch SW305c is turned on, and the charge sampled in the sample cap cap 106c in the clock φ2 is guided to the sample cap cap 106a. Further, the switch SW305d is turned on, and the charge sampled in the sample cap cap 106c in the clock φ2 is guided to the sample cap Cap 106b. Further, since the switch SW305a is turned on, the sample caps caps 106a and 106b are charged and the sample operation is performed. Further, the switch SW305k is turned on, and the charge sampled in the sample cap cap 106c in the clock φ2 is guided to the A / D conversion circuit 104.

FIG. 12 illustrates the configuration of the stage S1 including the 1.5-bit A / D conversion circuit 104. In the case of the (m + 0.5) bit A / D conversion circuit (m is a natural number), the comparator is (( m + 1) to the power of -2), and the reference voltage must be (± 1, ± 3, ± 5,..., ± (2 to the (m + 1) th power −3)) / (2 to the (m + 1) th power) I must.
In the case of an (m + 0.5) bit A / D conversion circuit (m is a natural number), a circuit configuration 310 including switches SW305d to 305h, a sample cap cap106b, and a multi-value output circuit 105 is expressed as (2 m − 1) The node 311 and the summing node 312 shown in the figure must be connected in parallel.

  The circuit configuration of stage S2, stage S3,..., Stage Sk is all the same as that of stage S1, and clocks φ1, φ2 for operating analog switches SW305a to SW1205n are odd-numbered stages of stage 1, stage 3,. The even-numbered stages of stage 2, stage 4,... Are obtained by changing the clock φ1 of stage S1 to clock φ2 and the clock φ2 to clock φ1.

JP 2000-13232 A

  As described above, the conventional pipeline type A / D converter outputs the value based on the analog continuous input signal Ain which is the output of the sample hold circuit S / H and is discretized by the sample cap Cap 106c, to the sample cap cap 106a of the stage S1. , 106b and the A / D conversion circuit 104. In particular, when the analog continuous input signal Ain includes a high frequency band component, it is necessary to discretize the analog continuous input signal Ain by the sample hold circuit S / H.

Therefore, in the conventional pipeline type A / D converter, the sample hold circuit S / H is necessary. By providing such a sample hold circuit S / H, the power consumption of the entire converter and the layout area can be reduced. There is an inconvenience that it causes increase and noise.
Accordingly, the present invention has been devised to solve these problems, and an object of the present invention is to provide a novel pipeline type A / D converter that does not require a sample hold circuit and a control method thereof. is there.

In order to solve the above problems, the first invention
A plurality of stages are provided, and the stage inputs an analog input signal, converts it into a digital signal and outputs it, and outputs an analog output signal generated by the digital signal and the analog input signal to another stage in the subsequent stage. An A / D converter that outputs to
At least the first stage of the plurality of stages is
A sampling circuit that inputs and samples the analog input signal from one end of a sampling capacitor , a timing selector switch that determines a sampling operation timing of the sampling circuit, and is connected to the other end of the sampling capacitor and is sampled by the sampling circuit A / D conversion circuit that converts the analog input signal into the digital signal and outputs the same, and a sampling value adjustment circuit that adjusts the value of the analog input signal sampled by the sampling circuit in accordance with the value of the digital signal And transfer means for outputting the analog signal adjusted by the sampling value adjusting circuit to the other stage as the analog output signal .

The second invention is
In the first invention, the first stage further includes a summing node to which the sampling capacitor is connected and which stores the analog input signal sampled by the sampling circuit, and the A / D conversion circuit includes the summing node It is an A / D converter characterized by A / D converting the voltage concerning.
The third invention is
In the first or second aspect of the invention, construction of the subsequent stage, an A / D converter, characterized in that it is the same as the configuration of the first stage of the stage.

The fourth invention is:
A pipeline type A / D converter control method including a plurality of stages for performing A / D conversion and D / A conversion, wherein at least the first stage of the plurality of stages is processed by analog input. A sample phase for inputting a signal from one end of a sampling capacitor of a sampling circuit by a timing selector switch, and an A / D conversion circuit for connecting the analog input signal sampled by the sampling circuit to the other end of the sampling capacitor The comparator phase for converting into a digital output signal by adjusting the value of the analog input signal sampled by the sampling circuit in accordance with the value of the digital output signal , and adjusting the analog input signal after the other stage In order of the hold phase output to the Repeating Te is a control method of an A / D converter according to claim.

Since the present invention performs discretization such as sampling of the analog continuous input signal Ain, which has been performed by the conventional sample-and-hold circuit S / H, at the first (first stage) stage, it is like a conventional A / D converter. It is not necessary to use a simple sample and hold circuit.
As a result, an increase in power consumption, layout area, and noise can be avoided, so that compactness, power saving, and noise reduction can be achieved.

1 is a block diagram showing an embodiment of an A / D converter 100 according to the present invention. It is a figure for demonstrating the calculation which calculates the digital output signal Dout. It is a block diagram which shows the structure of the first stage FS1, and its sample phase (T1: Sample phase). 2 is a configuration diagram showing an A / D conversion circuit 104. FIG. It is a timing chart for demonstrating the output timing of clock (phi) 1, (phi) 2, (phi) S, and (phi) C. It is a block diagram which shows the structure of the first stage FS1, and its comparison phase (T2: Compare phase). It is a block diagram which shows the structure of the first stage FS1, and its hold phase (T3: Hold phase). It is a block diagram which shows the structure of the first stage FS1 which concerns on other embodiment, and its sample phase (T1: Sample phase). It is a block diagram which shows the structure of the first stage FS1 which concerns on other embodiment, and its comparison phase (T2: Compare phase). It is a block diagram which shows the structure of the first stage FS1 which concerns on other embodiment, and its hold phase (T3: Hold phase). It is a block diagram which shows an example of the conventional pipeline type A / D converter. It is a block diagram which shows the relationship between the sample hold circuit S / H of the conventional pipeline type A / D converter, and the first stage S1.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.
(First embodiment)
(overall structure)
FIG. 1 is a block diagram showing a first embodiment of a pipeline type A / D converter 100 according to the present invention.
As shown in the figure, the A / D converter 100 converts an analog continuous input signal Ain into an N-bit digital output signal Dout and outputs it.
The A / D converter 100 includes k stages FS1, S2,... Sk connected in cascade to determine each bit, and an n-digit digital output signal dj (determined in each of the stages FS1 to Sk. j is a memory 102 for storing 1 to k), and an arithmetic circuit 101 for calculating a digital output signal Dout from an A / D conversion value of the analog continuous input signal Ain based on the digital output signal dj stored in the memory 102 Consists mainly of.

The stages FS1 to Sk are connected in series to each other in multiple stages, and send an n-digit digital output signal dj to the memory 102 based on the input analog input signal Vin. In each of the stages FS1 to Sk, the input analog input signal Vin is converted based on the D / A conversion result of the digital output signal dj, and sequentially output to the subsequent stage as the analog output signal Vout.
The memory 102 inputs and stores an n-digit digital output signal dj from each of the k stages FS <b> 1 to Sk. For this reason, the memory 102 is a semiconductor memory or the like that can store at least k addresses of n bits.
The arithmetic circuit 101 performs an operation based on the digital output signal dj stored in the memory 102 and outputs an N-digit digital output signal Dout.

The calculation for calculating the digital output signal Dout is performed as follows.
That is, the arithmetic circuit 101 adds the most significant digit of the digital output dk of the stage Sk and the least significant digit of the digital output d (k−1) of the stage S (k−1) in a binary system. Further, based on the result of addition (added value), the most significant digit of d (k−1) and the least significant digit of the digital output d (k−2) of stage S (k−2) are also binary-coded. Add by the method.
Such processing is repeated to add up to the least significant digit of the digital output d1 of the stage FS1 and the most significant digit of the digital output d2 of the stage S2. The final result of the addition is output as a digital output signal Dout.

FIG. 2 is a diagram for illustrating an operation for calculating such a digital output signal Dout. In the example of FIG. 2, there are four stages, and each stage outputs 3-digit digital outputs d1 to d4 to the memory 102 shown in FIG. More specifically, the values of the digital outputs d1 to d4 are determined as follows.
d1 = 001, d2 = 100, d3 = 101, d4 = 111
In the example of FIG. 2, as a result of adding the most significant digit and the least significant digit of the digital output output by the adjacent stage, a value of “010011011” is obtained as the digital output signal Dout.

(Circuit configuration of stage FS1)
Next, FIG. 3 shows a circuit configuration of the stage FS1 located at least in the first stage among the k stages FS1 to Sk described above, and in the pipeline type A / D converter 100 of the present invention. This is a new and characteristic part. Since each of the stages FS1 to Sk has the same circuit configuration, the description of the stage FS1 shown in FIG. 3 is replaced with the description of all the stages FS1 to Sk. Therefore, the inputs of the stages S2 to Sk located after the first stages FS1 to Sk are obtained by replacing the analog continuous input signal Ain in FIG. 3 with the analog discrete input signal Vin discretized in the preceding stage. Further, the same structure as that of the prior art may be used for the circuit configuration of an arbitrary stage Sk.

As shown in the figure, the stage FS1 inputs an analog continuous input signal Ain and outputs a digital output signal d1, and outputs an analog discrete output signal Vout1 to a subsequent stage S2.
The stage FS1 includes sample caps (sampling capacitors) Cap 306a and Cap 306b that sample the input analog continuous input signal Ain, an A / D conversion circuit 302 that converts the analog input signal Ain into a digital output signal d1, and a sample cap 306b. A multi-value output circuit 304 that distributes the output of the signal to a predetermined multi-value output, and an amplifier 303 that amplifies a value based on the analog input signal Ain with a predetermined gain G corresponding to the number of bits of the digital output of the A / D conversion circuit And is composed mainly of. In general, in a pipeline type A / D converter, when the number of digits of the digital output signal dj of the input A / D conversion circuit 104 is n, the gain G of the amplifier 303 is 2 to the (n−1) th power. And shall be.

  Further, the stage FS1 includes analog switches SW305c and 305d that open and close according to the clock φ1 output from the control circuit 301, analog switches SW305b and 305e that open and close according to the clock φ2 output from the control circuit 301, and the control circuit. Analog switches SW305a and 305i that open and close in accordance with a clock φS output from 301 and analog switches SW305j that open and close in accordance with a clock φC output from the control circuit 301 are provided.

The multi-value output circuit 304 converts the digital output signal d1 output from the A / D conversion circuit 302 into an analog signal, and functions as a D / A sub-converter. This multi-value output circuit The analog switches SW305f, 305g, and 305h included in 304 are opened and closed according to the output result of the A / D conversion circuit 302.
As shown in FIG. 4, the A / D conversion circuit 302 receives the sampling trigger φC output from the control circuit 301, and in synchronization with the fall of the sampling trigger φC, −AinV and a preset reference voltage (1 / 4) Vr and (-1/4) Vr are compared, and the result is output as a digital output signal d1. As described above, the digital output signal d1 is input to the multi-value output circuit 304 to control the analog switches SW305f to 305h.

Here, FIG. 4 shows the configuration of a 1.5-bit A / D conversion circuit using two comparators 401 and 402, and (m + 0.5) bit A / D converter (m is a natural number). ) Requires 2 to the (m + 1) th power −2, and the reference voltage is (± 1, ± 3, ± 5,..., ± (2 to the (m + 1) th power −3)) / (2 to the power of (m + 1)).
A portion indicated by reference numeral 307 in the figure is a summing node and can store charges.
In this embodiment, the control circuit 301 is further provided, and the control circuit 301 outputs four types of clocks φ1, φ2, φS, and φC for controlling the opening and closing of the analog switches SW.

FIG. 5 is a timing chart for explaining the output timings of the clocks φ1, φ2, φS, and φC. The vertical axis indicates signal values High (H) and Low (L), and the horizontal axis indicates time t. Yes. 5A is a timing chart of the clock φ1, FIG. 5B is a timing chart of the clock φ2, FIG. 5C is a timing chart of the clock φS, and FIG. 5D is a timing chart of the clock φC. Each is shown.
In the present embodiment, a period in which the clock φS is H is a sample phase, and a period in which the clock φC is H is a compare phase. Further, a section in which the clock φ2 is H is a hold phase.

The timings T1, T2, and T3 shown in the figure all indicate the operation timing of the stage FS1 according to the present embodiment, and T1 is an arbitrary timing included in the sampling phase. T2 is an arbitrary timing included in the comparison phase. T3 is an arbitrary timing included in the hold phase.
In the present embodiment, the rising of the clock φ1 and the rising of the clock φS are simultaneous, and the falling of the clock φ1 and the falling of the clock φC are simultaneous. The clock φS and the clock φC are non-overlapping clocks that do not become H at the same time. Note that the clocks φ1 and φ2 are also non-overlapping clocks that do not simultaneously become H as in the prior art.

(Operation)
Next, the operation of the stage FS1 having such a configuration will be described.
As shown in FIG. 3, the analog continuous input signal Ain is guided to the sample cap Cap 306a when the analog switches SW305i and 305c are turned on, and is guided to the sample cap Cap 306b when the analog switches SW305i and 305d are turned on. The sample caps Cap 306a and 306b charge the analog continuous input signal Ain and perform sampling (also referred to as sample operation). The sampled charge is stored in the summing node 307 .

Next, with respect to the stored charges, the analog switches SW305a and 305i are turned off by turning on the analog switch SW305j in the comparison phase (clock φC is H), so that the voltage of the summing node 307 becomes −AinV.
In the comparison phase, the digital output signal d1 is converted by the A / D converter 302. The digital output signal d1 is output to the memory 102 shown in FIG. 1, is branched, and is led to the switches SW 305f to 305h via the multi-value output circuit 304.

Here, the A / D converter 302 performs a calculation by a known method to determine the value of the digital output signal d1.
In the multi-value output circuit 304, the analog switches SW305f to 305h are turned on or off according to the value of the digital output signal d1. By turning on / off the analog switches SW305f to 305h, the multi-value output circuit 304 adjusts the analog discrete output signal Vout1 to a value within a range between a preset upper limit value and lower limit value.

  In the example shown in FIG. 3, the analog switch SW305f is turned on and a voltage value (VC + Vr) V (VC: analog common ground voltage) (Vr: maximum input range of Ain, AinP, AinN, Vr> 0) is output. Connected. Further, when the analog switch SW305g is turned on, it is connected to a terminal that outputs a voltage value (VC) V, and when the analog switch SW305h is turned on, it is connected to a terminal that outputs a voltage value (VC−Vr) V.

Next, the operation of the stage FS1 having such a configuration will be described in the order of timings T1 to T3 shown in FIG.
<T1: Sample phase>
First, FIG. 3 shows the timing of T1 shown in FIG. 5, that is, the state of the stage FS1 in the sample phase.
In this sample phase, as shown in FIG. 5, since only the clocks φ1 and φS are H, the analog switches SW305i and SW305c are turned on, and the analog continuous input signal Ain is guided to the sample cap Cap 306a. The switch SW305d is also turned on, and the analog continuous input signal Ain is guided to the sample cap Cap 306b. Further, since the switch SW305a is turned on, the sample caps 306a and 306b are charged and the sample operation is performed.

<T2: Comparative phase>
Next, FIG. 6 shows the timing of T2 in FIG. 5, that is, the state of the stage FS1 in the comparison phase.
In this comparison phase, as shown in FIG. 5, only the clocks φ1 and φC are H, so that the analog switches SW305a and 305i are turned off. Therefore, the charge of the analog continuous input signal Ain sampled in the sample caps Cap 306 a and 306 b is stored and determined in the summing node 307. Further, since the analog switch SW305j is turned on, the voltage of the summing node 312 is inverted to become -AinV, and the A / D conversion circuit 104 performs an operation on this -AinV by a known method, and the digital output signal d1 The value of is determined. The digital output signal d1 is output to the memory 102 shown in FIG. 1, and branched and guided to the analog switches SW305f to 305h via the multi-value output circuit 304.

In the multi-value output circuit 304 , the analog switches SW305f to 305h are turned on or off according to the value of the digital output signal d1. Then, by turning on / off the analog switches SW305f to 305h, the multi-value output circuit 304 adjusts the analog discrete output signal Vout1 to a value within a range between a preset upper limit value and lower limit value.
In the example shown in the figure, the analog switch SW305f of the multi-value output circuit 304 is turned on and connected to a terminal that outputs a voltage value (VC + Vr) V. Further, when the analog switch SW305g is turned on, it is connected to a terminal that outputs a voltage value (VC) V, and when the analog switch SW305h is turned on, it is connected to a terminal that outputs a voltage value (VC−Vr) V.

<T3: Hold phase>
Next, FIG. 7 shows the timing of T3 in FIG. 5, that is, the state of the stage FS1 in the hold phase.
In this hold phase, the charge stored in the summing node 307 is calculated by a known method using the sample caps Cap 306a and 306b and transferred to the subsequent stage S2. As a result of the transfer, the analog output signal Vout1 is output as a target value to the subsequent stage S2.
Thereafter, the processing is repeated by sequentially switching the sample phase, the comparison phase, and the hold phase according to the clocks φ1, φ2, φS, and φC that are output at the timing shown in FIG.

  The above is the description along the time series of the operation of the stage FS1. Note that T4 shown in FIG. 5 is the rising time of the clock φ2, and the hold phase after T4 becomes the sample phase in the subsequent stage S2 shown in FIG. The even-numbered stages S2, S4,... Have the same circuit configuration as in FIG. 3, and the timing chart of the clock for driving the analog switch has a rise time of φ1 as T5, and φ1, φ2, φH, φS, and φC. All the relative relations to are driven by a clock similar to that in FIG. 5 and operate in the same manner as in this embodiment. The odd-numbered stages S3, S5,... Have the same circuit configuration as in FIG. 3, and the timing charts of clocks for driving the analog switches are all driven by the same clocks as in FIG. Works like a form.

(effect)
As described above, the pipeline type A / D converter 100 of the present invention is such that at least the first stage FS1 directly inputs the analog continuous input signal Ain and performs discretization such as sampling. There is no need to use a sample-and-hold circuit such as a / D converter.
As a result, an increase in power consumption, layout area, and noise can be avoided, so that compactness, power saving, and noise reduction can be achieved.
Further, since the input path of the stage FS1 is one path of the sample caps Cap 306a and 306b, there is an effect that the trigger for sampling the analog continuous input signal Ain is only the analog switch SW305a (the analog switch SW1205K in FIG. Become).

  3, 6, and 7, the configuration of the stage FS <b> 1 including the 1.5-bit A / D conversion circuit 302 has been described, but in the case of (m + 0.5) bit A / D conversion circuit (m is a natural number) Shows a circuit configuration 310 including analog switches SW305d to 305h, a sample cap Cap306b, and a multi-value output circuit 304 between the node 311 and the summing node 307 shown in the figure by (2 to the power of m−1). Will be connected in parallel.

  Further, the sampling capacitor and the sampling circuit constituting the A / D converter of the present invention shown in the means for solving the problems correspond to the sample caps Cap 306a, 306b, etc. shown in FIG. , Analog switches SW305i, SW305c, SW305a, and the like. Similarly, the inverting circuit corresponds to the summing node 307, the analog switch SW305j, and the like, and the A / D conversion circuit corresponds to the A / D conversion circuit 302 and the like. Further, the sampling value adjustment circuit corresponds to the multi-value output circuit 304 and the like, and the transfer switch corresponds to the summing node 307, the sample caps Cap 306a and 306b, the amplifier 303, and the like.

(Second Embodiment)
Next, FIGS. 8 to 10 show a second embodiment of the A / D converter 100 according to the present invention.
In contrast to the first embodiment of the present invention described above that handles a single-ended signal, this embodiment handles a differential signal. Therefore, the overall configuration is the same as in the first embodiment, the input signal Ain is equal to the difference between the differential input signals AinP and AinN, and the output signal Vout is equal to the difference between the differential output signals VoutP and VoutN.

(Circuit configuration of stage FS1)
FIG. 8 is a diagram showing a circuit configuration of the stage FS1 of the differential pipeline type A / D converter 100 according to the present embodiment. Since each of the stages FS1 to Sk shown in FIG. 1 has the same circuit configuration, the description of the stage according to FIG. 8 is replaced with the description of all the stages FS1 to Sk. Here, the inputs of the stages S2 to Sk are obtained by replacing the analog differential continuous input signals AinP and AinN in FIG. 8 with the analog discrete input signals VinP and VinN discretized in the previous stage. Further, the same structure as that of the prior art may be used for the circuit configuration of an arbitrary stage Sk.
As shown in FIG. 8, the stage FS1 inputs analog differential continuous input signals AinP and AinN, outputs a digital output signal d1, and outputs analog differential discrete output signals Vout1P and Vout1N to the subsequent stage 2. It is a circuit to output.

  For this purpose, the stage FS1 includes sample caps Cap 806a and 806b for sampling the input analog continuous input signal AinP, sample caps Cap 806c and 806d for sampling the input analog continuous input signal AinN, and the analog input signal AinP. An A / D conversion circuit 802 that converts the difference AinP-AinN of the analog input signal AinN into a digital output signal d1, a multi-value output circuit 804 that distributes the output of the sample cap Cap 806b to a predetermined multi-value output, and an output of the sample cap Cap 806d A multi-value output circuit 808 that distributes the signal to a predetermined multi-value output, and the number of bits of the digital output of the A / D converter 802 for a value based on the difference AinP-AinN between the analog input signal AinP and the analog input signal AinN And a amplifier 803 for amplifying with a predetermined gain G corresponding. In the pipeline type A / D converter, the gain G of the amplifier 803 is set to 2 to the (n-1) th power when the number of digits of the input digital output signal dj of the A / D converter 802 is n. There must be.

  The stage FS1 includes analog switches SW805c, 805d, 805m, and 805n that open and close according to the clock φ1, analog switches SW805b, 805e, 805l, and 805o that open and close according to the clock φ2, and an analog switch SW805a that opens and closes according to the clock φS. , 805i, 805k, and 805s, and analog switches SW805j and 805t that open and close in accordance with the clock φC.

The analog switches SW805f, 805g, and 805h included in the multi-value output circuit 804 are opened / closed according to the output result of the A / D converter 802. Similarly, the analog switches SW805p, 805q, and 805r included in the multi-value output circuit 808 are also opened / closed according to the output result of the A / D converter 802.
In this embodiment, the control circuit 301 is further provided as in the first embodiment, and the clocks φ1, φ2, φS, and φC are output by the control circuit 301. Further, portions denoted by reference numerals 807 and 809 in the figure are summing nodes, and can store charges. The multi-value output circuits 804 and 808 are configured to convert the digital output signal d1 into an analog signal, and function as a D / A sub-converter.

When Ain = AinP−AinN in FIG. 4, the A / D converter 802 is an example of the A / D converter 802 in the first embodiment, which is an example of the A / D converter circuit 302 in the first embodiment. Will be the same.
That is, the A / D converter 802 receives the sampling trigger φC, and is synchronized with the falling edge of the sampling trigger φC-(AinP-AinN) and a preset reference voltage (1/4) Vr, (-1/4) Vr is compared, and the result is output as a digital output signal d1. The digital output signal d1 is input to the multi-value output circuit 804 to control the SWs 805f to 805h. The digital output signal d1 is input to the multi-value output circuit 808 to control the SWs 805p to 805r.

(Operation)
Next, the operation of the stage SF1 according to the present embodiment will be described in the order of timings T1 to T3 shown in FIG.
<T1: Sample phase>
First, FIG. 8 shows the timing of T1 shown in FIG. 5, that is, the state of the stage FS1 in the sample phase.
In this sample phase, as shown in FIG. 5, since only the clocks φ1 and φS are H, the analog switches SW805i and 805c are turned on, and the analog continuous input signal AinP is guided to the sample cap Cap806a. Further, the analog switches SW805i and 805d are turned on, and the analog continuous input signal AinP is guided to the sample cap Cap 806b. Furthermore, since the analog switch SW805a is turned on, the sample caps Cap806a and 806b are charged and the sample operation is performed.

  In this sample phase, the analog switches SW805s and 805m are further turned on, and the analog continuous input signal AinN is guided to the sample cap Cap806c. Further, the analog switches SW805s and 805n are turned on, and the analog continuous input signal AinN is guided to the sample cap Cap806d. Furthermore, since the analog switch SW805k is turned on, the sample caps Cap806c and 806d are charged and the sample operation is performed.

<T2: Comparative phase>
Next, FIG. 9 shows the timing of T2 in FIG. 5, that is, the state of the stage FS1 in the comparison phase.
In this comparison phase, since only the clocks φ1 and φC are H as shown in FIG. 5, the analog switches SW805a, 805i, 805k, and 805s are turned off. Therefore, the charges of the analog continuous input signal AinP sampled in the sample caps Cap 806a and 806b are stored and determined in the summing node 807, and the charges of the analog continuous input signal AinN sampled in the sample caps Cap 806c and 806d are Saved and confirmed in 809.
Further, the analog switches SW805j and 805t are turned on. For this reason, the voltage at the summing node 807 becomes −AinPV, the voltage at the summing node 809 becomes −AinNV, and the difference − (AinP−AinN) V is calculated by a known method by the A / D converter 802. The value of the digital output signal d1 is determined.

<T3: Hold phase>
Next, FIG. 10 shows the timing of T3 in FIG. 5, that is, the state of the stage FS1 in the hold phase.
In this hold phase, the charge stored in the summing node 807 is calculated by a known method in the sample caps Cap 806 a and 806 b and transferred to the stage 2. The charge stored in the summing node 809 is calculated by a known method using the sample caps Cap 806 c and 806 d and transferred to the stage 2. As a result of the transfer, the analog output signals Vout1P and Vout1N are output to the stage 2 as target values.

  8, 9, and 10 have described the configuration of the stage 1 including the 1.5-bit A / D converter 802. In the case of an (m + 0.5) bit A / D converter (m is a natural number), (2 (m + 1) power −2) comparators are required, and the reference voltages are (± 1, ± 3, ± 5, ..., ± (2 to the (m + 1) th power −3)) / (2 to the (m + 1) th power). In the case of an (m + 0.5) bit A / D converter (m is a natural number), a circuit configuration 812 including SWs 805d to 805h, a sample cap 806b, and a multi-value output circuit 804 is expressed as (2 to the power of m−1). ), The node 813 and the summing node 807 shown in the figure must be connected in parallel. In the case of an (m + 0.5) bit A / D converter (m is a natural number), a circuit configuration 814 including SWs 805n to 805r, a sample cap 806d, and a multi-value output circuit 808 is expressed as (2 to the power of m−1). ), The node 815 and the summing node 809 shown in the figure must be connected in parallel.

(effect)
In the present embodiment having such a configuration, the sample hold circuit S / H is not required as in the first embodiment, so that power consumption, layout area, and noise can be reduced.
Similarly, an effect that the input path of the stage FS1 of the analog input signal AinP is one path of the sample caps Cap 806a and 806b, in other words, an effect that the trigger for sampling the analog continuous input signal AinP is only the analog switch SW805a is obtained. . Similarly, an effect that the input path of the analog input signal AinN in the stage 1 is also one path of the sample caps Cap 806c and 806d, in other words, an effect that the trigger for sampling the analog continuous input signal AinN is only the analog switch SW805k is obtained. .

  The sampling capacitor and the sampling circuit constituting the A / D converter of the present invention shown in the means for solving the problems correspond to the sample caps Cap 806a, 806b, 806c, 806d, etc. shown in FIG. The timing switch corresponds to the analog switches SW805i, SW805c, SW805a, SW805s, SW805m, SW805k, and the like. Similarly, the inverting circuit corresponds to the summing nodes 807 and 809, the analog switches SW805j and SW805t, and the A / D conversion circuit corresponds to the A / D conversion circuit 802 and the like. Further, the sampling value adjustment circuit corresponds to the multi-value output circuits 804 and 808, and the transfer switch corresponds to the summing nodes 807 and 809, the sample caps Cap 806a to 806d, the amplifier 803, and the like.

DESCRIPTION OF SYMBOLS 100 ... A / D converter 101 ... Arithmetic circuit 102 ... Memory 301 ... Control circuit 302 ... A / D conversion circuit 303 ... Amplifier 304 ... Multi-value output circuit 307 ... Summing node 311 ... Node 401, 402 ... Comparator SW305a-SW305j ... Analog switch Cap 306a, Cap 306b ... Sample cap Ain ... Analog input signal d1-dk ... Digital output signal FS1 ... First stage S2-Sk ... Stage φ1, φ2, φS, φC ... Clock

Claims (4)

Multiple stages are provided,
The stage receives an analog input signal, converts it to a digital signal and outputs it, and outputs an analog output signal generated by the digital signal and the analog input signal to another stage after the A / D. A converter,
At least the first stage of the plurality of stages is
A sampling circuit that inputs and samples the analog input signal from one end of a sampling capacitor;
A timing changeover switch for determining a sampling operation timing of the sampling circuit;
An A / D conversion circuit connected to the other end of the sampling capacitor and converting the analog input signal sampled by the sampling circuit into the digital signal and outputting the digital signal;
The value of the analog input signal sampled at the sampling circuit, the sampling value adjusting circuit for adjusting in response to the value of the digital signal,
A transfer means for outputting the analog signal adjusted by the sampling value adjusting circuit to the other stage as the analog output signal ;
An A / D converter comprising: The first stage further includes a summing node to which the sampling capacitor is connected and which stores the analog input signal sampled by the sampling circuit,
The A / D converter according to claim 1, wherein the A / D converter circuit performs A / D conversion on a voltage applied to the summing node. 3. The A / D converter according to claim 1, wherein the configuration of the subsequent stage is the same as the configuration of the first stage. 4. A method for controlling a pipelined A / D converter having a plurality of stages for performing A / D conversion and D / A conversion,
Processing of at least the first stage among the plurality of stages,
A sample phase in which an analog input signal is sampled by inputting from one end of a sampling capacitor of a sampling circuit by a timing selector switch,
A comparator phase for converting the analog input signal sampled by the sampling circuit into a digital output signal by an A / D conversion circuit connected to the other end of the sampling capacitor ;
The value of the analog input signal sampled by the sampling circuit is adjusted in accordance with the value of the digital output signal, and the adjusted analog input signal is repeatedly switched in the order of the hold phase that is output to the other stage. A method for controlling an A / D converter.

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